LIB := $(obj)lib$(SOC).a
COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
+COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
+COBJS-$(CONFIG_PCI) += sc520_pci.o
+
SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
/* stuff specific for the sc520,
* but idependent of implementation */
-#include <config.h>
#include <common.h>
-#include <config.h>
-#include <pci.h>
-#ifdef CONFIG_SYS_SC520_SSI
-#include <asm/ic/ssi.h>
-#endif
#include <asm/io.h>
-#include <asm/pci.h>
#include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
*
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
- * void pci_sc520_init(struct pci_controller *hose)
- *
- * void reset_timer(void)
- * ulong get_timer(ulong base)
- * void set_timer(ulong t)
- * void udelay(unsigned long usec)
- *
*/
static u32 mmcr_base= 0xfffef000;
return dram_present;
}
-
-#ifdef CONFIG_PCI
-
-
-static struct {
- u8 priority;
- u16 level_reg;
- u8 level_bit;
-} sc520_irq[] = {
- { SC520_IRQ0, SC520_MPICMODE, 0x01 },
- { SC520_IRQ1, SC520_MPICMODE, 0x02 },
- { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
- { SC520_IRQ3, SC520_MPICMODE, 0x08 },
- { SC520_IRQ4, SC520_MPICMODE, 0x10 },
- { SC520_IRQ5, SC520_MPICMODE, 0x20 },
- { SC520_IRQ6, SC520_MPICMODE, 0x40 },
- { SC520_IRQ7, SC520_MPICMODE, 0x80 },
-
- { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
- { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
- { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
- { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
- { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
- { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
- { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
- { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
-};
-
-
-/* The interrupt used for PCI INTA-INTD */
-int sc520_pci_ints[15] = {
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1
-};
-
-/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
-{
- int i;
-
-# if 1
- printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-#endif
- if (irq < 0 || irq > 15) {
- return -1; /* illegal irq */
- }
-
- if (pci_pin < 0 || pci_pin > 15) {
- return -1; /* illegal pci int pin */
- }
-
- /* first disable any non-pci interrupt source that use
- * this level */
- for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
- if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
- continue;
- }
- if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
- write_mmcr_byte(i, SC520_IRQ_DISABLED);
- }
- }
-
- /* Set the trigger to level */
- write_mmcr_byte(sc520_irq[irq].level_reg,
- read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
-
-
- if (pci_pin < 4) {
- /* PCI INTA-INTD */
- /* route the interrupt */
- write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-
-
- } else {
- /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
-
- /* also set the polarity in this case */
- write_mmcr_word(SC520_INTPINPOL,
- read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-
- }
-
- /* register the pin */
- sc520_pci_ints[pci_pin] = irq;
-
-
- return 0; /* OK */
-}
-
-void pci_sc520_init(struct pci_controller *hose)
-{
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(hose->regions + 0,
- SC520_PCI_MEMORY_BUS,
- SC520_PCI_MEMORY_PHYS,
- SC520_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- SC520_PCI_MEM_BUS,
- SC520_PCI_MEM_PHYS,
- SC520_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
- SC520_ISA_MEM_BUS,
- SC520_ISA_MEM_PHYS,
- SC520_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 3,
- SC520_PCI_IO_BUS,
- SC520_PCI_IO_PHYS,
- SC520_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
- SC520_ISA_IO_BUS,
- SC520_ISA_IO_PHYS,
- SC520_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 5;
-
- pci_setup_type1(hose,
- SC520_REG_ADDR,
- SC520_REG_DATA);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- /* enable target memory acceses on host brige */
- pci_write_config_word(0, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-}
-
-
-#endif
-
-#ifdef CONFIG_SYS_SC520_TIMER
-
-
-void reset_timer(void)
-{
- write_mmcr_word(SC520_GPTMR0CNT, 0);
- write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-
-}
-
-ulong get_timer(ulong base)
-{
- /* fixme: 30 or 33 */
- return read_mmcr_word(SC520_GPTMR0CNT) / 33;
-}
-
-void set_timer(ulong t)
-{
- /* FixMe: use two cascade coupled timers */
- write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
- write_mmcr_word(SC520_GPTMR0CNT, t*33);
- write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-}
-
-
-void udelay(unsigned long usec)
-{
- int m=0;
- long u;
-
- read_mmcr_word(SC520_SWTMRMILLI);
- read_mmcr_word(SC520_SWTMRMICRO);
-
-#if 0
- /* do not enable this line, udelay is used in the serial driver -> recursion */
- printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
-#endif
- while (1) {
-
- m += read_mmcr_word(SC520_SWTMRMILLI);
- u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
-
- if (usec <= u) {
- break;
- }
- }
-}
-
-#endif
-
-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
-{
- u8 temp=0;
-
- if (freq >= 8192) {
- temp |= CTL_CLK_SEL_4;
- } else if (freq >= 4096) {
- temp |= CTL_CLK_SEL_8;
- } else if (freq >= 2048) {
- temp |= CTL_CLK_SEL_16;
- } else if (freq >= 1024) {
- temp |= CTL_CLK_SEL_32;
- } else if (freq >= 512) {
- temp |= CTL_CLK_SEL_64;
- } else if (freq >= 256) {
- temp |= CTL_CLK_SEL_128;
- } else if (freq >= 128) {
- temp |= CTL_CLK_SEL_256;
- } else {
- temp |= CTL_CLK_SEL_512;
- }
-
- if (!lsb_first) {
- temp |= MSBF_ENB;
- }
-
- if (inv_clock) {
- temp |= CLK_INV_ENB;
- }
-
- if (inv_phase) {
- temp |= PHS_INV_ENB;
- }
-
- write_mmcr_byte(SC520_SSICTL, temp);
-
- return 0;
-}
-
-u8 ssi_txrx_byte(u8 data)
-{
- write_mmcr_byte(SC520_SSIXMIT, data);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- return read_mmcr_byte(SC520_SSIRCV);
-}
-
-
-void ssi_tx_byte(u8 data)
-{
- write_mmcr_byte(SC520_SSIXMIT, data);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
-}
-
-u8 ssi_rx_byte(void)
-{
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- return read_mmcr_byte(SC520_SSIRCV);
-}
-
#ifdef CONFIG_SYS_SC520_RESET
void reset_cpu(ulong addr)
{
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+static struct {
+ u8 priority;
+ u16 level_reg;
+ u8 level_bit;
+} sc520_irq[] = {
+ { SC520_IRQ0, SC520_MPICMODE, 0x01 },
+ { SC520_IRQ1, SC520_MPICMODE, 0x02 },
+ { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
+ { SC520_IRQ3, SC520_MPICMODE, 0x08 },
+ { SC520_IRQ4, SC520_MPICMODE, 0x10 },
+ { SC520_IRQ5, SC520_MPICMODE, 0x20 },
+ { SC520_IRQ6, SC520_MPICMODE, 0x40 },
+ { SC520_IRQ7, SC520_MPICMODE, 0x80 },
+
+ { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
+ { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
+ { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
+ { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
+ { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
+ { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
+ { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
+ { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
+};
+
+
+/* The interrupt used for PCI INTA-INTD */
+int sc520_pci_ints[15] = {
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1
+};
+
+/* utility function to configure a pci interrupt */
+int pci_sc520_set_irq(int pci_pin, int irq)
+{
+ int i;
+
+# if 1
+ printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
+#endif
+ if (irq < 0 || irq > 15) {
+ return -1; /* illegal irq */
+ }
+
+ if (pci_pin < 0 || pci_pin > 15) {
+ return -1; /* illegal pci int pin */
+ }
+
+ /* first disable any non-pci interrupt source that use
+ * this level */
+ for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
+ if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
+ continue;
+ }
+ if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
+ write_mmcr_byte(i, SC520_IRQ_DISABLED);
+ }
+ }
+
+ /* Set the trigger to level */
+ write_mmcr_byte(sc520_irq[irq].level_reg,
+ read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
+
+
+ if (pci_pin < 4) {
+ /* PCI INTA-INTD */
+ /* route the interrupt */
+ write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
+
+
+ } else {
+ /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
+ write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
+
+ /* also set the polarity in this case */
+ write_mmcr_word(SC520_INTPINPOL,
+ read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
+
+ }
+
+ /* register the pin */
+ sc520_pci_ints[pci_pin] = irq;
+
+
+ return 0; /* OK */
+}
+
+void pci_sc520_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space */
+ pci_set_region(hose->regions + 0,
+ SC520_PCI_MEMORY_BUS,
+ SC520_PCI_MEMORY_PHYS,
+ SC520_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ SC520_PCI_MEM_BUS,
+ SC520_PCI_MEM_PHYS,
+ SC520_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ SC520_ISA_MEM_BUS,
+ SC520_ISA_MEM_PHYS,
+ SC520_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ SC520_PCI_IO_BUS,
+ SC520_PCI_IO_PHYS,
+ SC520_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ SC520_ISA_IO_BUS,
+ SC520_ISA_IO_PHYS,
+ SC520_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_type1(hose,
+ SC520_REG_ADDR,
+ SC520_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* enable target memory acceses on host brige */
+ pci_write_config_word(0, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <asm/ic/ssi.h>
+#include <asm/ic/sc520.h>
+
+int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
+{
+ u8 temp=0;
+
+ if (freq >= 8192) {
+ temp |= CTL_CLK_SEL_4;
+ } else if (freq >= 4096) {
+ temp |= CTL_CLK_SEL_8;
+ } else if (freq >= 2048) {
+ temp |= CTL_CLK_SEL_16;
+ } else if (freq >= 1024) {
+ temp |= CTL_CLK_SEL_32;
+ } else if (freq >= 512) {
+ temp |= CTL_CLK_SEL_64;
+ } else if (freq >= 256) {
+ temp |= CTL_CLK_SEL_128;
+ } else if (freq >= 128) {
+ temp |= CTL_CLK_SEL_256;
+ } else {
+ temp |= CTL_CLK_SEL_512;
+ }
+
+ if (!lsb_first) {
+ temp |= MSBF_ENB;
+ }
+
+ if (inv_clock) {
+ temp |= CLK_INV_ENB;
+ }
+
+ if (inv_phase) {
+ temp |= PHS_INV_ENB;
+ }
+
+ write_mmcr_byte(SC520_SSICTL, temp);
+
+ return 0;
+}
+
+u8 ssi_txrx_byte(u8 data)
+{
+ write_mmcr_byte(SC520_SSIXMIT, data);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ return read_mmcr_byte(SC520_SSIRCV);
+}
+
+
+void ssi_tx_byte(u8 data)
+{
+ write_mmcr_byte(SC520_SSIXMIT, data);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
+}
+
+u8 ssi_rx_byte(void)
+{
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ return read_mmcr_byte(SC520_SSIRCV);
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <asm/interrupt.h>
+#include <asm/ic/sc520.h>
+
+void reset_timer(void)
+{
+ write_mmcr_word(SC520_GPTMR0CNT, 0);
+ write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
+
+}
+
+ulong get_timer(ulong base)
+{
+ /* fixme: 30 or 33 */
+ return read_mmcr_word(SC520_GPTMR0CNT) / 33;
+}
+
+void set_timer(ulong t)
+{
+ /* FixMe: use two cascade coupled timers */
+ write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
+ write_mmcr_word(SC520_GPTMR0CNT, t*33);
+ write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
+}
+
+
+void udelay(unsigned long usec)
+{
+ int m=0;
+ long u;
+
+ read_mmcr_word(SC520_SWTMRMILLI);
+ read_mmcr_word(SC520_SWTMRMICRO);
+
+#if 0
+ /* do not enable this line, udelay is used in the serial driver -> recursion */
+ printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
+#endif
+ while (1) {
+
+ m += read_mmcr_word(SC520_SWTMRMILLI);
+ u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
+
+ if (usec <= u) {
+ break;
+ }
+ }
+}
projects / platform / kernel / u-boot.git / commitdiff