case ISD::SUB:
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
- if (N->getOperand(1).getOpcode() == ISD::Constant)
- return;
Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
break;
case ISD::SHL:
;
; RV64I-LABEL: add_positive_low_bound_reject:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 2047
ret i32 %1
;
; RV64I-LABEL: add_positive_low_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1024
-; RV64I-NEXT: addi a0, a0, 1024
+; RV64I-NEXT: addiw a0, a0, 1024
+; RV64I-NEXT: addiw a0, a0, 1024
; RV64I-NEXT: ret
%1 = add i32 %a, 2048
ret i32 %1
;
; RV64I-LABEL: add_positive_high_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2047
-; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 4094
ret i32 %1
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, 4095
ret i32 %1
;
; RV64I-LABEL: add_negative_high_bound_reject:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -2048
ret i32 %1
;
; RV64I-LABEL: add_negative_high_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -1025
-; RV64I-NEXT: addi a0, a0, -1024
+; RV64I-NEXT: addiw a0, a0, -1025
+; RV64I-NEXT: addiw a0, a0, -1024
; RV64I-NEXT: ret
%1 = add i32 %a, -2049
ret i32 %1
;
; RV64I-LABEL: add_negative_low_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -2048
-; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -4096
ret i32 %1
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, -4097
ret i32 %1
;
; RV64I-LABEL: add32_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1500
-; RV64I-NEXT: addi a0, a0, 1499
+; RV64I-NEXT: addiw a0, a0, 1500
+; RV64I-NEXT: addiw a0, a0, 1499
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
ret i32 %1
;
; RV64I-LABEL: addi:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
-; RV64IFD-NEXT: addi a1, a1, -1
+; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func@plt
; RV64IM-LABEL: muli32_p384:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 384
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 384
ret i32 %1
; RV64IM-LABEL: muli32_p12288:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 3
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 12288
ret i32 %1
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 1048575
; RV64IM-NEXT: addiw a1, a1, -256
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, -4352
ret i32 %1
define i32 @aext_addiw_aext(i32 %a) nounwind {
; RV64I-LABEL: aext_addiw_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
define i32 @aext_addiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: aext_addiw_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2
+; RV64I-NEXT: addiw a0, a0, 2
; RV64I-NEXT: ret
%1 = add i32 %a, 2
ret i32 %1
define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: aext_addiw_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 3
+; RV64I-NEXT: addiw a0, a0, 3
; RV64I-NEXT: ret
%1 = add i32 %a, 3
ret i32 %1
;
; RV64I-LABEL: and_icmps_const_1bit_diff:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -44
+; RV64I-NEXT: addiw a0, a0, -44
; RV64I-NEXT: andi a0, a0, -17
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44
; RV64I-NEXT: bge a4, a2, .LBB1_2
; RV64I-NEXT: .LBB1_1: # %while_body
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: addi a4, a3, 1
+; RV64I-NEXT: addiw a4, a3, 1
; RV64I-NEXT: sw a4, 0(a1)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a0)
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8