ppc4xx: Make DDR2 timing for intip more robust
authorDirk Eibach <eibach@gdsys.de>
Mon, 21 Sep 2009 11:27:14 +0000 (13:27 +0200)
committerTom Rix <Tom.Rix@windriver.com>
Sat, 3 Oct 2009 14:04:32 +0000 (09:04 -0500)
DDR2 timing for intip was on the edge for some of the available chips
for this board. Now it is verfied to work with all of them.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
include/configs/intip.h

index 4f7bc7e..19f12fa 100644 (file)
 #define CONFIG_SYS_SDRAM_R3BAS         0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDULL     0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDUHB     0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL       0x80001C80
+#define CONFIG_SYS_SDRAM_CONF1LL       0x80001C00
 #define CONFIG_SYS_SDRAM_CONF1HB       0x80001C80
 #define CONFIG_SYS_SDRAM_CONFPATHB     0x10a68000
 
 #define CONFIG_SYS_SDRAM0_MB1CF                0x00000000
 #define CONFIG_SYS_SDRAM0_MB2CF                0x00000000
 #define CONFIG_SYS_SDRAM0_MB3CF                0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1       0x05122000
+#define CONFIG_SYS_SDRAM0_MCOPT1       0x05120000
 #define CONFIG_SYS_SDRAM0_MCOPT2       0x00000000
 #define CONFIG_SYS_SDRAM0_MODT0                0x00000000
 #define CONFIG_SYS_SDRAM0_MODT1                0x00000000
 #define CONFIG_SYS_SDRAM0_INITPLR1     0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR2     0x81020000
 #define CONFIG_SYS_SDRAM0_INITPLR3     0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4     0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR4     0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR5     0xE4000542
 #define CONFIG_SYS_SDRAM0_INITPLR6     0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR7     0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR9     0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR10    0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR11    0x81000442
-#define CONFIG_SYS_SDRAM0_INITPLR12    0x81010380
-#define CONFIG_SYS_SDRAM0_INITPLR13    0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR12    0x81010382
+#define CONFIG_SYS_SDRAM0_INITPLR13    0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR14    0x00000000
 #define CONFIG_SYS_SDRAM0_INITPLR15    0x00000000
 #define CONFIG_SYS_SDRAM0_RQDC         0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC         0x003F0000
-#define CONFIG_SYS_SDRAM0_RDCC         0x80000000
+#define CONFIG_SYS_SDRAM0_RFDC         0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC         0x40000000
 #define CONFIG_SYS_SDRAM0_DLCR         0x00000000
 #define CONFIG_SYS_SDRAM0_CLKTR                0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR                0x84000800
+#define CONFIG_SYS_SDRAM0_WRDTR                0x84000823
 #define CONFIG_SYS_SDRAM0_SDTR1                0x80201000
 #define CONFIG_SYS_SDRAM0_SDTR2                0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3                0x090B0D15
+#define CONFIG_SYS_SDRAM0_SDTR3                0x090C0D15
 #define CONFIG_SYS_SDRAM0_MMODE                0x00000442
-#define CONFIG_SYS_SDRAM0_MEMODE       0x00000000
+#define CONFIG_SYS_SDRAM0_MEMODE       0x00000002
 
 #define CONFIG_SYS_MBYTES_SDRAM        256     /* 256MB */