*
*
*/
-#define RX_VER2 "ver.2019/09/05"
+#define RX_VER2 "ver.2019/09/11"
/*print type*/
#define LOG_EN 0x01
int cdr_lock_level;
int clock_lock_th = 2;
int scdc_force_en;
+/* for hdcp_hpd debug, disable by default */
+bool hdcp_hpd_ctrl_en;
/*------------------------variable define end------------------------------*/
void rx_esm_tmdsclk_en(bool en)
{
hdmirx_wr_bits_top(TOP_CLK_CNTL, HDCP22_TMDSCLK_EN, en);
- if (hdcp22_on)
+ if (hdcp22_on && hdcp_hpd_ctrl_en)
hdmirx_hdcp22_hpd(en);
if (log_level & HDCP_LOG)
rx_pr("%s:%d\n", __func__, en);
hdmirx_wr_dwc(DWC_CHLOCK_CONFIG, data32);
/* hdcp2.2 ctl */
- if (hdcp22_on)
+ if (hdcp22_on) {
/* set hdcp_hpd high later */
- hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0);
- else
+ if (hdcp_hpd_ctrl_en)
+ hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0);
+ else
+ hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x1000);
+ } else {
hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 2);
+ }
}
extern int hbr_force_8ch;
extern int clock_lock_th;
extern int scdc_force_en;
+extern bool hdcp_hpd_ctrl_en;
extern void rx_get_best_eq_setting(void);
extern void wr_reg_hhi(unsigned int offset, unsigned int val);
extern void wr_reg_hhi_bits(unsigned int offset, unsigned int mask,
return pr_var(earc_cap_ds_update_hpd_en, index);
if (set_pr_var(tmpbuf, scdc_force_en, value, &index, ret))
return pr_var(scdc_force_en, index);
+ if (set_pr_var(tmpbuf, hdcp_hpd_ctrl_en, value, &index, ret))
+ return pr_var(hdcp_hpd_ctrl_en, index);
return 0;
}
pr_var(en_take_dtd_space, i++);
pr_var(earc_cap_ds_update_hpd_en, i++);
pr_var(scdc_force_en, i++);
+ pr_var(hdcp_hpd_ctrl_en, i++);
}
void skip_frame(unsigned int cnt)
pwr_sts = tmp_5v;
rx.cur_5v_sts = (pwr_sts >> rx.port) & 1;
hotplug_wait_query();
+ rx_pr("hotplug-0x%x\n", pwr_sts);
if (rx.cur_5v_sts == 0) {
set_fsm_state(FSM_5V_LOST);
rx.err_code = ERR_5V_LOST;