]
(const_string "<ssevecmode>")))])
-(define_insn "*andnottf3"
- [(set (match_operand:TF 0 "register_operand" "=x,x,v,v")
- (and:TF
- (not:TF (match_operand:TF 1 "register_operand" "0,x,v,v"))
- (match_operand:TF 2 "vector_operand" "xBm,xm,vm,v")))]
+;; Modes for andnot3 not covered by VI and MODEF.
+(define_mode_iterator ANDNOT_MODE [TF V1TI])
+
+(define_insn "*andnot<mode>3"
+ [(set (match_operand:ANDNOT_MODE 0 "register_operand" "=x,x,v,v")
+ (and:ANDNOT_MODE
+ (not:ANDNOT_MODE (match_operand:ANDNOT_MODE 1 "register_operand" "0,x,v,v"))
+ (match_operand:ANDNOT_MODE 2 "vector_operand" "xBm,xm,vm,v")))]
"TARGET_SSE"
{
char buf[128];
--- /dev/null
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-O2 -msse2" } */
+
+typedef __int128 v1ti __attribute__ ((__vector_size__ (16)));
+
+v1ti andnot1(v1ti x, v1ti y) { return ~x & y; }
+v1ti andnot2(v1ti x, v1ti y) { return x & ~y; }
+
+/* { dg-final { scan-assembler-times "pandn" 2 } } */
+/* { dg-final { scan-assembler-not "pcmpeqd" } } */
+/* { dg-final { scan-assembler-not "pxor" } } */