UNATIVE_OFFSET sz;
instrDesc* id;
insFormat fmt = emitInsModeFormat(ins, IF_RRD_CNS);
- bool valInByte = ((signed char)val == val) && (ins != INS_mov) && (ins != INS_test);
+ bool valInByte = ((signed char)val == (target_ssize_t)val) && (ins != INS_mov) && (ins != INS_test);
// BT reg,imm might be useful but it requires special handling of the immediate value
// (it is always encoded in a byte). Let's not complicate things until this is needed.
{
UNATIVE_OFFSET sz;
instrDesc* id;
- bool valInByte = ((signed char)val == val);
+ bool valInByte = ((signed char)val == (target_ssize_t)val);
#ifdef TARGET_AMD64
// mov reg, imm64 is the only opcode which takes a full 8 byte immediate
instruction ins = id->idIns();
regNumber reg = id->idReg1();
ssize_t val = emitGetInsSC(id);
- bool valInByte = ((signed char)val == val) && (ins != INS_mov) && (ins != INS_test);
+ bool valInByte = ((signed char)val == (target_ssize_t)val) && (ins != INS_mov) && (ins != INS_test);
// BT reg,imm might be useful but it requires special handling of the immediate value
// (it is always encoded in a byte). Let's not complicate things until this is needed.
instruction ins = id->idIns();
emitAttr size = id->idOpSize();
ssize_t val = emitGetInsSC(id);
- bool valInByte = ((signed char)val == val);
+ bool valInByte = ((signed char)val == (target_ssize_t)val);
// We would to update GC info correctly
assert(!IsSSEInstruction(ins));