#include <soc/tegra/bpmp.h>
#include "mc.h"
+/*
+ * MC Client entries are sorted in the increasing order of the
+ * override and security register offsets.
+ */
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
.id = TEGRA234_MEMORY_CLIENT_HDAR,
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
+ .name = "pcie6ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x140,
+ .security = 0x144,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
+ .name = "pcie6aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x148,
+ .security = 0x14c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
+ .name = "pcie7ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x150,
+ .security = 0x154,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x160,
+ .security = 0x164,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x168,
+ .security = 0x16c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA0,
+ .regs = {
+ .sid = {
+ .override = 0x170,
+ .security = 0x174,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
+ .name = "dla0rdb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x178,
+ .security = 0x17c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
+ .name = "pcie7aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x180,
+ .security = 0x184,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
+ .name = "pcie8ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x190,
+ .security = 0x194,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_HDAW,
.name = "hdaw",
.bpmp_id = TEGRA_ICC_BPMP_HDA,
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
+ .name = "pcie8aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE8,
+ .regs = {
+ .sid = {
+ .override = 0x1d8,
+ .security = 0x1dc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
+ .name = "pcie9ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1e0,
+ .security = 0x1e4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
+ .name = "pcie6ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE6,
+ .regs = {
+ .sid = {
+ .override = 0x1e8,
+ .security = 0x1ec,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
+ .name = "pcie9aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE9,
+ .regs = {
+ .sid = {
+ .override = 0x1f0,
+ .security = 0x1f4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
+ .name = "pcie10ar",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x1f8,
+ .security = 0x1fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
+ .name = "pcie10aw",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x200,
+ .security = 0x204,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
+ .name = "pcie10ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE10,
+ .regs = {
+ .sid = {
+ .override = 0x240,
+ .security = 0x244,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
+ .name = "pcie7ar1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_PCIE7,
+ .regs = {
+ .sid = {
+ .override = 0x248,
+ .security = 0x24c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
.name = "mgbeard",
.bpmp_id = TEGRA_ICC_BPMP_EQOS,
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
+ .name = "dla0rdb1",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x370,
+ .security = 0x374,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
+ .name = "dla0wrb",
+ .sid = TEGRA234_SID_NVDLA1,
+ .regs = {
+ .sid = {
+ .override = 0x378,
+ .security = 0x37c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_VI2W,
.name = "vi2w",
.bpmp_id = TEGRA_ICC_BPMP_VI2,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
- .name = "vi2falw",
- .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
- .type = TEGRA_ICC_ISO_VIFAL,
- .sid = TEGRA234_SID_ISO_VI2FALC,
- .regs = {
- .sid = {
- .override = 0x3e0,
- .security = 0x3e4,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_APER,
.name = "aper",
.bpmp_id = TEGRA_ICC_BPMP_APE,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
- .name = "nvdisplayr",
- .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
- .type = TEGRA_ICC_ISO_DISPLAY,
- .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .id = TEGRA234_MEMORY_CLIENT_VI2FALW,
+ .name = "vi2falw",
+ .bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
+ .type = TEGRA_ICC_ISO_VIFAL,
+ .sid = TEGRA234_SID_ISO_VI2FALC,
.regs = {
.sid = {
- .override = 0x490,
- .security = 0x494,
+ .override = 0x3e0,
+ .security = 0x3e4,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
- .name = "nvdisplayr1",
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
+ .name = "nvdisplayr",
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
.type = TEGRA_ICC_ISO_DISPLAY,
.sid = TEGRA234_SID_ISO_NVDISPLAY,
.regs = {
.sid = {
- .override = 0x508,
- .security = 0x50c,
+ .override = 0x490,
+ .security = 0x494,
},
},
}, {
},
},
}, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
+ .name = "nvdisplayr1",
+ .bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
+ .type = TEGRA_ICC_ISO_DISPLAY,
+ .sid = TEGRA234_SID_ISO_NVDISPLAY,
+ .regs = {
+ .sid = {
+ .override = 0x508,
+ .security = 0x50c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA0,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x160,
- .security = 0x164,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x748,
- .security = 0x74c,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA0,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x168,
- .security = 0x16c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA0,
- .regs = {
- .sid = {
- .override = 0x170,
- .security = 0x174,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
.name = "dla0rda",
.sid = TEGRA234_SID_NVDLA1,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
- .name = "dla0rdb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x178,
- .security = 0x17c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
- .name = "dla0rda1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x750,
- .security = 0x754,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
.name = "dla0falwrb",
.sid = TEGRA234_SID_NVDLA1,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
- .name = "dla0rdb1",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x370,
- .security = 0x374,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
- .name = "dla0wrb",
- .sid = TEGRA234_SID_NVDLA1,
- .regs = {
- .sid = {
- .override = 0x378,
- .security = 0x37c,
- },
- },
- }, {
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
.name = "pcie0r",
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
- .name = "pcie5r1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE5,
- .regs = {
- .sid = {
- .override = 0x778,
- .security = 0x77c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
- .name = "pcie6ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x140,
- .security = 0x144,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
- .name = "pcie6aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x148,
- .security = 0x14c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
- .name = "pcie6ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE6,
- .regs = {
- .sid = {
- .override = 0x1e8,
- .security = 0x1ec,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
- .name = "pcie7ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x150,
- .security = 0x154,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
- .name = "pcie7aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x180,
- .security = 0x184,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
- .name = "pcie7ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE7,
- .regs = {
- .sid = {
- .override = 0x248,
- .security = 0x24c,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
- .name = "pcie8ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x190,
- .security = 0x194,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
- .name = "pcie8aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE8,
- .regs = {
- .sid = {
- .override = 0x1d8,
- .security = 0x1dc,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
- .name = "pcie9ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
- .regs = {
- .sid = {
- .override = 0x1e0,
- .security = 0x1e4,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
- .name = "pcie9aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE9,
- .regs = {
- .sid = {
- .override = 0x1f0,
- .security = 0x1f4,
- },
- },
- }, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
- .name = "pcie10ar",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA0,
.regs = {
.sid = {
- .override = 0x1f8,
- .security = 0x1fc,
+ .override = 0x748,
+ .security = 0x74c,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
- .name = "pcie10aw",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
- .type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
+ .name = "dla0rda1",
+ .sid = TEGRA234_SID_NVDLA1,
.regs = {
.sid = {
- .override = 0x200,
- .security = 0x204,
+ .override = 0x750,
+ .security = 0x754,
},
},
}, {
- .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
- .name = "pcie10ar1",
- .bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
+ .id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
+ .name = "pcie5r1",
+ .bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
.type = TEGRA_ICC_NISO,
- .sid = TEGRA234_SID_PCIE10,
+ .sid = TEGRA234_SID_PCIE5,
.regs = {
.sid = {
- .override = 0x240,
- .security = 0x244,
+ .override = 0x778,
+ .security = 0x77c,
},
},
}, {