driver:GPU:set the gpu frequency to 594Mhz

set the gpu frequency to 594Mhz

Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>

diff --git a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c
index ed9b0b9..af93caa 100644 (file)
--- a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c
+++ b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c
@@ -264,6 +264,12 @@ static int create_sf7110_cfg(struct device *dev)
                goto err_gpu_unmap;
        }
 
+       psf->clk_div = devm_clk_get_optional(dev, "clk_bv");
+       if (IS_ERR(psf->clk_div)) {
+               dev_err(dev, "failed to get gpu clk_div\n");
+               goto err_gpu_unmap;
+       }
+
        psf->rst_apb = devm_reset_control_get_exclusive(dev, "rst_apb");
        if (IS_ERR(psf->rst_apb)) {
                dev_err(dev, "failed to get GPU rst_apb\n");
@@ -289,6 +295,7 @@ void u0_img_gpu_enable(void)
 
        clk_prepare_enable(sf_cfg_t.clk_apb);
        clk_prepare_enable(sf_cfg_t.clk_rtc);
+       clk_set_rate(sf_cfg_t.clk_div, RGX_STARFIVE_7100_CORE_CLOCK_SPEED);
        clk_prepare_enable(sf_cfg_t.clk_core);
        clk_prepare_enable(sf_cfg_t.clk_sys);
 }

diff --git a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h
index 0673a46..f44edb3 100644 (file)
--- a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h
+++ b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.h
@@ -62,6 +62,7 @@ struct sf7110_cfg {
        struct clk *clk_core;
        struct clk *clk_sys;
        struct clk *clk_axi;
+       struct clk *clk_div;
        struct reset_control *rst_apb;
        struct reset_control *rst_doma;
 
@@ -79,7 +80,7 @@ struct sf7110_cfg {
 #define RGX_STARFIVE_7100_CORE_CLOCK_SPEED (8 * 1000 * 1000)//actually the CLK is 8M on FPGA platform 
 #define SYS_RGX_ACTIVE_POWER_LATENCY_MS (80000)
 #else
-#define RGX_STARFIVE_7100_CORE_CLOCK_SPEED (409.6 * 1000 * 1000)//maybe 400M?
+#define RGX_STARFIVE_7100_CORE_CLOCK_SPEED (594.0 * 1000 * 1000)//maybe 400M?
 #define SYS_RGX_ACTIVE_POWER_LATENCY_MS (100)
 #endif