if (map->staging)
iris_flush_staging_region(xfer, box);
- uint32_t history_flush = 0;
-
if (res->base.b.target == PIPE_BUFFER) {
- if (map->staging)
- history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_TILE_CACHE_FLUSH;
-
- if (map->dest_had_defined_contents)
- history_flush |= iris_flush_bits_for_history(ice, res);
-
util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
}
- if (history_flush & ~PIPE_CONTROL_CS_STALL) {
- iris_foreach_batch(ice, batch) {
- if (batch->contains_draw || batch->cache.render->entries) {
- iris_batch_maybe_flush(batch, 24);
- iris_emit_pipe_control_flush(batch,
- "cache history: transfer flush",
- history_flush);
- }
- }
- }
-
/* Make sure we flag constants dirty even if there's no need to emit
* any PIPE_CONTROLs to a batch.
*/
ice->state.stage_dirty |= stage_dirty;
}
-/**
- * Produce a set of PIPE_CONTROL bits which ensure data written to a
- * resource becomes visible, and any stale read cache data is invalidated.
- */
-uint32_t
-iris_flush_bits_for_history(struct iris_context *ice,
- struct iris_resource *res)
-{
- struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
-
- uint32_t flush = PIPE_CONTROL_CS_STALL;
-
- if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
- flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
- flush |= screen->compiler->indirect_ubos_use_sampler ?
- PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
- PIPE_CONTROL_DATA_CACHE_FLUSH;
- }
-
- if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
- flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-
- if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
- flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
-
- if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
- flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
-
- return flush;
-}
-
bool
iris_resource_set_clear_color(struct iris_context *ice,
struct iris_resource *res,
if (active) {
ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
} else {
- uint32_t flush = 0;
for (int i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
struct iris_stream_output_target *tgt =
(void *) ice->state.so_target[i];
- if (tgt) {
- struct iris_resource *res = (void *) tgt->base.buffer;
- flush |= iris_flush_bits_for_history(ice, res);
- iris_dirty_for_history(ice, res);
- }
+ if (tgt)
+ iris_dirty_for_history(ice, (void *)tgt->base.buffer);
}
-#if GFX_VER >= 12
- /* SO draws require flushing of const cache to make SO data
- * observable when VB/IB are cached in L3.
- */
- if (flush & PIPE_CONTROL_VF_CACHE_INVALIDATE)
- flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
-#endif
- iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
- "make streamout results visible", flush);
}
}