}
break;
}
+ case ARMISD::VBICIMM: {
+ SDValue Op0 = Op.getOperand(0);
+ unsigned ModImm = Op.getConstantOperandVal(1);
+ unsigned EltBits = 0;
+ uint64_t Mask = ARM_AM::decodeVMOVModImm(ModImm, EltBits);
+ if ((OriginalDemandedBits & Mask) == 0)
+ return TLO.CombineTo(Op, Op0);
+ }
}
return TargetLowering::SimplifyDemandedBitsForTargetNode(
; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vmullt.u8 q2, q1, q0
; CHECK-NEXT: vmullb.u8 q0, q1, q0
-; CHECK-NEXT: vqshrnb.u16 q2, q2, #7
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
-; CHECK-NEXT: vmovlb.u8 q2, q2
-; CHECK-NEXT: vmovlb.u8 q0, q0
-; CHECK-NEXT: vmovnt.i16 q0, q2
+; CHECK-NEXT: vqshrnt.u16 q0, q2, #7
; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB21_4
; CHECK-NEXT: @ %bb.5: @ %middle.block
define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_t1(<8 x i16> %s0, <16 x i8> %src1) {
; CHECK-LABEL: vqmovni16_uminmax_t1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vqmovnb.u16 q0, q0
-; CHECK-NEXT: vmovlb.u8 q0, q0
-; CHECK-NEXT: vmovnt.i16 q1, q0
+; CHECK-NEXT: vqmovnt.u16 q1, q0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry:
; CHECK-LABEL: vqmovni16_uminmax_t2:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vqmovnb.u16 q0, q0
-; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vmovnt.i16 q0, q1
; CHECK-NEXT: bx lr
entry:
define arm_aapcs_vfpcc <16 x i8> @vqmovni16_uminmax_b1(<8 x i16> %s0, <16 x i8> %src1) {
; CHECK-LABEL: vqmovni16_uminmax_b1:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vqmovnb.u16 q0, q0
-; CHECK-NEXT: vmovlb.u8 q0, q0
-; CHECK-NEXT: vmovnb.i16 q1, q0
+; CHECK-NEXT: vqmovnb.u16 q1, q0
; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr
entry: