* Clean `valuenum.cpp`.
* Clean `emitarm64.cpp`.
* Clean `lsraarm64.cpp`.
* Clean `lsraarmarch.cpp`.
* Clean `lowerarmarch.cpp`.
* Clean `lower.cpp`.
* Clean `ssabuilder.cpp`.
* Clean `simd.cpp`.
* Clear `simdcodegenxarch.cpp`.
* Clean `lowerxarch.cpp`.
* Clean `scopeinfo.cpp`.
* Clean `hwintrinsiccodegenxarch.cpp`.
unsigned R = bmImm.immR;
unsigned S = bmImm.immS;
- unsigned elemWidth = 64; // used when immN == 1
+ unsigned elemWidth = 64; // used when N == 1
- if (bmImm.immN == 0) // find the smaller elemWidth when immN == 0
+ if (N == 0) // find the smaller elemWidth when N == 0
{
// Scan S for the highest bit not set
elemWidth = 32;
void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
- instrDesc* id = nullptr;
+ insFormat fmt = IF_NONE;
+ instrDesc* id = nullptr;
/* Figure out the encoding format of the instruction */
switch (ins)
ssize_t imm8 = 0;
unsigned pos = 0;
canEncode = true;
- bool failed = false;
while (uimm != 0)
{
INT64 loByte = uimm & 0xFF;
void emitter::emitIns_R_COND(instruction ins, emitAttr attr, regNumber reg, insCond cond)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
+ insFormat fmt = IF_NONE;
condFlagsImm cfi;
cfi.immCFVal = 0;
void emitter::emitIns_R_R_COND(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCond cond)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
+ insFormat fmt = IF_NONE;
condFlagsImm cfi;
cfi.immCFVal = 0;
void emitter::emitIns_R_R_R_COND(
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, insCond cond)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
+ insFormat fmt = IF_NONE;
condFlagsImm cfi;
cfi.immCFVal = 0;
void emitter::emitIns_R_R_FLAGS_COND(
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, insCflags flags, insCond cond)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
+ insFormat fmt = IF_NONE;
condFlagsImm cfi;
cfi.immCFVal = 0;
void emitter::emitIns_R_I_FLAGS_COND(
instruction ins, emitAttr attr, regNumber reg, int imm, insCflags flags, insCond cond)
{
- emitAttr size = EA_SIZE(attr);
- insFormat fmt = IF_NONE;
+ insFormat fmt = IF_NONE;
condFlagsImm cfi;
cfi.immCFVal = 0;
emitAttr size = EA_SIZE(attr);
insFormat fmt = IF_NONE;
- int disp = 0;
instrDescJmp* id = emitNewInstrJmp();
switch (ins)
size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
{
- BYTE* dst = *dp;
- BYTE* odst = dst;
- code_t code = 0;
- size_t sz = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
- instruction ins = id->idIns();
- insFormat fmt = id->idInsFmt();
- emitAttr size = id->idOpSize();
- unsigned char callInstrSize = 0;
+ BYTE* dst = *dp;
+ BYTE* odst = dst;
+ code_t code = 0;
+ size_t sz = emitGetInstrDescSize(id); // TODO-ARM64-Cleanup: on ARM, this is set in each case. why?
+ instruction ins = id->idIns();
+ insFormat fmt = id->idInsFmt();
+ emitAttr size = id->idOpSize();
#ifdef DEBUG
#if DUMP_GC_TABLES
assert(REG_NA == (int)REG_NA);
- VARSET_TP GCvars(VarSetOps::UninitVal());
-
/* What instruction format have we got? */
switch (fmt)
regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src)
{
- regNumber result = REG_NA;
-
// dst can only be a reg
assert(!dst->isContained());
regNumber emitter::emitInsTernary(instruction ins, emitAttr attr, GenTree* dst, GenTree* src1, GenTree* src2)
{
- regNumber result = REG_NA;
-
// dst can only be a reg
assert(!dst->isContained());
if (genIsTableDrivenHWIntrinsic(intrinsicId, category))
{
- GenTree* op1 = node->gtGetOp1();
- GenTree* op2 = node->gtGetOp2();
- regNumber targetReg = node->gtRegNum;
- var_types targetType = node->TypeGet();
- var_types baseType = node->gtSIMDBaseType;
+ GenTree* op1 = node->gtGetOp1();
+ GenTree* op2 = node->gtGetOp2();
+ regNumber targetReg = node->gtRegNum;
+ var_types baseType = node->gtSIMDBaseType;
regNumber op1Reg = REG_NA;
regNumber op2Reg = REG_NA;
//
void CodeGen::genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr)
{
- var_types targetType = node->TypeGet();
- regNumber targetReg = node->gtRegNum;
- GenTree* op1 = node->gtGetOp1();
- GenTree* op2 = node->gtGetOp2();
- emitter* emit = getEmitter();
+ regNumber targetReg = node->gtRegNum;
+ GenTree* op1 = node->gtGetOp1();
+ GenTree* op2 = node->gtGetOp2();
+ emitter* emit = getEmitter();
if (op2 != nullptr)
{
//
void CodeGen::genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
{
- var_types targetType = node->TypeGet();
- regNumber targetReg = node->gtRegNum;
- GenTree* op1 = node->gtGetOp1();
- emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
- emitter* emit = getEmitter();
+ regNumber targetReg = node->gtRegNum;
+ GenTree* op1 = node->gtGetOp1();
+ emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
+ emitter* emit = getEmitter();
// TODO-XArch-CQ: Commutative operations can have op1 be contained
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
//
void CodeGen::genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, int8_t ival)
{
- var_types targetType = node->TypeGet();
- regNumber targetReg = node->gtRegNum;
- GenTree* op1 = node->gtGetOp1();
- GenTree* op2 = node->gtGetOp2();
- emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
- emitter* emit = getEmitter();
+ regNumber targetReg = node->gtRegNum;
+ GenTree* op1 = node->gtGetOp1();
+ GenTree* op2 = node->gtGetOp2();
+ emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
+ emitter* emit = getEmitter();
// TODO-XArch-CQ: Commutative operations can have op1 be contained
// TODO-XArch-CQ: Non-VEX encoded instructions can have both ops contained
//
void CodeGen::genHWIntrinsic_R_R_RM_R(GenTreeHWIntrinsic* node, instruction ins)
{
- var_types targetType = node->TypeGet();
- regNumber targetReg = node->gtRegNum;
- GenTree* op1 = node->gtGetOp1();
- GenTree* op2 = node->gtGetOp2();
- GenTree* op3 = nullptr;
- emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
- emitter* emit = getEmitter();
+ regNumber targetReg = node->gtRegNum;
+ GenTree* op1 = node->gtGetOp1();
+ GenTree* op2 = node->gtGetOp2();
+ GenTree* op3 = nullptr;
+ emitAttr simdSize = EA_ATTR(node->gtSIMDSize);
+ emitter* emit = getEmitter();
assert(op1->OperIsList());
assert(op2 == nullptr);
BasicBlock* jmpTable[256];
unsigned jmpTableBase = emit->emitBBTableDataGenBeg(maxByte, true);
- unsigned jmpTableOffs = 0;
// Emit the jump table
for (unsigned i = 0; i < maxByte; i++)
NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
GenTree* op1 = node->gtGetOp1();
GenTree* op2 = node->gtGetOp2();
- GenTree* op3 = nullptr;
- GenTree* op4 = nullptr;
regNumber targetReg = node->gtRegNum;
- var_types targetType = node->TypeGet();
var_types baseType = node->gtSIMDBaseType;
regNumber op1Reg = REG_NA;
- regNumber op2Reg = REG_NA;
- regNumber op3Reg = REG_NA;
- regNumber op4Reg = REG_NA;
emitter* emit = getEmitter();
genConsumeHWIntrinsicOperands(node);
NamedIntrinsic intrinsicId = node->gtHWIntrinsicId;
GenTree* op1 = node->gtGetOp1();
GenTree* op2 = node->gtGetOp2();
- GenTree* op3 = nullptr;
- GenTree* op4 = nullptr;
regNumber targetReg = node->gtRegNum;
- var_types targetType = node->TypeGet();
var_types baseType = node->gtSIMDBaseType;
regNumber op1Reg = REG_NA;
- regNumber op2Reg = REG_NA;
- regNumber op3Reg = REG_NA;
- regNumber op4Reg = REG_NA;
emitter* emit = getEmitter();
genConsumeHWIntrinsicOperands(node);
noway_assert(jumpCnt >= 2);
// Spill the argument to the switch node into a local so that it can be used later.
- unsigned blockWeight = originalSwitchBB->getBBWeight(comp);
-
LIR::Use use(switchBBRange, &(node->gtOp.gtOp1), node);
ReplaceWithLclVar(use);
assert(node->gtOper == GT_SWITCH);
GenTree* temp = node->gtOp.gtOp1;
assert(temp->gtOper == GT_LCL_VAR);
- unsigned tempLclNum = temp->gtLclVarCommon.gtLclNum;
- LclVarDsc* tempVarDsc = comp->lvaTable + tempLclNum;
- var_types tempLclType = temp->TypeGet();
+ unsigned tempLclNum = temp->gtLclVarCommon.gtLclNum;
+ var_types tempLclType = temp->TypeGet();
BasicBlock* defaultBB = jumpTab[jumpCnt - 1];
BasicBlock* followingBB = originalSwitchBB->bbNext;
// This should not be a GT_PHI_ARG.
assert(treeNode->OperGet() != GT_PHI_ARG);
- GenTreeLclVarCommon* lcl = treeNode->AsLclVarCommon();
- LclVarDsc* lclVar = &comp->lvaTable[lcl->gtLclNum];
+ GenTreeLclVarCommon* lcl = treeNode->AsLclVarCommon();
// Fast tail calling criteria permits passing of structs of size 1, 2, 4 and 8 as args.
// It is possible that the callerArgLclNum corresponds to such a struct whose stack slot
#if defined(_TARGET_XARCH_) || defined(_TARGET_ARM64_)
GenTree* op1 = cmp->gtGetOp1();
- var_types op1Type = op1->TypeGet();
GenTreeIntCon* op2 = cmp->gtGetOp2()->AsIntCon();
ssize_t op2Value = op2->IconValue();
#ifdef _TARGET_XARCH_
+ var_types op1Type = op1->TypeGet();
if (IsContainableMemoryOp(op1) && varTypeIsSmall(op1Type) && genSmallTypeCanRepresentValue(op1Type, op2Value))
{
//
// platform. They may be changed in the future such that they preserve all register values.
GenTree* result = nullptr;
- void* addr = nullptr;
// assert we have seen one of these
noway_assert(comp->info.compCallUnmanaged != 0);
{
assert(addr != nullptr);
- unsigned markCount = 0;
-
SideEffectSet baseSideEffects;
if (base != nullptr)
{
return addr;
}
- GenTree* arrLength = nullptr;
-
JITDUMP("Addressing mode:\n");
JITDUMP(" Base\n ");
DISPNODE(base);
//
GenTree* Lowering::LowerAdd(GenTree* node)
{
- GenTree* next = node->gtNext;
-
#ifndef _TARGET_ARMARCH_
if (varTypeIsIntegralOrI(node))
{
assert(divMod->OperGet() != GT_UMOD);
#endif // _TARGET_ARM64_
- GenTree* next = divMod->gtNext;
GenTree* dividend = divMod->gtGetOp1();
GenTree* divisor = divMod->gtGetOp2();
// We need to use the dividend node multiple times so its value needs to be
// computed once and stored in a temp variable.
-
- unsigned curBBWeight = comp->compCurBB->getBBWeight(comp);
-
LIR::Use opDividend(BlockRange(), &divMod->gtOp.gtOp1, divMod);
dividend = ReplaceWithLclVar(opDividend);
GenTree* Lowering::LowerSignedDivOrMod(GenTree* node)
{
assert((node->OperGet() == GT_DIV) || (node->OperGet() == GT_MOD));
- GenTree* next = node->gtNext;
- GenTree* divMod = node;
- GenTree* dividend = divMod->gtGetOp1();
- GenTree* divisor = divMod->gtGetOp2();
+ GenTree* next = node->gtNext;
if (varTypeIsIntegral(node->TypeGet()))
{
GenTree* Lowering::LowerArrElem(GenTree* node)
{
// This will assert if we don't have an ArrElem node
- GenTreeArrElem* arrElem = node->AsArrElem();
- const unsigned char rank = arrElem->gtArrElem.gtArrRank;
- const unsigned blockWeight = m_block->getBBWeight(comp);
+ GenTreeArrElem* arrElem = node->AsArrElem();
+ const unsigned char rank = arrElem->gtArrElem.gtArrRank;
JITDUMP("Lowering ArrElem\n");
JITDUMP("============\n");
GenTree* arrObjNode = arrElem->gtArrObj;
assert(arrObjNode->IsLocal());
- LclVarDsc* const varDsc = &comp->lvaTable[arrElem->gtArrObj->AsLclVarCommon()->gtLclNum];
-
GenTree* insertionPoint = arrElem;
// The first ArrOffs node will have 0 for the offset of the previous dimension.
bool makeContained = true;
if ((addr->OperGet() == GT_LEA) && IsSafeToContainMem(indirNode, addr))
{
- GenTreeAddrMode* lea = addr->AsAddrMode();
- GenTree* base = lea->Base();
- GenTree* index = lea->Index();
- int cns = lea->Offset();
-
#ifdef _TARGET_ARM_
// ARM floating-point load/store doesn't support a form similar to integer
// ldr Rdst, [Rbase + Roffset] with offset in a register. The only supported
// form is vldr Rdst, [Rbase + imm] with a more limited constraint on the imm.
+ GenTreeAddrMode* lea = addr->AsAddrMode();
+ int cns = lea->Offset();
if (lea->HasIndex() || !emitter::emitIns_valid_imm_for_vldst_offset(cns))
{
if (indirNode->OperGet() == GT_STOREIND)
//
void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
{
- NamedIntrinsic intrinsicID = node->gtHWIntrinsicId;
- GenTreeArgList* argList = nullptr;
- GenTree* op1 = node->gtOp.gtOp1;
- GenTree* op2 = node->gtOp.gtOp2;
+ GenTreeArgList* argList = nullptr;
+ GenTree* op1 = node->gtOp.gtOp1;
+ GenTree* op2 = node->gtOp.gtOp2;
if (op1->OperIs(GT_LIST))
{
//
void Lowering::LowerBlockStore(GenTreeBlk* blkNode)
{
- GenTree* dstAddr = blkNode->Addr();
- unsigned size = blkNode->gtBlkSize;
- GenTree* source = blkNode->Data();
- Compiler* compiler = comp;
- GenTree* srcAddrOrFill = nullptr;
- bool isInitBlk = blkNode->OperIsInitBlkOp();
+ GenTree* dstAddr = blkNode->Addr();
+ unsigned size = blkNode->gtBlkSize;
+ GenTree* source = blkNode->Data();
+ GenTree* srcAddrOrFill = nullptr;
+ bool isInitBlk = blkNode->OperIsInitBlkOp();
if (!isInitBlk)
{
}
#ifdef FEATURE_PUT_STRUCT_ARG_STK
- GenTree* dst = putArgStk;
GenTree* srcAddr = nullptr;
bool haveLocalAddr = false;
// it might be the right thing to do.
// This threshold will decide from using the helper or let the JIT decide to inline
- // a code sequence of its choice.
+ // a code sequence of its choice, but currently we use CPBLK_UNROLL_LIMIT, see #20549.
ssize_t helperThreshold = max(CPBLK_MOVS_LIMIT, CPBLK_UNROLL_LIMIT);
ssize_t size = putArgStk->gtNumSlots * TARGET_POINTER_SIZE;
return;
}
- GenTree* dividend = node->gtGetOp1();
- GenTree* divisor = node->gtGetOp2();
+ GenTree* divisor = node->gtGetOp2();
bool divisorCanBeRegOptional = true;
#ifdef _TARGET_X86_
+ GenTree* dividend = node->gtGetOp1();
if (dividend->OperGet() == GT_LONG)
{
divisorCanBeRegOptional = false;
int LinearScan::BuildNode(GenTree* tree)
{
assert(!tree->isContained());
- Interval* prefSrcInterval = nullptr;
int srcCount;
int dstCount = 0;
regMaskTP dstCandidates = RBM_NONE;
// Reset the build-related members of LinearScan.
clearBuildState();
- RegisterType registerType = TypeGet(tree);
-
// Set the default dstCount. This may be modified below.
if (tree->IsValue())
{
GenTreeBoundsChk* node = tree->AsBoundsChk();
// Consumes arrLen & index - has no result
assert(dstCount == 0);
-
- GenTree* intCns = nullptr;
- GenTree* other = nullptr;
- srcCount = BuildOperandUses(tree->AsBoundsChk()->gtIndex);
- srcCount += BuildOperandUses(tree->AsBoundsChk()->gtArrLen);
+ srcCount = BuildOperandUses(node->gtIndex);
+ srcCount += BuildOperandUses(node->gtArrLen);
}
break;
op1 = op1->AsArgList()->Current();
}
- int dstCount = intrinsicTree->IsValue() ? 1 : 0;
bool op2IsDelayFree = false;
bool op3IsDelayFree = false;
return srcCount;
}
- bool isStore = (indirTree->gtOper == GT_STOREIND);
-
GenTree* addr = indirTree->Addr();
GenTree* index = nullptr;
int cns = 0;
regNumber otherRegNum = REG_NA;
for (unsigned nCnt = 0; nCnt < structDesc.eightByteCount; nCnt++)
{
- unsigned len = structDesc.eightByteSizes[nCnt];
var_types regType = TYP_UNDEF;
if (nCnt == 0)
unsigned initCount = argCount - 1;
unsigned elementCount = getSIMDVectorLength(size, baseType);
noway_assert(initCount == elementCount);
- GenTree* nextArg = op2;
// Build a GT_LIST with the N values.
// We must maintain left-to-right order of the args, but we will pop
GenTree* list = nullptr;
GenTree* firstArg = nullptr;
GenTree* prevArg = nullptr;
- int offset = 0;
bool areArgsContiguous = true;
for (unsigned i = 0; i < initCount; i++)
{
assert(op2->TypeGet() == TYP_REF);
GenTree* arrayRefForArgChk = op2;
GenTree* argRngChk = nullptr;
- GenTree* asg = nullptr;
if ((arrayRefForArgChk->gtFlags & GTF_SIDE_EFFECT) != 0)
{
op2 = fgInsertCommaFormTemp(&arrayRefForArgChk);
// op2 - VSmall
// op1 - byref of VLarge
assert(baseType == TYP_FLOAT);
- unsigned elementByteCount = 4;
GenTree* op4 = nullptr;
if (argCount == 4)
assert(op1->IsLocal() && op1->TypeGet() == TYP_SIMD32);
regNumber srcReg = simdNode->gtRegNum;
regNumber lclVarReg = genConsumeReg(op1);
- unsigned varNum = op1->AsLclVarCommon()->gtLclNum;
assert(lclVarReg != REG_NA);
assert(srcReg != REG_NA);
if (simdNode->gtFlags & GTF_SPILLED)
for (NodeToTestDataMap::KeyIterator ki = testData->Begin(); !ki.Equal(testData->End()); ++ki)
{
TestLabelAndNum tlAndN;
- GenTree* node = ki.Get();
- bool b = testData->Lookup(node, &tlAndN);
- assert(b);
+ GenTree* node = ki.Get();
+ bool nodeExists = testData->Lookup(node, &tlAndN);
+ assert(nodeExists);
if (tlAndN.m_tl == TL_SsaName)
{
if (node->OperGet() != GT_LCL_VAR)
}
// The mapping(s) must be one-to-one: if the label has a mapping, then the ssaNm must, as well.
ssize_t num2;
- bool b = ssaToLabel->Lookup(ssaNm, &num2);
+ bool ssaExists = ssaToLabel->Lookup(ssaNm, &num2);
+ assert(ssaExists);
// And the mappings must be the same.
if (tlAndN.m_num != num2)
{
compCurStmtNum = blk->bbStmtNum - 1; // Set compCurStmtNum
#endif
- unsigned outerLoopNum = BasicBlock::NOT_IN_LOOP;
-
// First: visit phi's. If "newVNForPhis", give them new VN's. If not,
// first check to see if all phi args have the same value.
GenTree* firstNonPhi = blk->FirstNonPhiDef();
// can recognize redundant loads with no stores between them.
GenTree* addr = tree->AsIndir()->Addr();
GenTreeLclVarCommon* lclVarTree = nullptr;
- FieldSeqNode* fldSeq1 = nullptr;
FieldSeqNode* fldSeq2 = nullptr;
GenTree* obj = nullptr;
GenTree* staticOffset = nullptr;
ValueNum inxVN = ValueNumStore::NoVN;
FieldSeqNode* fldSeq = nullptr;
- // GenTree* addr = tree->gtOp.gtOp1;
- ValueNum addrVN = addrNvnp.GetLiberal();
-
// Try to parse it.
GenTree* arr = nullptr;
addr->ParseArrayAddress(this, &arrInfo, &arr, &inxVN, &fldSeq);
}
// The mapping(s) must be one-to-one: if the label has a mapping, then the ssaNm must, as well.
ssize_t num2;
- bool b = vnToLabel->Lookup(vn, &num2);
+ bool found = vnToLabel->Lookup(vn, &num2);
+ assert(found);
// And the mappings must be the same.
if (tlAndN.m_num != num2)
{
projects / platform / upstream / coreclr.git / commitdiff