--- /dev/null
+From 2d4293b849ed3cc2a11dc3751b638ebe004f9cb8 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Sun, 30 Jun 2013 21:39:00 +0200
+Subject: drm/gma500: Add generic code for clock calculation
+
+This patch aims to unify the bits and pieces that are common (or similar
+enough) for pll clock calculations. Nothing makes use of this code yet
+That will come in later patches.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 5ea75e0f05d03007369f155c6c67541bc4ec309f)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/Makefile | 1
+ drivers/gpu/drm/gma500/gma_display.c | 143 +++++++++++++++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 74 +++++++++++++++
+ drivers/gpu/drm/gma500/psb_drv.h | 2
+ drivers/gpu/drm/gma500/psb_intel_display.c | 3
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 3
+ 6 files changed, 226 insertions(+)
+ create mode 100644 drivers/gpu/drm/gma500/gma_display.c
+ create mode 100644 drivers/gpu/drm/gma500/gma_display.h
+
+--- a/drivers/gpu/drm/gma500/Makefile
++++ b/drivers/gpu/drm/gma500/Makefile
+@@ -15,6 +15,7 @@ gma500_gfx-y += \
+ mmu.o \
+ power.o \
+ psb_drv.o \
++ gma_display.o \
+ psb_intel_display.o \
+ psb_intel_lvds.o \
+ psb_intel_modes.o \
+--- /dev/null
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -0,0 +1,143 @@
++/*
++ * Copyright © 2006-2011 Intel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Authors:
++ * Eric Anholt <eric@anholt.net>
++ * Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
++ */
++
++#include <drm/drmP.h>
++#include "gma_display.h"
++#include "psb_intel_drv.h"
++#include "psb_intel_reg.h"
++#include "psb_drv.h"
++
++/**
++ * Returns whether any output on the specified pipe is of the specified type
++ */
++bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_mode_config *mode_config = &dev->mode_config;
++ struct drm_connector *l_entry;
++
++ list_for_each_entry(l_entry, &mode_config->connector_list, head) {
++ if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
++ struct psb_intel_encoder *psb_intel_encoder =
++ psb_intel_attached_encoder(l_entry);
++ if (psb_intel_encoder->type == type)
++ return true;
++ }
++ }
++
++ return false;
++}
++
++#define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
++
++bool gma_pll_is_valid(struct drm_crtc *crtc,
++ const struct gma_limit_t *limit,
++ struct gma_clock_t *clock)
++{
++ if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
++ GMA_PLL_INVALID("p1 out of range");
++ if (clock->p < limit->p.min || limit->p.max < clock->p)
++ GMA_PLL_INVALID("p out of range");
++ if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
++ GMA_PLL_INVALID("m2 out of range");
++ if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
++ GMA_PLL_INVALID("m1 out of range");
++ /* On CDV m1 is always 0 */
++ if (clock->m1 <= clock->m2 && clock->m1 != 0)
++ GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
++ if (clock->m < limit->m.min || limit->m.max < clock->m)
++ GMA_PLL_INVALID("m out of range");
++ if (clock->n < limit->n.min || limit->n.max < clock->n)
++ GMA_PLL_INVALID("n out of range");
++ if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
++ GMA_PLL_INVALID("vco out of range");
++ /* XXX: We may need to be checking "Dot clock"
++ * depending on the multiplier, connector, etc.,
++ * rather than just a single range.
++ */
++ if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
++ GMA_PLL_INVALID("dot out of range");
++
++ return true;
++}
++
++bool gma_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target, int refclk,
++ struct gma_clock_t *best_clock)
++{
++ struct drm_device *dev = crtc->dev;
++ const struct gma_clock_funcs *clock_funcs =
++ to_psb_intel_crtc(crtc)->clock_funcs;
++ struct gma_clock_t clock;
++ int err = target;
++
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
++ (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
++ /*
++ * For LVDS, if the panel is on, just rely on its current
++ * settings for dual-channel. We haven't figured out how to
++ * reliably set up different single/dual channel state, if we
++ * even can.
++ */
++ if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
++ LVDS_CLKB_POWER_UP)
++ clock.p2 = limit->p2.p2_fast;
++ else
++ clock.p2 = limit->p2.p2_slow;
++ } else {
++ if (target < limit->p2.dot_limit)
++ clock.p2 = limit->p2.p2_slow;
++ else
++ clock.p2 = limit->p2.p2_fast;
++ }
++
++ memset(best_clock, 0, sizeof(*best_clock));
++
++ /* m1 is always 0 on CDV so the outmost loop will run just once */
++ for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
++ for (clock.m2 = limit->m2.min;
++ (clock.m2 < clock.m1 || clock.m1 == 0) &&
++ clock.m2 <= limit->m2.max; clock.m2++) {
++ for (clock.n = limit->n.min;
++ clock.n <= limit->n.max; clock.n++) {
++ for (clock.p1 = limit->p1.min;
++ clock.p1 <= limit->p1.max;
++ clock.p1++) {
++ int this_err;
++
++ clock_funcs->clock(refclk, &clock);
++
++ if (!clock_funcs->pll_is_valid(crtc,
++ limit, &clock))
++ continue;
++
++ this_err = abs(clock.dot - target);
++ if (this_err < err) {
++ *best_clock = clock;
++ err = this_err;
++ }
++ }
++ }
++ }
++ }
++
++ return err != target;
++}
+--- /dev/null
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -0,0 +1,74 @@
++/*
++ * Copyright © 2006-2011 Intel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Authors:
++ * Eric Anholt <eric@anholt.net>
++ * Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
++ */
++
++#ifndef _GMA_DISPLAY_H_
++#define _GMA_DISPLAY_H_
++
++struct gma_clock_t {
++ /* given values */
++ int n;
++ int m1, m2;
++ int p1, p2;
++ /* derived values */
++ int dot;
++ int vco;
++ int m;
++ int p;
++};
++
++struct gma_range_t {
++ int min, max;
++};
++
++struct gma_p2_t {
++ int dot_limit;
++ int p2_slow, p2_fast;
++};
++
++struct gma_limit_t {
++ struct gma_range_t dot, vco, n, m, m1, m2, p, p1;
++ struct gma_p2_t p2;
++ bool (*find_pll)(const struct gma_limit_t *, struct drm_crtc *,
++ int target, int refclk,
++ struct gma_clock_t *best_clock);
++};
++
++struct gma_clock_funcs {
++ void (*clock)(int refclk, struct gma_clock_t *clock);
++ const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
++ bool (*pll_is_valid)(struct drm_crtc *crtc,
++ const struct gma_limit_t *limit,
++ struct gma_clock_t *clock);
++};
++
++/* Common pipe related functions */
++extern bool gma_pipe_has_type(struct drm_crtc *crtc, int type);
++
++/* Common clock related functions */
++extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
++extern void gma_clock(int refclk, struct gma_clock_t *clock);
++extern bool gma_pll_is_valid(struct drm_crtc *crtc,
++ const struct gma_limit_t *limit,
++ struct gma_clock_t *clock);
++extern bool gma_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target, int refclk,
++ struct gma_clock_t *best_clock);
++#endif
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -27,6 +27,7 @@
+ #include <drm/gma_drm.h>
+ #include "psb_reg.h"
+ #include "psb_intel_drv.h"
++#include "gma_display.h"
+ #include "intel_bios.h"
+ #include "gtt.h"
+ #include "power.h"
+@@ -676,6 +677,7 @@ struct psb_ops {
+ /* Sub functions */
+ struct drm_crtc_helper_funcs const *crtc_helper;
+ struct drm_crtc_funcs const *crtc_funcs;
++ const struct gma_clock_funcs *clock_funcs;
+
+ /* Setup hooks */
+ int (*chip_setup)(struct drm_device *dev);
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -1251,6 +1251,9 @@ void psb_intel_crtc_init(struct drm_devi
+ /* Set the CRTC operations from the chip specific data */
+ drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
+
++ /* Set the CRTC clock functions from chip specific data */
++ psb_intel_crtc->clock_funcs = dev_priv->ops->clock_funcs;
++
+ drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
+ psb_intel_crtc->pipe = pipe;
+ psb_intel_crtc->plane = pipe;
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -24,6 +24,7 @@
+ #include <drm/drm_crtc.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <linux/gpio.h>
++#include "gma_display.h"
+
+ /*
+ * Display related stuff
+@@ -188,6 +189,8 @@ struct psb_intel_crtc {
+
+ /* Saved Crtc HW states */
+ struct psb_intel_crtc_state *crtc_state;
++
++ const struct gma_clock_funcs *clock_funcs;
+ };
+
+ #define to_psb_intel_crtc(x) \
--- /dev/null
+From 070e5cc463b922114ea8481ebfaead907198dd70 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 1 Jul 2013 01:42:16 +0200
+Subject: drm/gma500/cdv: Make use of the generic clock code
+
+Add chip specific callbacks for the generic and non-generic clock
+calculation code. Also remove as much dupilicated code as possible.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 2adb29ff61c97982addf702d7da106569e217329)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_device.c | 1
+ drivers/gpu/drm/gma500/cdv_device.h | 1
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 197 +++++------------------------
+ 3 files changed, 36 insertions(+), 163 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_device.c
++++ b/drivers/gpu/drm/gma500/cdv_device.c
+@@ -641,6 +641,7 @@ const struct psb_ops cdv_chip_ops = {
+
+ .crtc_helper = &cdv_intel_helper_funcs,
+ .crtc_funcs = &cdv_intel_crtc_funcs,
++ .clock_funcs = &cdv_clock_funcs,
+
+ .output_init = cdv_output_init,
+ .hotplug = cdv_hotplug_event,
+--- a/drivers/gpu/drm/gma500/cdv_device.h
++++ b/drivers/gpu/drm/gma500/cdv_device.h
+@@ -17,6 +17,7 @@
+
+ extern const struct drm_crtc_helper_funcs cdv_intel_helper_funcs;
+ extern const struct drm_crtc_funcs cdv_intel_crtc_funcs;
++extern const struct gma_clock_funcs cdv_clock_funcs;
+ extern void cdv_intel_crt_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev);
+ extern void cdv_intel_lvds_init(struct drm_device *dev,
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -30,43 +30,10 @@
+ #include "power.h"
+ #include "cdv_device.h"
+
++static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk, struct gma_clock_t *best_clock);
+
+-struct cdv_intel_range_t {
+- int min, max;
+-};
+-
+-struct cdv_intel_p2_t {
+- int dot_limit;
+- int p2_slow, p2_fast;
+-};
+-
+-struct cdv_intel_clock_t {
+- /* given values */
+- int n;
+- int m1, m2;
+- int p1, p2;
+- /* derived values */
+- int dot;
+- int vco;
+- int m;
+- int p;
+-};
+-
+-#define INTEL_P2_NUM 2
+-
+-struct cdv_intel_limit_t {
+- struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
+- struct cdv_intel_p2_t p2;
+- bool (*find_pll)(const struct cdv_intel_limit_t *, struct drm_crtc *,
+- int, int, struct cdv_intel_clock_t *);
+-};
+-
+-static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
+- struct drm_crtc *crtc, int target, int refclk,
+- struct cdv_intel_clock_t *best_clock);
+-static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target,
+- int refclk,
+- struct cdv_intel_clock_t *best_clock);
+
+ #define CDV_LIMIT_SINGLE_LVDS_96 0
+ #define CDV_LIMIT_SINGLE_LVDS_100 1
+@@ -75,7 +42,7 @@ static bool cdv_intel_find_dp_pll(const
+ #define CDV_LIMIT_DP_27 4
+ #define CDV_LIMIT_DP_100 5
+
+-static const struct cdv_intel_limit_t cdv_intel_limits[] = {
++static const struct gma_limit_t cdv_intel_limits[] = {
+ { /* CDV_SINGLE_LVDS_96MHz */
+ .dot = {.min = 20000, .max = 115500},
+ .vco = {.min = 1800000, .max = 3600000},
+@@ -85,9 +52,8 @@ static const struct cdv_intel_limit_t cd
+ .m2 = {.min = 58, .max = 158},
+ .p = {.min = 28, .max = 140},
+ .p1 = {.min = 2, .max = 10},
+- .p2 = {.dot_limit = 200000,
+- .p2_slow = 14, .p2_fast = 14},
+- .find_pll = cdv_intel_find_best_PLL,
++ .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
++ .find_pll = gma_find_best_pll,
+ },
+ { /* CDV_SINGLE_LVDS_100MHz */
+ .dot = {.min = 20000, .max = 115500},
+@@ -102,7 +68,7 @@ static const struct cdv_intel_limit_t cd
+ * is 80-224Mhz. Prefer single channel as much as possible.
+ */
+ .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
+- .find_pll = cdv_intel_find_best_PLL,
++ .find_pll = gma_find_best_pll,
+ },
+ { /* CDV_DAC_HDMI_27MHz */
+ .dot = {.min = 20000, .max = 400000},
+@@ -114,7 +80,7 @@ static const struct cdv_intel_limit_t cd
+ .p = {.min = 5, .max = 90},
+ .p1 = {.min = 1, .max = 9},
+ .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
+- .find_pll = cdv_intel_find_best_PLL,
++ .find_pll = gma_find_best_pll,
+ },
+ { /* CDV_DAC_HDMI_96MHz */
+ .dot = {.min = 20000, .max = 400000},
+@@ -126,7 +92,7 @@ static const struct cdv_intel_limit_t cd
+ .p = {.min = 5, .max = 100},
+ .p1 = {.min = 1, .max = 10},
+ .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
+- .find_pll = cdv_intel_find_best_PLL,
++ .find_pll = gma_find_best_pll,
+ },
+ { /* CDV_DP_27MHz */
+ .dot = {.min = 160000, .max = 272000},
+@@ -255,7 +221,7 @@ void cdv_sb_reset(struct drm_device *dev
+ */
+ static int
+ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
+- struct cdv_intel_clock_t *clock, bool is_lvds, u32 ddi_select)
++ struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
+ {
+ struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
+ int pipe = psb_crtc->pipe;
+@@ -405,31 +371,11 @@ cdv_dpll_set_clock_cdv(struct drm_device
+ return 0;
+ }
+
+-/*
+- * Returns whether any encoder on the specified pipe is of the specified type
+- */
+-static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_mode_config *mode_config = &dev->mode_config;
+- struct drm_connector *l_entry;
+-
+- list_for_each_entry(l_entry, &mode_config->connector_list, head) {
+- if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
+- struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(l_entry);
+- if (psb_intel_encoder->type == type)
+- return true;
+- }
+- }
+- return false;
+-}
+-
+-static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
+- int refclk)
++static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
++ int refclk)
+ {
+- const struct cdv_intel_limit_t *limit;
+- if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
++ const struct gma_limit_t *limit;
++ if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+ /*
+ * Now only single-channel LVDS is supported on CDV. If it is
+ * incorrect, please add the dual-channel LVDS.
+@@ -454,8 +400,7 @@ static const struct cdv_intel_limit_t *c
+ }
+
+ /* m1 is reserved as 0 in CDV, n is a ring counter */
+-static void cdv_intel_clock(struct drm_device *dev,
+- int refclk, struct cdv_intel_clock_t *clock)
++static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
+ {
+ clock->m = clock->m2 + 2;
+ clock->p = clock->p1 * clock->p2;
+@@ -463,93 +408,12 @@ static void cdv_intel_clock(struct drm_d
+ clock->dot = clock->vco / clock->p;
+ }
+
+-
+-#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
+-static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
+- const struct cdv_intel_limit_t *limit,
+- struct cdv_intel_clock_t *clock)
+-{
+- if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
+- INTELPllInvalid("p1 out of range\n");
+- if (clock->p < limit->p.min || limit->p.max < clock->p)
+- INTELPllInvalid("p out of range\n");
+- /* unnecessary to check the range of m(m1/M2)/n again */
+- if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
+- INTELPllInvalid("vco out of range\n");
+- /* XXX: We may need to be checking "Dot clock"
+- * depending on the multiplier, connector, etc.,
+- * rather than just a single range.
+- */
+- if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
+- INTELPllInvalid("dot out of range\n");
+-
+- return true;
+-}
+-
+-static bool cdv_intel_find_best_PLL(const struct cdv_intel_limit_t *limit,
+- struct drm_crtc *crtc, int target, int refclk,
+- struct cdv_intel_clock_t *best_clock)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct cdv_intel_clock_t clock;
+- int err = target;
+-
+-
+- if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+- (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
+- /*
+- * For LVDS, if the panel is on, just rely on its current
+- * settings for dual-channel. We haven't figured out how to
+- * reliably set up different single/dual channel state, if we
+- * even can.
+- */
+- if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
+- LVDS_CLKB_POWER_UP)
+- clock.p2 = limit->p2.p2_fast;
+- else
+- clock.p2 = limit->p2.p2_slow;
+- } else {
+- if (target < limit->p2.dot_limit)
+- clock.p2 = limit->p2.p2_slow;
+- else
+- clock.p2 = limit->p2.p2_fast;
+- }
+-
+- memset(best_clock, 0, sizeof(*best_clock));
+- clock.m1 = 0;
+- /* m1 is reserved as 0 in CDV, n is a ring counter.
+- So skip the m1 loop */
+- for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
+- for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
+- clock.m2++) {
+- for (clock.p1 = limit->p1.min;
+- clock.p1 <= limit->p1.max;
+- clock.p1++) {
+- int this_err;
+-
+- cdv_intel_clock(dev, refclk, &clock);
+-
+- if (!cdv_intel_PLL_is_valid(crtc,
+- limit, &clock))
+- continue;
+-
+- this_err = abs(clock.dot - target);
+- if (this_err < err) {
+- *best_clock = clock;
+- err = this_err;
+- }
+- }
+- }
+- }
+-
+- return err != target;
+-}
+-
+-static bool cdv_intel_find_dp_pll(const struct cdv_intel_limit_t *limit, struct drm_crtc *crtc, int target,
+- int refclk,
+- struct cdv_intel_clock_t *best_clock)
++static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk,
++ struct gma_clock_t *best_clock)
+ {
+- struct cdv_intel_clock_t clock;
++ struct gma_clock_t clock;
+ if (refclk == 27000) {
+ if (target < 200000) {
+ clock.p1 = 2;
+@@ -584,7 +448,7 @@ static bool cdv_intel_find_dp_pll(const
+ clock.p = clock.p1 * clock.p2;
+ clock.vco = (refclk * clock.m) / clock.n;
+ clock.dot = clock.vco / clock.p;
+- memcpy(best_clock, &clock, sizeof(struct cdv_intel_clock_t));
++ memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
+ return true;
+ }
+
+@@ -1035,14 +899,14 @@ static int cdv_intel_crtc_mode_set(struc
+ int pipe = psb_intel_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk;
+- struct cdv_intel_clock_t clock;
++ struct gma_clock_t clock;
+ u32 dpll = 0, dspcntr, pipeconf;
+ bool ok;
+ bool is_crt = false, is_lvds = false, is_tv = false;
+ bool is_hdmi = false, is_dp = false;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_connector *connector;
+- const struct cdv_intel_limit_t *limit;
++ const struct gma_limit_t *limit;
+ u32 ddi_select = 0;
+ bool is_edp = false;
+
+@@ -1108,12 +972,13 @@ static int cdv_intel_crtc_mode_set(struc
+
+ drm_mode_debug_printmodeline(adjusted_mode);
+
+- limit = cdv_intel_limit(crtc, refclk);
++ limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
+
+ ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
+ &clock);
+ if (!ok) {
+- dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
++ DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
++ adjusted_mode->clock, clock.dot);
+ return 0;
+ }
+
+@@ -1612,7 +1477,7 @@ static int cdv_crtc_set_config(struct dr
+
+ /* FIXME: why are we using this, should it be cdv_ in this tree ? */
+
+-static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
++static void i8xx_clock(int refclk, struct gma_clock_t *clock)
+ {
+ clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
+ clock->p = clock->p1 * clock->p2;
+@@ -1630,7 +1495,7 @@ static int cdv_intel_crtc_clock_get(stru
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 dpll;
+ u32 fp;
+- struct cdv_intel_clock_t clock;
++ struct gma_clock_t clock;
+ bool is_lvds;
+ struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
+
+@@ -1788,3 +1653,9 @@ const struct drm_crtc_funcs cdv_intel_cr
+ .set_config = cdv_crtc_set_config,
+ .destroy = cdv_intel_crtc_destroy,
+ };
++
++const struct gma_clock_funcs cdv_clock_funcs = {
++ .clock = cdv_intel_clock,
++ .limit = cdv_intel_limit,
++ .pll_is_valid = gma_pll_is_valid,
++};
--- /dev/null
+From 1752120eac763847e20e55d68b54f163d61541bc Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Tue, 2 Jul 2013 17:02:22 +0200
+Subject: drm/gma500: Make use of gma_pipe_has_type()
+
+Replace any use of xxx_intel_pipe_has_type() with the generic
+gma_pipe_has_type() function. Poulsbo still use it but that will be
+removed when we rip out psb_intel_pipe_has_type().
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit fe477cc1b09ecd957c8c201b4f9c84e9d03621d4)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 8 ++++----
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 8 ++++----
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 6 +++---
+ 3 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -26,7 +26,7 @@
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
+-#include "psb_intel_display.h"
++#include "gma_display.h"
+ #include "power.h"
+ #include "cdv_device.h"
+
+@@ -375,7 +375,7 @@ static const struct gma_limit_t *cdv_int
+ int refclk)
+ {
+ const struct gma_limit_t *limit;
+- if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
+ /*
+ * Now only single-channel LVDS is supported on CDV. If it is
+ * incorrect, please add the dual-channel LVDS.
+@@ -384,8 +384,8 @@ static const struct gma_limit_t *cdv_int
+ limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
+ else
+ limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
+- } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
+- psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
++ } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
++ gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
+ if (refclk == 27000)
+ limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
+ else
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -23,7 +23,7 @@
+
+ #include <drm/drmP.h>
+ #include "psb_intel_reg.h"
+-#include "psb_intel_display.h"
++#include "gma_display.h"
+ #include "framebuffer.h"
+ #include "mdfld_output.h"
+ #include "mdfld_dsi_output.h"
+@@ -611,8 +611,8 @@ static const struct mrst_limit_t *mdfld_
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+- if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)
+- || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) {
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)
++ || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) {
+ if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19))
+ limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19];
+ else if (ksel == KSEL_BYPASS_25)
+@@ -624,7 +624,7 @@ static const struct mrst_limit_t *mdfld_
+ (dev_priv->core_freq == 100 ||
+ dev_priv->core_freq == 200))
+ limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100];
+- } else if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
++ } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+ if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19))
+ limit = &mdfld_limits[MDFLD_LIMT_DPLL_19];
+ else if (ksel == KSEL_BYPASS_25)
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -23,7 +23,7 @@
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
+-#include "psb_intel_display.h"
++#include "gma_display.h"
+ #include "power.h"
+
+ struct psb_intel_range_t {
+@@ -88,8 +88,8 @@ static const struct oaktrail_limit_t *oa
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+- if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+- || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
++ || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
+ switch (dev_priv->core_freq) {
+ case 100:
+ limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L];
--- /dev/null
+From 6ee0194f961ca20c23e0f7034340bcee7b02bc01 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Tue, 2 Jul 2013 17:07:59 +0200
+Subject: drm/gma500/psb: Make use of generic clock code
+
+Add chip specific callbacks for the generic and non-generic clock
+calculation code. Also remove as much dupilicated code as possible.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 7f67c06721641df12ed68249218d1c2118517f78)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_device.c | 3
+ drivers/gpu/drm/gma500/psb_device.h | 24 +++
+ drivers/gpu/drm/gma500/psb_intel_display.c | 189 +++--------------------------
+ drivers/gpu/drm/gma500/psb_intel_display.h | 2
+ 4 files changed, 51 insertions(+), 167 deletions(-)
+ create mode 100644 drivers/gpu/drm/gma500/psb_device.h
+
+--- a/drivers/gpu/drm/gma500/psb_device.c
++++ b/drivers/gpu/drm/gma500/psb_device.c
+@@ -25,7 +25,7 @@
+ #include "psb_reg.h"
+ #include "psb_intel_reg.h"
+ #include "intel_bios.h"
+-
++#include "psb_device.h"
+
+ static int psb_output_init(struct drm_device *dev)
+ {
+@@ -380,6 +380,7 @@ const struct psb_ops psb_chip_ops = {
+
+ .crtc_helper = &psb_intel_helper_funcs,
+ .crtc_funcs = &psb_intel_crtc_funcs,
++ .clock_funcs = &psb_clock_funcs,
+
+ .output_init = psb_output_init,
+
+--- /dev/null
++++ b/drivers/gpu/drm/gma500/psb_device.h
+@@ -0,0 +1,24 @@
++/*
++ * Copyright © 2013 Patrik Jakobsson
++ * Copyright © 2011 Intel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef _PSB_DEVICE_H_
++#define _PSB_DEVICE_H_
++
++extern const struct gma_clock_funcs psb_clock_funcs;
++
++#endif
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -26,39 +26,13 @@
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
+-#include "psb_intel_display.h"
++#include "gma_display.h"
+ #include "power.h"
+
+-struct psb_intel_clock_t {
+- /* given values */
+- int n;
+- int m1, m2;
+- int p1, p2;
+- /* derived values */
+- int dot;
+- int vco;
+- int m;
+- int p;
+-};
+-
+-struct psb_intel_range_t {
+- int min, max;
+-};
+-
+-struct psb_intel_p2_t {
+- int dot_limit;
+- int p2_slow, p2_fast;
+-};
+-
+-struct psb_intel_limit_t {
+- struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1;
+- struct psb_intel_p2_t p2;
+-};
+-
+ #define INTEL_LIMIT_I9XX_SDVO_DAC 0
+ #define INTEL_LIMIT_I9XX_LVDS 1
+
+-static const struct psb_intel_limit_t psb_intel_limits[] = {
++static const struct gma_limit_t psb_intel_limits[] = {
+ { /* INTEL_LIMIT_I9XX_SDVO_DAC */
+ .dot = {.min = 20000, .max = 400000},
+ .vco = {.min = 1400000, .max = 2800000},
+@@ -68,8 +42,8 @@ static const struct psb_intel_limit_t ps
+ .m2 = {.min = 3, .max = 7},
+ .p = {.min = 5, .max = 80},
+ .p1 = {.min = 1, .max = 8},
+- .p2 = {.dot_limit = 200000,
+- .p2_slow = 10, .p2_fast = 5},
++ .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
++ .find_pll = gma_find_best_pll,
+ },
+ { /* INTEL_LIMIT_I9XX_LVDS */
+ .dot = {.min = 20000, .max = 400000},
+@@ -83,23 +57,24 @@ static const struct psb_intel_limit_t ps
+ /* The single-channel range is 25-112Mhz, and dual-channel
+ * is 80-224Mhz. Prefer single channel as much as possible.
+ */
+- .p2 = {.dot_limit = 112000,
+- .p2_slow = 14, .p2_fast = 7},
++ .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
++ .find_pll = gma_find_best_pll,
+ },
+ };
+
+-static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc)
++static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
++ int refclk)
+ {
+- const struct psb_intel_limit_t *limit;
++ const struct gma_limit_t *limit;
+
+- if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
+ limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
+ else
+ limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
+ return limit;
+ }
+
+-static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock)
++static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
+ {
+ clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
+ clock->p = clock->p1 * clock->p2;
+@@ -107,130 +82,6 @@ static void psb_intel_clock(int refclk,
+ clock->dot = clock->vco / clock->p;
+ }
+
+-/**
+- * Returns whether any output on the specified pipe is of the specified type
+- */
+-bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_mode_config *mode_config = &dev->mode_config;
+- struct drm_connector *l_entry;
+-
+- list_for_each_entry(l_entry, &mode_config->connector_list, head) {
+- if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
+- struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(l_entry);
+- if (psb_intel_encoder->type == type)
+- return true;
+- }
+- }
+- return false;
+-}
+-
+-#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
+-/**
+- * Returns whether the given set of divisors are valid for a given refclk with
+- * the given connectors.
+- */
+-
+-static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc,
+- struct psb_intel_clock_t *clock)
+-{
+- const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
+-
+- if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
+- INTELPllInvalid("p1 out of range\n");
+- if (clock->p < limit->p.min || limit->p.max < clock->p)
+- INTELPllInvalid("p out of range\n");
+- if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
+- INTELPllInvalid("m2 out of range\n");
+- if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
+- INTELPllInvalid("m1 out of range\n");
+- if (clock->m1 <= clock->m2)
+- INTELPllInvalid("m1 <= m2\n");
+- if (clock->m < limit->m.min || limit->m.max < clock->m)
+- INTELPllInvalid("m out of range\n");
+- if (clock->n < limit->n.min || limit->n.max < clock->n)
+- INTELPllInvalid("n out of range\n");
+- if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
+- INTELPllInvalid("vco out of range\n");
+- /* XXX: We may need to be checking "Dot clock"
+- * depending on the multiplier, connector, etc.,
+- * rather than just a single range.
+- */
+- if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
+- INTELPllInvalid("dot out of range\n");
+-
+- return true;
+-}
+-
+-/**
+- * Returns a set of divisors for the desired target clock with the given
+- * refclk, or FALSE. The returned values represent the clock equation:
+- * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+- */
+-static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target,
+- int refclk,
+- struct psb_intel_clock_t *best_clock)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct psb_intel_clock_t clock;
+- const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
+- int err = target;
+-
+- if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
+- (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
+- /*
+- * For LVDS, if the panel is on, just rely on its current
+- * settings for dual-channel. We haven't figured out how to
+- * reliably set up different single/dual channel state, if we
+- * even can.
+- */
+- if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
+- LVDS_CLKB_POWER_UP)
+- clock.p2 = limit->p2.p2_fast;
+- else
+- clock.p2 = limit->p2.p2_slow;
+- } else {
+- if (target < limit->p2.dot_limit)
+- clock.p2 = limit->p2.p2_slow;
+- else
+- clock.p2 = limit->p2.p2_fast;
+- }
+-
+- memset(best_clock, 0, sizeof(*best_clock));
+-
+- for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
+- clock.m1++) {
+- for (clock.m2 = limit->m2.min;
+- clock.m2 < clock.m1 && clock.m2 <= limit->m2.max;
+- clock.m2++) {
+- for (clock.n = limit->n.min;
+- clock.n <= limit->n.max; clock.n++) {
+- for (clock.p1 = limit->p1.min;
+- clock.p1 <= limit->p1.max;
+- clock.p1++) {
+- int this_err;
+-
+- psb_intel_clock(refclk, &clock);
+-
+- if (!psb_intel_PLL_is_valid
+- (crtc, &clock))
+- continue;
+-
+- this_err = abs(clock.dot - target);
+- if (this_err < err) {
+- *best_clock = clock;
+- err = this_err;
+- }
+- }
+- }
+- }
+- }
+-
+- return err != target;
+-}
+-
+ void psb_intel_wait_for_vblank(struct drm_device *dev)
+ {
+ /* Wait for 20ms, i.e. one cycle at 50hz. */
+@@ -484,12 +335,13 @@ static int psb_intel_crtc_mode_set(struc
+ int pipe = psb_intel_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk;
+- struct psb_intel_clock_t clock;
++ struct gma_clock_t clock;
+ u32 dpll = 0, fp = 0, dspcntr, pipeconf;
+ bool ok, is_sdvo = false;
+ bool is_lvds = false, is_tv = false;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_connector *connector;
++ const struct gma_limit_t *limit;
+
+ /* No scan out no play */
+ if (crtc->fb == NULL) {
+@@ -520,10 +372,13 @@ static int psb_intel_crtc_mode_set(struc
+
+ refclk = 96000;
+
+- ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
++ limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
++
++ ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
+ &clock);
+ if (!ok) {
+- dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
++ DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
++ adjusted_mode->clock, clock.dot);
+ return 0;
+ }
+
+@@ -1022,7 +877,7 @@ static int psb_intel_crtc_clock_get(stru
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 dpll;
+ u32 fp;
+- struct psb_intel_clock_t clock;
++ struct gma_clock_t clock;
+ bool is_lvds;
+ struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
+
+@@ -1190,6 +1045,12 @@ const struct drm_crtc_funcs psb_intel_cr
+ .destroy = psb_intel_crtc_destroy,
+ };
+
++const struct gma_clock_funcs psb_clock_funcs = {
++ .clock = psb_intel_clock,
++ .limit = psb_intel_limit,
++ .pll_is_valid = gma_pll_is_valid,
++};
++
+ /*
+ * Set the default value of cursor control and base register
+ * to zero. This is a workaround for h/w defect on Oaktrail
+--- a/drivers/gpu/drm/gma500/psb_intel_display.h
++++ b/drivers/gpu/drm/gma500/psb_intel_display.h
+@@ -20,6 +20,4 @@
+ #ifndef _INTEL_DISPLAY_H_
+ #define _INTEL_DISPLAY_H_
+
+-bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type);
+-
+ #endif
--- /dev/null
+From bc4141913f69e2b63a2961df2f4c921d3990754e Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 1 Jul 2013 23:14:58 +0200
+Subject: drm/gma500: Remove the unused psb_intel_display.h
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit f0e9d89b9b7f3c4b1d21ca2e0d25e3ebe5d2a1d2)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.h | 23 -----------------------
+ 1 file changed, 23 deletions(-)
+ delete mode 100644 drivers/gpu/drm/gma500/psb_intel_display.h
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.h
++++ /dev/null
+@@ -1,23 +0,0 @@
+-/* copyright (c) 2008, Intel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms and conditions of the GNU General Public License,
+- * version 2, as published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; if not, write to the Free Software Foundation, Inc.,
+- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+- *
+- * Authors:
+- * Eric Anholt <eric@anholt.net>
+- */
+-
+-#ifndef _INTEL_DISPLAY_H_
+-#define _INTEL_DISPLAY_H_
+-
+-#endif
--- /dev/null
+From b302ccd0260d27ed03ad8e2c955c5c02408671b6 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 5 Jul 2013 16:41:49 +0200
+Subject: drm/gma500: Add generic pipe/crtc functions
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 2eff0b3359c097bbcfe4850dfdf9c94e514ddfee)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/gma_display.c | 326 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 14 +
+ 2 files changed, 340 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -24,6 +24,7 @@
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
+ #include "psb_drv.h"
++#include "framebuffer.h"
+
+ /**
+ * Returns whether any output on the specified pipe is of the specified type
+@@ -46,6 +47,331 @@ bool gma_pipe_has_type(struct drm_crtc *
+ return false;
+ }
+
++void gma_wait_for_vblank(struct drm_device *dev)
++{
++ /* Wait for 20ms, i.e. one cycle at 50hz. */
++ mdelay(20);
++}
++
++int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
++ struct drm_framebuffer *old_fb)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
++ int pipe = psb_intel_crtc->pipe;
++ const struct psb_offset *map = &dev_priv->regmap[pipe];
++ unsigned long start, offset;
++ u32 dspcntr;
++ int ret = 0;
++
++ if (!gma_power_begin(dev, true))
++ return 0;
++
++ /* no fb bound */
++ if (!crtc->fb) {
++ dev_err(dev->dev, "No FB bound\n");
++ goto gma_pipe_cleaner;
++ }
++
++ /* We are displaying this buffer, make sure it is actually loaded
++ into the GTT */
++ ret = psb_gtt_pin(psbfb->gtt);
++ if (ret < 0)
++ goto gma_pipe_set_base_exit;
++ start = psbfb->gtt->offset;
++ offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
++
++ REG_WRITE(map->stride, crtc->fb->pitches[0]);
++
++ dspcntr = REG_READ(map->cntr);
++ dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
++
++ switch (crtc->fb->bits_per_pixel) {
++ case 8:
++ dspcntr |= DISPPLANE_8BPP;
++ break;
++ case 16:
++ if (crtc->fb->depth == 15)
++ dspcntr |= DISPPLANE_15_16BPP;
++ else
++ dspcntr |= DISPPLANE_16BPP;
++ break;
++ case 24:
++ case 32:
++ dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
++ break;
++ default:
++ dev_err(dev->dev, "Unknown color depth\n");
++ ret = -EINVAL;
++ goto gma_pipe_set_base_exit;
++ }
++ REG_WRITE(map->cntr, dspcntr);
++
++ dev_dbg(dev->dev,
++ "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
++
++ /* FIXME: Investigate whether this really is the base for psb and why
++ the linear offset is named base for the other chips. map->surf
++ should be the base and map->linoff the offset for all chips */
++ if (IS_PSB(dev)) {
++ REG_WRITE(map->base, offset + start);
++ REG_READ(map->base);
++ } else {
++ REG_WRITE(map->base, offset);
++ REG_READ(map->base);
++ REG_WRITE(map->surf, start);
++ REG_READ(map->surf);
++ }
++
++gma_pipe_cleaner:
++ /* If there was a previous display we can now unpin it */
++ if (old_fb)
++ psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
++
++gma_pipe_set_base_exit:
++ gma_power_end(dev);
++ return ret;
++}
++
++/* Loads the palette/gamma unit for the CRTC with the prepared values */
++void gma_crtc_load_lut(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ int palreg = map->palette;
++ int i;
++
++ /* The clocks have to be on to load the palette. */
++ if (!crtc->enabled)
++ return;
++
++ if (gma_power_begin(dev, false)) {
++ for (i = 0; i < 256; i++) {
++ REG_WRITE(palreg + 4 * i,
++ ((psb_intel_crtc->lut_r[i] +
++ psb_intel_crtc->lut_adj[i]) << 16) |
++ ((psb_intel_crtc->lut_g[i] +
++ psb_intel_crtc->lut_adj[i]) << 8) |
++ (psb_intel_crtc->lut_b[i] +
++ psb_intel_crtc->lut_adj[i]));
++ }
++ gma_power_end(dev);
++ } else {
++ for (i = 0; i < 256; i++) {
++ /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
++ dev_priv->regs.pipe[0].palette[i] =
++ ((psb_intel_crtc->lut_r[i] +
++ psb_intel_crtc->lut_adj[i]) << 16) |
++ ((psb_intel_crtc->lut_g[i] +
++ psb_intel_crtc->lut_adj[i]) << 8) |
++ (psb_intel_crtc->lut_b[i] +
++ psb_intel_crtc->lut_adj[i]);
++ }
++
++ }
++}
++
++void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
++ u32 start, u32 size)
++{
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ int i;
++ int end = (start + size > 256) ? 256 : start + size;
++
++ for (i = start; i < end; i++) {
++ psb_intel_crtc->lut_r[i] = red[i] >> 8;
++ psb_intel_crtc->lut_g[i] = green[i] >> 8;
++ psb_intel_crtc->lut_b[i] = blue[i] >> 8;
++ }
++
++ gma_crtc_load_lut(crtc);
++}
++
++/**
++ * Sets the power management mode of the pipe and plane.
++ *
++ * This code should probably grow support for turning the cursor off and back
++ * on appropriately at the same time as we're turning the pipe off/on.
++ */
++void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ int pipe = psb_intel_crtc->pipe;
++ const struct psb_offset *map = &dev_priv->regmap[pipe];
++ u32 temp;
++
++ /* XXX: When our outputs are all unaware of DPMS modes other than off
++ * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
++ */
++
++ /* FIXME: Uncomment this when we move cdv to generic dpms
++ if (IS_CDV(dev))
++ cdv_intel_disable_self_refresh(dev);
++ */
++
++ switch (mode) {
++ case DRM_MODE_DPMS_ON:
++ case DRM_MODE_DPMS_STANDBY:
++ case DRM_MODE_DPMS_SUSPEND:
++ if (psb_intel_crtc->active)
++ break;
++
++ psb_intel_crtc->active = true;
++
++ /* Enable the DPLL */
++ temp = REG_READ(map->dpll);
++ if ((temp & DPLL_VCO_ENABLE) == 0) {
++ REG_WRITE(map->dpll, temp);
++ REG_READ(map->dpll);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
++ REG_READ(map->dpll);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
++ REG_READ(map->dpll);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ }
++
++ /* Enable the plane */
++ temp = REG_READ(map->cntr);
++ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
++ REG_WRITE(map->cntr,
++ temp | DISPLAY_PLANE_ENABLE);
++ /* Flush the plane changes */
++ REG_WRITE(map->base, REG_READ(map->base));
++ }
++
++ udelay(150);
++
++ /* Enable the pipe */
++ temp = REG_READ(map->conf);
++ if ((temp & PIPEACONF_ENABLE) == 0)
++ REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
++
++ temp = REG_READ(map->status);
++ temp &= ~(0xFFFF);
++ temp |= PIPE_FIFO_UNDERRUN;
++ REG_WRITE(map->status, temp);
++ REG_READ(map->status);
++
++ gma_crtc_load_lut(crtc);
++
++ /* Give the overlay scaler a chance to enable
++ * if it's on this pipe */
++ /* psb_intel_crtc_dpms_video(crtc, true); TODO */
++ break;
++ case DRM_MODE_DPMS_OFF:
++ if (!psb_intel_crtc->active)
++ break;
++
++ psb_intel_crtc->active = false;
++
++ /* Give the overlay scaler a chance to disable
++ * if it's on this pipe */
++ /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
++
++ /* Disable the VGA plane that we never use */
++ REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
++
++ /* Turn off vblank interrupts */
++ drm_vblank_off(dev, pipe);
++
++ /* Wait for vblank for the disable to take effect */
++ gma_wait_for_vblank(dev);
++
++ /* Disable plane */
++ temp = REG_READ(map->cntr);
++ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
++ REG_WRITE(map->cntr,
++ temp & ~DISPLAY_PLANE_ENABLE);
++ /* Flush the plane changes */
++ REG_WRITE(map->base, REG_READ(map->base));
++ REG_READ(map->base);
++ }
++
++ /* Disable pipe */
++ temp = REG_READ(map->conf);
++ if ((temp & PIPEACONF_ENABLE) != 0) {
++ REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
++ REG_READ(map->conf);
++ }
++
++ /* Wait for vblank for the disable to take effect. */
++ gma_wait_for_vblank(dev);
++
++ udelay(150);
++
++ /* Disable DPLL */
++ temp = REG_READ(map->dpll);
++ if ((temp & DPLL_VCO_ENABLE) != 0) {
++ REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
++ REG_READ(map->dpll);
++ }
++
++ /* Wait for the clocks to turn off. */
++ udelay(150);
++ break;
++ }
++
++ /* FIXME: Uncomment this when we move cdv to generic dpms
++ if (IS_CDV(dev))
++ cdv_intel_update_watermark(dev, crtc);
++ */
++
++ /* Set FIFO watermarks */
++ REG_WRITE(DSPARB, 0x3F3E);
++}
++
++bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
++ const struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ return true;
++}
++
++void gma_crtc_prepare(struct drm_crtc *crtc)
++{
++ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
++ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
++}
++
++void gma_crtc_commit(struct drm_crtc *crtc)
++{
++ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
++ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
++}
++
++void gma_crtc_disable(struct drm_crtc *crtc)
++{
++ struct gtt_range *gt;
++ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
++
++ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
++
++ if (crtc->fb) {
++ gt = to_psb_fb(crtc->fb)->gtt;
++ psb_gtt_unpin(gt);
++ }
++}
++
++void gma_crtc_destroy(struct drm_crtc *crtc)
++{
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++
++ kfree(psb_intel_crtc->crtc_state);
++ drm_crtc_cleanup(crtc);
++ kfree(psb_intel_crtc);
++}
++
+ #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
+
+ bool gma_pll_is_valid(struct drm_crtc *crtc,
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -61,6 +61,20 @@ struct gma_clock_funcs {
+
+ /* Common pipe related functions */
+ extern bool gma_pipe_has_type(struct drm_crtc *crtc, int type);
++extern void gma_wait_for_vblank(struct drm_device *dev);
++extern int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
++ struct drm_framebuffer *old_fb);
++extern void gma_crtc_load_lut(struct drm_crtc *crtc);
++extern void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
++ u16 *blue, u32 start, u32 size);
++extern void gma_crtc_dpms(struct drm_crtc *crtc, int mode);
++extern bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
++ const struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode);
++extern void gma_crtc_prepare(struct drm_crtc *crtc);
++extern void gma_crtc_commit(struct drm_crtc *crtc);
++extern void gma_crtc_disable(struct drm_crtc *crtc);
++extern void gma_crtc_destroy(struct drm_crtc *crtc);
+
+ /* Common clock related functions */
+ extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
--- /dev/null
+From 18ecae097760c83e2428a2bb93aeabab20df280d Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Tue, 9 Jul 2013 20:03:01 +0200
+Subject: drm/gma500/cdv: Use identical generic crtc funcs
+
+This patch makes cdv use the gma_xxx counterparts that are identical. I
+took them in one sweep as they should not cause any regressions.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit ad3c46eae3f51b34adea55e0625d255b21ec0a15)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_device.h | 9 ---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 74 ++++++-----------------------
+ 2 files changed, 16 insertions(+), 67 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_device.h
++++ b/drivers/gpu/drm/gma500/cdv_device.h
+@@ -26,12 +26,3 @@ extern void cdv_hdmi_init(struct drm_dev
+ int reg);
+ extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc);
+-
+-static inline void cdv_intel_wait_for_vblank(struct drm_device *dev)
+-{
+- /* Wait for 20ms, i.e. one cycle at 50hz. */
+- /* FIXME: msleep ?? */
+- mdelay(20);
+-}
+-
+-
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -595,7 +595,7 @@ static void cdv_intel_disable_self_refre
+ REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
+ REG_READ(FW_BLC_SELF);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ /* Cedarview workaround to write ovelay plane, which force to leave
+ * MAX_FIFO state.
+@@ -603,7 +603,7 @@ static void cdv_intel_disable_self_refre
+ REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
+ REG_READ(OV_OVADD);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+ }
+
+ }
+@@ -644,12 +644,12 @@ static void cdv_intel_update_watermark (
+
+ REG_WRITE(DSPFW6, 0x10);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ /* enable self-refresh for single pipe active */
+ REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+ REG_READ(FW_BLC_SELF);
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ } else {
+
+@@ -661,7 +661,7 @@ static void cdv_intel_update_watermark (
+ REG_WRITE(DSPFW5, 0x01010101);
+ REG_WRITE(DSPFW6, 0x1d0);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ cdv_intel_disable_self_refresh(dev);
+
+@@ -812,7 +812,7 @@ static void cdv_intel_crtc_dpms(struct d
+
+ drm_vblank_off(dev, pipe);
+ /* Wait for vblank for the disable to take effect */
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ /* Next, disable display pipes */
+ temp = REG_READ(map->conf);
+@@ -822,7 +822,7 @@ static void cdv_intel_crtc_dpms(struct d
+ }
+
+ /* Wait for vblank for the disable to take effect. */
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ udelay(150);
+
+@@ -851,26 +851,6 @@ static void cdv_intel_crtc_dpms(struct d
+ REG_WRITE(DSPARB, 0x3F3E);
+ }
+
+-static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-}
+-
+-static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+-}
+-
+-static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
+- const struct drm_display_mode *mode,
+- struct drm_display_mode *adjusted_mode)
+-{
+- return true;
+-}
+-
+-
+ /**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+@@ -1129,7 +1109,7 @@ static int cdv_intel_crtc_mode_set(struc
+ REG_WRITE(map->conf, pipeconf);
+ REG_READ(map->conf);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(map->cntr, dspcntr);
+
+@@ -1140,7 +1120,7 @@ static int cdv_intel_crtc_mode_set(struc
+ crtc_funcs->mode_set_base(crtc, x, y, old_fb);
+ }
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ return 0;
+ }
+@@ -1301,12 +1281,12 @@ static void cdv_intel_crtc_restore(struc
+ REG_WRITE(map->base, crtc_state->saveDSPBASE);
+ REG_WRITE(map->conf, crtc_state->savePIPECONF);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
+ REG_WRITE(map->base, crtc_state->saveDSPBASE);
+
+- cdv_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ paletteReg = map->palette;
+ for (i = 0; i < 256; ++i)
+@@ -1612,36 +1592,14 @@ struct drm_display_mode *cdv_intel_crtc_
+ return mode;
+ }
+
+-static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
+-{
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+-
+- kfree(psb_intel_crtc->crtc_state);
+- drm_crtc_cleanup(crtc);
+- kfree(psb_intel_crtc);
+-}
+-
+-static void cdv_intel_crtc_disable(struct drm_crtc *crtc)
+-{
+- struct gtt_range *gt;
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+-
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-
+- if (crtc->fb) {
+- gt = to_psb_fb(crtc->fb)->gtt;
+- psb_gtt_unpin(gt);
+- }
+-}
+-
+ const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
+ .dpms = cdv_intel_crtc_dpms,
+- .mode_fixup = cdv_intel_crtc_mode_fixup,
++ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = cdv_intel_crtc_mode_set,
+ .mode_set_base = cdv_intel_pipe_set_base,
+- .prepare = cdv_intel_crtc_prepare,
+- .commit = cdv_intel_crtc_commit,
+- .disable = cdv_intel_crtc_disable,
++ .prepare = gma_crtc_prepare,
++ .commit = gma_crtc_commit,
++ .disable = gma_crtc_disable,
+ };
+
+ const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
+@@ -1651,7 +1609,7 @@ const struct drm_crtc_funcs cdv_intel_cr
+ .cursor_move = cdv_intel_crtc_cursor_move,
+ .gamma_set = cdv_intel_crtc_gamma_set,
+ .set_config = cdv_crtc_set_config,
+- .destroy = cdv_intel_crtc_destroy,
++ .destroy = gma_crtc_destroy,
+ };
+
+ const struct gma_clock_funcs cdv_clock_funcs = {
--- /dev/null
+From 0fe97c7ececa5575b1f89c811a5a8a8c24cc2e2d Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 01:20:19 +0200
+Subject: drm/gma500: Make all chips use gma_wait_for_vblank
+
+Also remove the duplicated oaktrail function.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit d1fa08f3bacb6fc9a7642c85a4fa8976a3f1afac)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 3 ++-
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 6 +++---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 6 +++---
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 12 +++---------
+ drivers/gpu/drm/gma500/psb_intel_display.c | 16 +++++-----------
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 1 -
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 2 +-
+ 7 files changed, 17 insertions(+), 29 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -34,6 +34,7 @@
+ #include "psb_drv.h"
+ #include "psb_intel_drv.h"
+ #include "psb_intel_reg.h"
++#include "gma_display.h"
+ #include <drm/drm_dp_helper.h>
+
+ #define _wait_for(COND, MS, W) ({ \
+@@ -1317,7 +1318,7 @@ cdv_intel_dp_start_link_train(struct psb
+ /* Enable output, wait for it to become active */
+ REG_WRITE(intel_dp->output_reg, reg);
+ REG_READ(intel_dp->output_reg);
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ DRM_DEBUG_KMS("Link config\n");
+ /* Write the link configuration data */
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -65,7 +65,7 @@ void mdfldWaitForPipeDisable(struct drm_
+ }
+
+ /* FIXME JLIU7_PO */
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+ return;
+
+ /* Wait for for the pipe disable to take effect. */
+@@ -93,7 +93,7 @@ void mdfldWaitForPipeEnable(struct drm_d
+ }
+
+ /* FIXME JLIU7_PO */
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+ return;
+
+ /* Wait for for the pipe enable to take effect. */
+@@ -1034,7 +1034,7 @@ static int mdfld_crtc_mode_set(struct dr
+
+ /* Wait for for the pipe enable to take effect. */
+ REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ mrst_crtc_mode_set_exit:
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -242,7 +242,7 @@ static void oaktrail_crtc_dpms(struct dr
+ REG_READ(map->conf);
+ }
+ /* Wait for for the pipe disable to take effect. */
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ temp = REG_READ(map->dpll);
+ if ((temp & DPLL_VCO_ENABLE) != 0) {
+@@ -484,10 +484,10 @@ static int oaktrail_crtc_mode_set(struct
+
+ REG_WRITE(map->conf, pipeconf);
+ REG_READ(map->conf);
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(map->cntr, dspcntr);
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ oaktrail_crtc_mode_set_exit:
+ gma_power_end(dev);
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -155,12 +155,6 @@ static void oaktrail_hdmi_audio_disable(
+ HDMI_READ(HDMI_HCR);
+ }
+
+-static void wait_for_vblank(struct drm_device *dev)
+-{
+- /* Wait for 20ms, i.e. one cycle at 50hz. */
+- mdelay(20);
+-}
+-
+ static unsigned int htotal_calculate(struct drm_display_mode *mode)
+ {
+ u32 htotal, new_crtc_htotal;
+@@ -372,10 +366,10 @@ int oaktrail_crtc_hdmi_mode_set(struct d
+
+ REG_WRITE(PCH_PIPEBCONF, pipeconf);
+ REG_READ(PCH_PIPEBCONF);
+- wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(dspcntr_reg, dspcntr);
+- wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ gma_power_end(dev);
+
+@@ -459,7 +453,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_
+ REG_READ(PCH_PIPEBCONF);
+ }
+
+- wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ /* Enable plane */
+ temp = REG_READ(DSPBCNTR);
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -82,12 +82,6 @@ static void psb_intel_clock(int refclk,
+ clock->dot = clock->vco / clock->p;
+ }
+
+-void psb_intel_wait_for_vblank(struct drm_device *dev)
+-{
+- /* Wait for 20ms, i.e. one cycle at 50hz. */
+- mdelay(20);
+-}
+-
+ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
+ int x, int y, struct drm_framebuffer *old_fb)
+ {
+@@ -244,7 +238,7 @@ static void psb_intel_crtc_dpms(struct d
+ }
+
+ /* Wait for vblank for the disable to take effect. */
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ temp = REG_READ(map->dpll);
+ if ((temp & DPLL_VCO_ENABLE) != 0) {
+@@ -516,14 +510,14 @@ static int psb_intel_crtc_mode_set(struc
+ REG_WRITE(map->conf, pipeconf);
+ REG_READ(map->conf);
+
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(map->cntr, dspcntr);
+
+ /* Flush the plane changes */
+ crtc_funcs->mode_set_base(crtc, x, y, old_fb);
+
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ return 0;
+ }
+@@ -669,12 +663,12 @@ static void psb_intel_crtc_restore(struc
+ REG_WRITE(map->base, crtc_state->saveDSPBASE);
+ REG_WRITE(map->conf, crtc_state->savePIPECONF);
+
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
+ REG_WRITE(map->base, crtc_state->saveDSPBASE);
+
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ paletteReg = map->palette;
+ for (i = 0; i < 256; ++i)
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -246,7 +246,6 @@ extern struct drm_encoder *psb_intel_bes
+
+ extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc);
+-extern void psb_intel_wait_for_vblank(struct drm_device *dev);
+ extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+ extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev,
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -1121,7 +1121,7 @@ static void psb_intel_sdvo_dpms(struct d
+ if ((temp & SDVO_ENABLE) == 0)
+ psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
+ for (i = 0; i < 2; i++)
+- psb_intel_wait_for_vblank(dev);
++ gma_wait_for_vblank(dev);
+
+ status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
+ /* Warn if the device reported failure to sync.
--- /dev/null
+From 0e5005151d4edbb5e3ce4f5845f6187405a6d6d3 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 17:40:54 +0200
+Subject: drm/gma500/psb: Use identical generic crtc funcs
+
+This patch makes psb use the gma_xxx counterparts that are identical. I
+took them in one sweep as they should not cause any regressions.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 4855177ed0d94621eaf1c6bec64f16318a8be5fe)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 41 ++---------------------------
+ 1 file changed, 4 insertions(+), 37 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -255,18 +255,6 @@ static void psb_intel_crtc_dpms(struct d
+ REG_WRITE(DSPARB, 0x3F3E);
+ }
+
+-static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-}
+-
+-static void psb_intel_crtc_commit(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+-}
+-
+ void psb_intel_encoder_prepare(struct drm_encoder *encoder)
+ {
+ struct drm_encoder_helper_funcs *encoder_funcs =
+@@ -291,14 +279,6 @@ void psb_intel_encoder_destroy(struct dr
+ kfree(intel_encoder);
+ }
+
+-static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
+- const struct drm_display_mode *mode,
+- struct drm_display_mode *adjusted_mode)
+-{
+- return true;
+-}
+-
+-
+ /**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+@@ -1006,27 +986,14 @@ static void psb_intel_crtc_destroy(struc
+ kfree(psb_intel_crtc);
+ }
+
+-static void psb_intel_crtc_disable(struct drm_crtc *crtc)
+-{
+- struct gtt_range *gt;
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+-
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-
+- if (crtc->fb) {
+- gt = to_psb_fb(crtc->fb)->gtt;
+- psb_gtt_unpin(gt);
+- }
+-}
+-
+ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
+ .dpms = psb_intel_crtc_dpms,
+- .mode_fixup = psb_intel_crtc_mode_fixup,
++ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = psb_intel_crtc_mode_set,
+ .mode_set_base = psb_intel_pipe_set_base,
+- .prepare = psb_intel_crtc_prepare,
+- .commit = psb_intel_crtc_commit,
+- .disable = psb_intel_crtc_disable,
++ .prepare = gma_crtc_prepare,
++ .commit = gma_crtc_commit,
++ .disable = gma_crtc_disable,
+ };
+
+ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
--- /dev/null
+From 73ecdc73a813d11daf1db78fb277fefc9470ba8e Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 17:58:04 +0200
+Subject: drm/gma500/cdv: Convert to gma_pipe_set_base()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 3c447166536c80209f0dcb300cdffd76686187aa)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 77 -----------------------------
+ 1 file changed, 1 insertion(+), 76 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -452,81 +452,6 @@ static bool cdv_intel_find_dp_pll(const
+ return true;
+ }
+
+-static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
+- int x, int y, struct drm_framebuffer *old_fb)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+- int pipe = psb_intel_crtc->pipe;
+- const struct psb_offset *map = &dev_priv->regmap[pipe];
+- unsigned long start, offset;
+- u32 dspcntr;
+- int ret = 0;
+-
+- if (!gma_power_begin(dev, true))
+- return 0;
+-
+- /* no fb bound */
+- if (!crtc->fb) {
+- dev_err(dev->dev, "No FB bound\n");
+- goto psb_intel_pipe_cleaner;
+- }
+-
+-
+- /* We are displaying this buffer, make sure it is actually loaded
+- into the GTT */
+- ret = psb_gtt_pin(psbfb->gtt);
+- if (ret < 0)
+- goto psb_intel_pipe_set_base_exit;
+- start = psbfb->gtt->offset;
+- offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
+-
+- REG_WRITE(map->stride, crtc->fb->pitches[0]);
+-
+- dspcntr = REG_READ(map->cntr);
+- dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+-
+- switch (crtc->fb->bits_per_pixel) {
+- case 8:
+- dspcntr |= DISPPLANE_8BPP;
+- break;
+- case 16:
+- if (crtc->fb->depth == 15)
+- dspcntr |= DISPPLANE_15_16BPP;
+- else
+- dspcntr |= DISPPLANE_16BPP;
+- break;
+- case 24:
+- case 32:
+- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+- break;
+- default:
+- dev_err(dev->dev, "Unknown color depth\n");
+- ret = -EINVAL;
+- goto psb_intel_pipe_set_base_exit;
+- }
+- REG_WRITE(map->cntr, dspcntr);
+-
+- dev_dbg(dev->dev,
+- "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
+-
+- REG_WRITE(map->base, offset);
+- REG_READ(map->base);
+- REG_WRITE(map->surf, start);
+- REG_READ(map->surf);
+-
+-psb_intel_pipe_cleaner:
+- /* If there was a previous display we can now unpin it */
+- if (old_fb)
+- psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
+-
+-psb_intel_pipe_set_base_exit:
+- gma_power_end(dev);
+- return ret;
+-}
+-
+ #define FIFO_PIPEA (1 << 0)
+ #define FIFO_PIPEB (1 << 1)
+
+@@ -1596,7 +1521,7 @@ const struct drm_crtc_helper_funcs cdv_i
+ .dpms = cdv_intel_crtc_dpms,
+ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = cdv_intel_crtc_mode_set,
+- .mode_set_base = cdv_intel_pipe_set_base,
++ .mode_set_base = gma_pipe_set_base,
+ .prepare = gma_crtc_prepare,
+ .commit = gma_crtc_commit,
+ .disable = gma_crtc_disable,
--- /dev/null
+From d95dc0b3ee471019ab0b46b0960781318935bead Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 18:12:11 +0200
+Subject: drm/gma500/cdv: Convert to gma_crtc_dpms()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 7ea03f069572fef5701b8be90aed1cfd0b64d76e)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 137 -----------------------------
+ drivers/gpu/drm/gma500/gma_display.c | 4
+ drivers/gpu/drm/gma500/gma_display.h | 5 +
+ 3 files changed, 8 insertions(+), 138 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -512,7 +512,7 @@ static bool is_pipeb_lvds(struct drm_dev
+ return false;
+ }
+
+-static void cdv_intel_disable_self_refresh (struct drm_device *dev)
++void cdv_intel_disable_self_refresh(struct drm_device *dev)
+ {
+ if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
+
+@@ -533,7 +533,7 @@ static void cdv_intel_disable_self_refre
+
+ }
+
+-static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
++void cdv_intel_update_watermark(struct drm_device *dev, struct drm_crtc *crtc)
+ {
+
+ if (cdv_intel_single_pipe_active(dev)) {
+@@ -646,137 +646,6 @@ static void cdv_intel_crtc_load_lut(stru
+ }
+
+ /**
+- * Sets the power management mode of the pipe and plane.
+- *
+- * This code should probably grow support for turning the cursor off and back
+- * on appropriately at the same time as we're turning the pipe off/on.
+- */
+-static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- const struct psb_offset *map = &dev_priv->regmap[pipe];
+- u32 temp;
+-
+- /* XXX: When our outputs are all unaware of DPMS modes other than off
+- * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
+- */
+- cdv_intel_disable_self_refresh(dev);
+-
+- switch (mode) {
+- case DRM_MODE_DPMS_ON:
+- case DRM_MODE_DPMS_STANDBY:
+- case DRM_MODE_DPMS_SUSPEND:
+- if (psb_intel_crtc->active)
+- break;
+-
+- psb_intel_crtc->active = true;
+-
+- /* Enable the DPLL */
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) == 0) {
+- REG_WRITE(map->dpll, temp);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- }
+-
+- /* Jim Bish - switch plan and pipe per scott */
+- /* Enable the plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
+- REG_WRITE(map->cntr,
+- temp | DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- }
+-
+- udelay(150);
+-
+- /* Enable the pipe */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) == 0)
+- REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
+-
+- temp = REG_READ(map->status);
+- temp &= ~(0xFFFF);
+- temp |= PIPE_FIFO_UNDERRUN;
+- REG_WRITE(map->status, temp);
+- REG_READ(map->status);
+-
+- cdv_intel_crtc_load_lut(crtc);
+-
+- /* Give the overlay scaler a chance to enable
+- * if it's on this pipe */
+- /* psb_intel_crtc_dpms_video(crtc, true); TODO */
+- break;
+- case DRM_MODE_DPMS_OFF:
+- if (!psb_intel_crtc->active)
+- break;
+-
+- psb_intel_crtc->active = false;
+-
+- /* Give the overlay scaler a chance to disable
+- * if it's on this pipe */
+- /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
+-
+- /* Disable the VGA plane that we never use */
+- REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+-
+- /* Jim Bish - changed pipe/plane here as well. */
+-
+- drm_vblank_off(dev, pipe);
+- /* Wait for vblank for the disable to take effect */
+- gma_wait_for_vblank(dev);
+-
+- /* Next, disable display pipes */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) != 0) {
+- REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
+- REG_READ(map->conf);
+- }
+-
+- /* Wait for vblank for the disable to take effect. */
+- gma_wait_for_vblank(dev);
+-
+- udelay(150);
+-
+- /* Disable display plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
+- REG_WRITE(map->cntr,
+- temp & ~DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- REG_READ(map->base);
+- }
+-
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) != 0) {
+- REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- }
+-
+- /* Wait for the clocks to turn off. */
+- udelay(150);
+- break;
+- }
+- cdv_intel_update_watermark(dev, crtc);
+- /*Set FIFO Watermarks*/
+- REG_WRITE(DSPARB, 0x3F3E);
+-}
+-
+-/**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+ */
+@@ -1518,7 +1387,7 @@ struct drm_display_mode *cdv_intel_crtc_
+ }
+
+ const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
+- .dpms = cdv_intel_crtc_dpms,
++ .dpms = gma_crtc_dpms,
+ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = cdv_intel_crtc_mode_set,
+ .mode_set_base = gma_pipe_set_base,
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -210,10 +210,8 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
+ */
+
+- /* FIXME: Uncomment this when we move cdv to generic dpms
+ if (IS_CDV(dev))
+ cdv_intel_disable_self_refresh(dev);
+- */
+
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+@@ -322,10 +320,8 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ break;
+ }
+
+- /* FIXME: Uncomment this when we move cdv to generic dpms
+ if (IS_CDV(dev))
+ cdv_intel_update_watermark(dev, crtc);
+- */
+
+ /* Set FIFO watermarks */
+ REG_WRITE(DSPARB, 0x3F3E);
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -85,4 +85,9 @@ extern bool gma_pll_is_valid(struct drm_
+ extern bool gma_find_best_pll(const struct gma_limit_t *limit,
+ struct drm_crtc *crtc, int target, int refclk,
+ struct gma_clock_t *best_clock);
++
++/* Cedarview specific functions */
++extern void cdv_intel_disable_self_refresh(struct drm_device *dev);
++extern void cdv_intel_update_watermark(struct drm_device *dev,
++ struct drm_crtc *crtc);
+ #endif
--- /dev/null
+From 329fccc438bcafae6dddc5ab705f9567a4bf7618 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 18:23:29 +0200
+Subject: drm/gma500/cdv: Convert to generic gamma funcs
+
+There is a slight difference in how we pick the palette register in the
+generic function but we should be ok as long as psb_intel_crtc->pipe and
+the register map is sane.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit a1f4efe4416dbd8d58486e60752f3a8145aa84c9)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 70 -----------------------------
+ 1 file changed, 1 insertion(+), 69 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -593,58 +593,6 @@ void cdv_intel_update_watermark(struct d
+ }
+ }
+
+-/** Loads the palette/gamma unit for the CRTC with the prepared values */
+-static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int palreg = PALETTE_A;
+- int i;
+-
+- /* The clocks have to be on to load the palette. */
+- if (!crtc->enabled)
+- return;
+-
+- switch (psb_intel_crtc->pipe) {
+- case 0:
+- break;
+- case 1:
+- palreg = PALETTE_B;
+- break;
+- case 2:
+- palreg = PALETTE_C;
+- break;
+- default:
+- dev_err(dev->dev, "Illegal Pipe Number.\n");
+- return;
+- }
+-
+- if (gma_power_begin(dev, false)) {
+- for (i = 0; i < 256; i++) {
+- REG_WRITE(palreg + 4 * i,
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]));
+- }
+- gma_power_end(dev);
+- } else {
+- for (i = 0; i < 256; i++) {
+- dev_priv->regs.pipe[0].palette[i] =
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]);
+- }
+-
+- }
+-}
+-
+ /**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+@@ -1213,22 +1161,6 @@ static int cdv_intel_crtc_cursor_move(st
+ return 0;
+ }
+
+-static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
+- u16 *green, u16 *blue, uint32_t start, uint32_t size)
+-{
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int i;
+- int end = (start + size > 256) ? 256 : start + size;
+-
+- for (i = start; i < end; i++) {
+- psb_intel_crtc->lut_r[i] = red[i] >> 8;
+- psb_intel_crtc->lut_g[i] = green[i] >> 8;
+- psb_intel_crtc->lut_b[i] = blue[i] >> 8;
+- }
+-
+- cdv_intel_crtc_load_lut(crtc);
+-}
+-
+ static int cdv_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret = 0;
+@@ -1401,7 +1333,7 @@ const struct drm_crtc_funcs cdv_intel_cr
+ .restore = cdv_intel_crtc_restore,
+ .cursor_set = cdv_intel_crtc_cursor_set,
+ .cursor_move = cdv_intel_crtc_cursor_move,
+- .gamma_set = cdv_intel_crtc_gamma_set,
++ .gamma_set = gma_crtc_gamma_set,
+ .set_config = cdv_crtc_set_config,
+ .destroy = gma_crtc_destroy,
+ };
--- /dev/null
+From c32a0929afce35459829254852f297917996c2a9 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 18:37:03 +0200
+Subject: drm/gma500/psb: Convert to gma_pipe_set_base()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 00b1fe7445d8a3cd81ba564fba5d15dcbe26f23b)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 73 -----------------------------
+ 1 file changed, 1 insertion(+), 72 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -82,77 +82,6 @@ static void psb_intel_clock(int refclk,
+ clock->dot = clock->vco / clock->p;
+ }
+
+-static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
+- int x, int y, struct drm_framebuffer *old_fb)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+- int pipe = psb_intel_crtc->pipe;
+- const struct psb_offset *map = &dev_priv->regmap[pipe];
+- unsigned long start, offset;
+- u32 dspcntr;
+- int ret = 0;
+-
+- if (!gma_power_begin(dev, true))
+- return 0;
+-
+- /* no fb bound */
+- if (!crtc->fb) {
+- dev_dbg(dev->dev, "No FB bound\n");
+- goto psb_intel_pipe_cleaner;
+- }
+-
+- /* We are displaying this buffer, make sure it is actually loaded
+- into the GTT */
+- ret = psb_gtt_pin(psbfb->gtt);
+- if (ret < 0)
+- goto psb_intel_pipe_set_base_exit;
+- start = psbfb->gtt->offset;
+-
+- offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
+-
+- REG_WRITE(map->stride, crtc->fb->pitches[0]);
+-
+- dspcntr = REG_READ(map->cntr);
+- dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+-
+- switch (crtc->fb->bits_per_pixel) {
+- case 8:
+- dspcntr |= DISPPLANE_8BPP;
+- break;
+- case 16:
+- if (crtc->fb->depth == 15)
+- dspcntr |= DISPPLANE_15_16BPP;
+- else
+- dspcntr |= DISPPLANE_16BPP;
+- break;
+- case 24:
+- case 32:
+- dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+- break;
+- default:
+- dev_err(dev->dev, "Unknown color depth\n");
+- ret = -EINVAL;
+- psb_gtt_unpin(psbfb->gtt);
+- goto psb_intel_pipe_set_base_exit;
+- }
+- REG_WRITE(map->cntr, dspcntr);
+-
+- REG_WRITE(map->base, start + offset);
+- REG_READ(map->base);
+-
+-psb_intel_pipe_cleaner:
+- /* If there was a previous display we can now unpin it */
+- if (old_fb)
+- psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
+-
+-psb_intel_pipe_set_base_exit:
+- gma_power_end(dev);
+- return ret;
+-}
+-
+ /**
+ * Sets the power management mode of the pipe and plane.
+ *
+@@ -990,7 +919,7 @@ const struct drm_crtc_helper_funcs psb_i
+ .dpms = psb_intel_crtc_dpms,
+ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = psb_intel_crtc_mode_set,
+- .mode_set_base = psb_intel_pipe_set_base,
++ .mode_set_base = gma_pipe_set_base,
+ .prepare = gma_crtc_prepare,
+ .commit = gma_crtc_commit,
+ .disable = gma_crtc_disable,
--- /dev/null
+From ceb0d7061d50dcb7ed0d06345f9d9d148a7af5c8 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 18:39:58 +0200
+Subject: drm/gma500: Convert to generic gamma funcs
+
+This takes care of the remaining chips using the old generic code.
+We don't check if the pipe number is valid but the old code peeked in
+the register map before checking anyways so just ignore it.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 6443ea1aca56f011432b6ea66ec4cc21a813bb0d)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 2
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 2
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 2
+ drivers/gpu/drm/gma500/psb_drv.c | 2
+ drivers/gpu/drm/gma500/psb_intel_display.c | 70 ---------------------------
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 1
+ 6 files changed, 6 insertions(+), 73 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -436,7 +436,7 @@ static void mdfld_crtc_dpms(struct drm_c
+ }
+ }
+
+- psb_intel_crtc_load_lut(crtc);
++ gma_crtc_load_lut(crtc);
+
+ /* Give the overlay scaler a chance to enable
+ if it's on this pipe */
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -212,7 +212,7 @@ static void oaktrail_crtc_dpms(struct dr
+ REG_WRITE(map->base, REG_READ(map->base));
+ }
+
+- psb_intel_crtc_load_lut(crtc);
++ gma_crtc_load_lut(crtc);
+
+ /* Give the overlay scaler a chance to enable
+ if it's on this pipe */
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -464,7 +464,7 @@ void oaktrail_crtc_hdmi_dpms(struct drm_
+ REG_READ(DSPBSURF);
+ }
+
+- psb_intel_crtc_load_lut(crtc);
++ gma_crtc_load_lut(crtc);
+ }
+
+ /* DSPARB */
+--- a/drivers/gpu/drm/gma500/psb_drv.c
++++ b/drivers/gpu/drm/gma500/psb_drv.c
+@@ -459,7 +459,7 @@ static int psb_gamma_ioctl(struct drm_de
+ for (i = 0; i < 256; i++)
+ psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
+
+- psb_intel_crtc_load_lut(crtc);
++ gma_crtc_load_lut(crtc);
+
+ return 0;
+ }
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -135,7 +135,7 @@ static void psb_intel_crtc_dpms(struct d
+ REG_WRITE(map->base, REG_READ(map->base));
+ }
+
+- psb_intel_crtc_load_lut(crtc);
++ gma_crtc_load_lut(crtc);
+
+ /* Give the overlay scaler a chance to enable
+ * if it's on this pipe */
+@@ -431,54 +431,6 @@ static int psb_intel_crtc_mode_set(struc
+ return 0;
+ }
+
+-/** Loads the palette/gamma unit for the CRTC with the prepared values */
+-void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
+- int palreg = map->palette;
+- int i;
+-
+- /* The clocks have to be on to load the palette. */
+- if (!crtc->enabled)
+- return;
+-
+- switch (psb_intel_crtc->pipe) {
+- case 0:
+- case 1:
+- break;
+- default:
+- dev_err(dev->dev, "Illegal Pipe Number.\n");
+- return;
+- }
+-
+- if (gma_power_begin(dev, false)) {
+- for (i = 0; i < 256; i++) {
+- REG_WRITE(palreg + 4 * i,
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]));
+- }
+- gma_power_end(dev);
+- } else {
+- for (i = 0; i < 256; i++) {
+- dev_priv->regs.pipe[0].palette[i] =
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]);
+- }
+-
+- }
+-}
+-
+ /**
+ * Save HW states of giving crtc
+ */
+@@ -737,24 +689,6 @@ static int psb_intel_crtc_cursor_move(st
+ return 0;
+ }
+
+-static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
+- u16 *green, u16 *blue, uint32_t type, uint32_t size)
+-{
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int i;
+-
+- if (size != 256)
+- return;
+-
+- for (i = 0; i < 256; i++) {
+- psb_intel_crtc->lut_r[i] = red[i] >> 8;
+- psb_intel_crtc->lut_g[i] = green[i] >> 8;
+- psb_intel_crtc->lut_b[i] = blue[i] >> 8;
+- }
+-
+- psb_intel_crtc_load_lut(crtc);
+-}
+-
+ static int psb_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret;
+@@ -930,7 +864,7 @@ const struct drm_crtc_funcs psb_intel_cr
+ .restore = psb_intel_crtc_restore,
+ .cursor_set = psb_intel_crtc_cursor_set,
+ .cursor_move = psb_intel_crtc_cursor_move,
+- .gamma_set = psb_intel_crtc_gamma_set,
++ .gamma_set = gma_crtc_gamma_set,
+ .set_config = psb_crtc_set_config,
+ .destroy = psb_intel_crtc_destroy,
+ };
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -226,7 +226,6 @@ extern void oaktrail_dsi_init(struct drm
+ extern void mid_dsi_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev, int dsi_num);
+
+-extern void psb_intel_crtc_load_lut(struct drm_crtc *crtc);
+ extern void psb_intel_encoder_prepare(struct drm_encoder *encoder);
+ extern void psb_intel_encoder_commit(struct drm_encoder *encoder);
+ extern void psb_intel_encoder_destroy(struct drm_encoder *encoder);
--- /dev/null
+From fcf7307e2a8b0bec39a75b341cfc60cc1e4577dc Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 18:44:25 +0200
+Subject: drm/gma500/psb: Convert to gma_crtc_dpms()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 42568dd5d3b5bff18d9dbc6f2f2814ed28753ada)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 104 -----------------------------
+ 1 file changed, 1 insertion(+), 103 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -82,108 +82,6 @@ static void psb_intel_clock(int refclk,
+ clock->dot = clock->vco / clock->p;
+ }
+
+-/**
+- * Sets the power management mode of the pipe and plane.
+- *
+- * This code should probably grow support for turning the cursor off and back
+- * on appropriately at the same time as we're turning the pipe off/on.
+- */
+-static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- const struct psb_offset *map = &dev_priv->regmap[pipe];
+- u32 temp;
+-
+- /* XXX: When our outputs are all unaware of DPMS modes other than off
+- * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
+- */
+- switch (mode) {
+- case DRM_MODE_DPMS_ON:
+- case DRM_MODE_DPMS_STANDBY:
+- case DRM_MODE_DPMS_SUSPEND:
+- /* Enable the DPLL */
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) == 0) {
+- REG_WRITE(map->dpll, temp);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- }
+-
+- /* Enable the pipe */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) == 0)
+- REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
+-
+- /* Enable the plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
+- REG_WRITE(map->cntr,
+- temp | DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- }
+-
+- gma_crtc_load_lut(crtc);
+-
+- /* Give the overlay scaler a chance to enable
+- * if it's on this pipe */
+- /* psb_intel_crtc_dpms_video(crtc, true); TODO */
+- break;
+- case DRM_MODE_DPMS_OFF:
+- /* Give the overlay scaler a chance to disable
+- * if it's on this pipe */
+- /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
+-
+- /* Disable the VGA plane that we never use */
+- REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+-
+- /* Disable display plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
+- REG_WRITE(map->cntr,
+- temp & ~DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- REG_READ(map->base);
+- }
+-
+- /* Next, disable display pipes */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) != 0) {
+- REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
+- REG_READ(map->conf);
+- }
+-
+- /* Wait for vblank for the disable to take effect. */
+- gma_wait_for_vblank(dev);
+-
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) != 0) {
+- REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- }
+-
+- /* Wait for the clocks to turn off. */
+- udelay(150);
+- break;
+- }
+-
+- /*Set FIFO Watermarks*/
+- REG_WRITE(DSPARB, 0x3F3E);
+-}
+-
+ void psb_intel_encoder_prepare(struct drm_encoder *encoder)
+ {
+ struct drm_encoder_helper_funcs *encoder_funcs =
+@@ -850,7 +748,7 @@ static void psb_intel_crtc_destroy(struc
+ }
+
+ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
+- .dpms = psb_intel_crtc_dpms,
++ .dpms = gma_crtc_dpms,
+ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = psb_intel_crtc_mode_set,
+ .mode_set_base = gma_pipe_set_base,
--- /dev/null
+From 7cdfa3c8fe839e54d1367589f26f4ae40741844e Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 21:52:19 +0200
+Subject: drm/gma500/oak: Use identical generic crtc funcs
+
+Use the generic gma functions instead of the oaktrail functions where
+they are identical.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit fe5802957f2856b20a408b8933472a27d00e5f77)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 25 +++----------------------
+ 1 file changed, 3 insertions(+), 22 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -494,13 +494,6 @@ oaktrail_crtc_mode_set_exit:
+ return 0;
+ }
+
+-static bool oaktrail_crtc_mode_fixup(struct drm_crtc *crtc,
+- const struct drm_display_mode *mode,
+- struct drm_display_mode *adjusted_mode)
+-{
+- return true;
+-}
+-
+ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
+ int x, int y, struct drm_framebuffer *old_fb)
+ {
+@@ -563,24 +556,12 @@ pipe_set_base_exit:
+ return ret;
+ }
+
+-static void oaktrail_crtc_prepare(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-}
+-
+-static void oaktrail_crtc_commit(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+-}
+-
+ const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
+ .dpms = oaktrail_crtc_dpms,
+- .mode_fixup = oaktrail_crtc_mode_fixup,
++ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = oaktrail_crtc_mode_set,
+ .mode_set_base = oaktrail_pipe_set_base,
+- .prepare = oaktrail_crtc_prepare,
+- .commit = oaktrail_crtc_commit,
++ .prepare = gma_crtc_prepare,
++ .commit = gma_crtc_commit,
+ };
+
--- /dev/null
+From 5ab56d0a2278d74835f3220d49c1a2fd2df12149 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 22:04:20 +0200
+Subject: drm/gma500/mdfld: Use identical generic crtc funcs
+
+Use the generic gma functions instead of the medfield functions where
+they are identical.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit d903b610d3a319933caf6ca52c76933b11434ef6)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 25 +++----------------------
+ 1 file changed, 3 insertions(+), 22 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -104,25 +104,6 @@ void mdfldWaitForPipeEnable(struct drm_d
+ }
+ }
+
+-static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+-}
+-
+-static void psb_intel_crtc_commit(struct drm_crtc *crtc)
+-{
+- struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+-}
+-
+-static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
+- const struct drm_display_mode *mode,
+- struct drm_display_mode *adjusted_mode)
+-{
+- return true;
+-}
+-
+ /**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+@@ -1045,10 +1026,10 @@ mrst_crtc_mode_set_exit:
+
+ const struct drm_crtc_helper_funcs mdfld_helper_funcs = {
+ .dpms = mdfld_crtc_dpms,
+- .mode_fixup = psb_intel_crtc_mode_fixup,
++ .mode_fixup = gma_crtc_mode_fixup,
+ .mode_set = mdfld_crtc_mode_set,
+ .mode_set_base = mdfld__intel_pipe_set_base,
+- .prepare = psb_intel_crtc_prepare,
+- .commit = psb_intel_crtc_commit,
++ .prepare = gma_crtc_prepare,
++ .commit = gma_crtc_commit,
+ };
+
--- /dev/null
+From aacea152acdec18af2e058c29ac2314e667123f9 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 23:24:22 +0200
+Subject: drm/gma500/psb: Convert to generic crtc->destroy
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit b1255b884914920f4086448ec4930e814e97afde)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 23 +----------------------
+ 1 file changed, 1 insertion(+), 22 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -726,27 +726,6 @@ struct drm_display_mode *psb_intel_crtc_
+ return mode;
+ }
+
+-static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
+-{
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct gtt_range *gt;
+-
+- /* Unpin the old GEM object */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
+- psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- psb_intel_crtc->cursor_obj = NULL;
+- }
+-
+- if (psb_intel_crtc->cursor_gt != NULL)
+- psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt);
+- kfree(psb_intel_crtc->crtc_state);
+- drm_crtc_cleanup(crtc);
+- kfree(psb_intel_crtc);
+-}
+-
+ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
+ .dpms = gma_crtc_dpms,
+ .mode_fixup = gma_crtc_mode_fixup,
+@@ -764,7 +743,7 @@ const struct drm_crtc_funcs psb_intel_cr
+ .cursor_move = psb_intel_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
+ .set_config = psb_crtc_set_config,
+- .destroy = psb_intel_crtc_destroy,
++ .destroy = gma_crtc_destroy,
+ };
+
+ const struct gma_clock_funcs psb_clock_funcs = {
--- /dev/null
+From 14fe362348e8efcdff8bfeaffae1e37cffe56d95 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 23:43:01 +0200
+Subject: drm/gma500: Add generic cursor functions
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 38945be630a5848ffc75f2f9027cbb211dec3982)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/gma_display.c | 151 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 5 +
+ 2 files changed, 156 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -327,6 +327,157 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ REG_WRITE(DSPARB, 0x3F3E);
+ }
+
++int gma_crtc_cursor_set(struct drm_crtc *crtc,
++ struct drm_file *file_priv,
++ uint32_t handle,
++ uint32_t width, uint32_t height)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ int pipe = psb_intel_crtc->pipe;
++ uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
++ uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
++ uint32_t temp;
++ size_t addr = 0;
++ struct gtt_range *gt;
++ struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
++ struct drm_gem_object *obj;
++ void *tmp_dst, *tmp_src;
++ int ret = 0, i, cursor_pages;
++
++ /* If we didn't get a handle then turn the cursor off */
++ if (!handle) {
++ temp = CURSOR_MODE_DISABLE;
++
++ if (gma_power_begin(dev, false)) {
++ REG_WRITE(control, temp);
++ REG_WRITE(base, 0);
++ gma_power_end(dev);
++ }
++
++ /* Unpin the old GEM object */
++ if (psb_intel_crtc->cursor_obj) {
++ gt = container_of(psb_intel_crtc->cursor_obj,
++ struct gtt_range, gem);
++ psb_gtt_unpin(gt);
++ drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
++ psb_intel_crtc->cursor_obj = NULL;
++ }
++
++ return 0;
++ }
++
++ /* Currently we only support 64x64 cursors */
++ if (width != 64 || height != 64) {
++ dev_dbg(dev->dev, "We currently only support 64x64 cursors\n");
++ return -EINVAL;
++ }
++
++ obj = drm_gem_object_lookup(dev, file_priv, handle);
++ if (!obj)
++ return -ENOENT;
++
++ if (obj->size < width * height * 4) {
++ dev_dbg(dev->dev, "Buffer is too small\n");
++ ret = -ENOMEM;
++ goto unref_cursor;
++ }
++
++ gt = container_of(obj, struct gtt_range, gem);
++
++ /* Pin the memory into the GTT */
++ ret = psb_gtt_pin(gt);
++ if (ret) {
++ dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
++ goto unref_cursor;
++ }
++
++ if (dev_priv->ops->cursor_needs_phys) {
++ if (cursor_gt == NULL) {
++ dev_err(dev->dev, "No hardware cursor mem available");
++ ret = -ENOMEM;
++ goto unref_cursor;
++ }
++
++ /* Prevent overflow */
++ if (gt->npage > 4)
++ cursor_pages = 4;
++ else
++ cursor_pages = gt->npage;
++
++ /* Copy the cursor to cursor mem */
++ tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
++ for (i = 0; i < cursor_pages; i++) {
++ tmp_src = kmap(gt->pages[i]);
++ memcpy(tmp_dst, tmp_src, PAGE_SIZE);
++ kunmap(gt->pages[i]);
++ tmp_dst += PAGE_SIZE;
++ }
++
++ addr = psb_intel_crtc->cursor_addr;
++ } else {
++ addr = gt->offset;
++ psb_intel_crtc->cursor_addr = addr;
++ }
++
++ temp = 0;
++ /* set the pipe for the cursor */
++ temp |= (pipe << 28);
++ temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
++
++ if (gma_power_begin(dev, false)) {
++ REG_WRITE(control, temp);
++ REG_WRITE(base, addr);
++ gma_power_end(dev);
++ }
++
++ /* unpin the old bo */
++ if (psb_intel_crtc->cursor_obj) {
++ gt = container_of(psb_intel_crtc->cursor_obj,
++ struct gtt_range, gem);
++ psb_gtt_unpin(gt);
++ drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
++ }
++
++ psb_intel_crtc->cursor_obj = obj;
++ return ret;
++
++unref_cursor:
++ drm_gem_object_unreference(obj);
++ return ret;
++}
++
++int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
++{
++ struct drm_device *dev = crtc->dev;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ int pipe = psb_intel_crtc->pipe;
++ uint32_t temp = 0;
++ uint32_t addr;
++
++ if (x < 0) {
++ temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
++ x = -x;
++ }
++ if (y < 0) {
++ temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
++ y = -y;
++ }
++
++ temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
++ temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
++
++ addr = psb_intel_crtc->cursor_addr;
++
++ if (gma_power_begin(dev, false)) {
++ REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
++ REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
++ gma_power_end(dev);
++ }
++ return 0;
++}
++
+ bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -64,6 +64,11 @@ extern bool gma_pipe_has_type(struct drm
+ extern void gma_wait_for_vblank(struct drm_device *dev);
+ extern int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
+ struct drm_framebuffer *old_fb);
++extern int gma_crtc_cursor_set(struct drm_crtc *crtc,
++ struct drm_file *file_priv,
++ uint32_t handle,
++ uint32_t width, uint32_t height);
++extern int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y);
+ extern void gma_crtc_load_lut(struct drm_crtc *crtc);
+ extern void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, u32 start, u32 size);
--- /dev/null
+From 2cf163994682c62ca231b0c6b7c493a5e1514420 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 23:46:11 +0200
+Subject: drm/gma500/cdv: Convert to generic cursor funcs
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 04416625f9264d6a2322cb919fa4b5b2bf72b94f)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 130 -----------------------------
+ 1 file changed, 2 insertions(+), 128 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -1035,132 +1035,6 @@ static void cdv_intel_crtc_restore(struc
+ REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
+ }
+
+-static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
+- struct drm_file *file_priv,
+- uint32_t handle,
+- uint32_t width, uint32_t height)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
+- uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
+- uint32_t temp;
+- size_t addr = 0;
+- struct gtt_range *gt;
+- struct drm_gem_object *obj;
+- int ret = 0;
+-
+- /* if we want to turn of the cursor ignore width and height */
+- if (!handle) {
+- /* turn off the cursor */
+- temp = CURSOR_MODE_DISABLE;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE(control, temp);
+- REG_WRITE(base, 0);
+- gma_power_end(dev);
+- }
+-
+- /* unpin the old GEM object */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
+- psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- psb_intel_crtc->cursor_obj = NULL;
+- }
+-
+- return 0;
+- }
+-
+- /* Currently we only support 64x64 cursors */
+- if (width != 64 || height != 64) {
+- dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
+- return -EINVAL;
+- }
+-
+- obj = drm_gem_object_lookup(dev, file_priv, handle);
+- if (!obj)
+- return -ENOENT;
+-
+- if (obj->size < width * height * 4) {
+- dev_dbg(dev->dev, "buffer is to small\n");
+- ret = -ENOMEM;
+- goto unref_cursor;
+- }
+-
+- gt = container_of(obj, struct gtt_range, gem);
+-
+- /* Pin the memory into the GTT */
+- ret = psb_gtt_pin(gt);
+- if (ret) {
+- dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
+- goto unref_cursor;
+- }
+-
+- addr = gt->offset; /* Or resource.start ??? */
+-
+- psb_intel_crtc->cursor_addr = addr;
+-
+- temp = 0;
+- /* set the pipe for the cursor */
+- temp |= (pipe << 28);
+- temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE(control, temp);
+- REG_WRITE(base, addr);
+- gma_power_end(dev);
+- }
+-
+- /* unpin the old GEM object */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
+- psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- }
+-
+- psb_intel_crtc->cursor_obj = obj;
+- return ret;
+-
+-unref_cursor:
+- drm_gem_object_unreference(obj);
+- return ret;
+-}
+-
+-static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- uint32_t temp = 0;
+- uint32_t adder;
+-
+-
+- if (x < 0) {
+- temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
+- x = -x;
+- }
+- if (y < 0) {
+- temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
+- y = -y;
+- }
+-
+- temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
+- temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
+-
+- adder = psb_intel_crtc->cursor_addr;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
+- REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
+- gma_power_end(dev);
+- }
+- return 0;
+-}
+-
+ static int cdv_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret = 0;
+@@ -1331,8 +1205,8 @@ const struct drm_crtc_helper_funcs cdv_i
+ const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
+ .save = cdv_intel_crtc_save,
+ .restore = cdv_intel_crtc_restore,
+- .cursor_set = cdv_intel_crtc_cursor_set,
+- .cursor_move = cdv_intel_crtc_cursor_move,
++ .cursor_set = gma_crtc_cursor_set,
++ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
+ .set_config = cdv_crtc_set_config,
+ .destroy = gma_crtc_destroy,
--- /dev/null
+From bc3bae59d7c246c37b7b188655eaf53e63aa2ed3 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 10 Jul 2013 23:48:13 +0200
+Subject: drm/gma500/psb: Convert to generic cursor funcs
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 561573bf69f71c67e6d807efef91c7cf11637817)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 157 -----------------------------
+ 1 file changed, 2 insertions(+), 155 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -434,159 +434,6 @@ static void psb_intel_crtc_restore(struc
+ REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
+ }
+
+-static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
+- struct drm_file *file_priv,
+- uint32_t handle,
+- uint32_t width, uint32_t height)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
+- uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
+- uint32_t temp;
+- size_t addr = 0;
+- struct gtt_range *gt;
+- struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
+- struct drm_gem_object *obj;
+- void *tmp_dst, *tmp_src;
+- int ret = 0, i, cursor_pages;
+-
+- /* if we want to turn of the cursor ignore width and height */
+- if (!handle) {
+- /* turn off the cursor */
+- temp = CURSOR_MODE_DISABLE;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE(control, temp);
+- REG_WRITE(base, 0);
+- gma_power_end(dev);
+- }
+-
+- /* Unpin the old GEM object */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
+- psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- psb_intel_crtc->cursor_obj = NULL;
+- }
+-
+- return 0;
+- }
+-
+- /* Currently we only support 64x64 cursors */
+- if (width != 64 || height != 64) {
+- dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
+- return -EINVAL;
+- }
+-
+- obj = drm_gem_object_lookup(dev, file_priv, handle);
+- if (!obj)
+- return -ENOENT;
+-
+- if (obj->size < width * height * 4) {
+- dev_dbg(dev->dev, "buffer is to small\n");
+- ret = -ENOMEM;
+- goto unref_cursor;
+- }
+-
+- gt = container_of(obj, struct gtt_range, gem);
+-
+- /* Pin the memory into the GTT */
+- ret = psb_gtt_pin(gt);
+- if (ret) {
+- dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
+- goto unref_cursor;
+- }
+-
+- if (dev_priv->ops->cursor_needs_phys) {
+- if (cursor_gt == NULL) {
+- dev_err(dev->dev, "No hardware cursor mem available");
+- ret = -ENOMEM;
+- goto unref_cursor;
+- }
+-
+- /* Prevent overflow */
+- if (gt->npage > 4)
+- cursor_pages = 4;
+- else
+- cursor_pages = gt->npage;
+-
+- /* Copy the cursor to cursor mem */
+- tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
+- for (i = 0; i < cursor_pages; i++) {
+- tmp_src = kmap(gt->pages[i]);
+- memcpy(tmp_dst, tmp_src, PAGE_SIZE);
+- kunmap(gt->pages[i]);
+- tmp_dst += PAGE_SIZE;
+- }
+-
+- addr = psb_intel_crtc->cursor_addr;
+- } else {
+- addr = gt->offset; /* Or resource.start ??? */
+- psb_intel_crtc->cursor_addr = addr;
+- }
+-
+- temp = 0;
+- /* set the pipe for the cursor */
+- temp |= (pipe << 28);
+- temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE(control, temp);
+- REG_WRITE(base, addr);
+- gma_power_end(dev);
+- }
+-
+- /* unpin the old bo */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
+- psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- }
+-
+- psb_intel_crtc->cursor_obj = obj;
+- return ret;
+-
+-unref_cursor:
+- drm_gem_object_unreference(obj);
+- return ret;
+-}
+-
+-static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
+- uint32_t temp = 0;
+- uint32_t addr;
+-
+-
+- if (x < 0) {
+- temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
+- x = -x;
+- }
+- if (y < 0) {
+- temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
+- y = -y;
+- }
+-
+- temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
+- temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
+-
+- addr = psb_intel_crtc->cursor_addr;
+-
+- if (gma_power_begin(dev, false)) {
+- REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
+- REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
+- gma_power_end(dev);
+- }
+- return 0;
+-}
+-
+ static int psb_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret;
+@@ -739,8 +586,8 @@ const struct drm_crtc_helper_funcs psb_i
+ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
+ .save = psb_intel_crtc_save,
+ .restore = psb_intel_crtc_restore,
+- .cursor_set = psb_intel_crtc_cursor_set,
+- .cursor_move = psb_intel_crtc_cursor_move,
++ .cursor_set = gma_crtc_cursor_set,
++ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
+ .set_config = psb_crtc_set_config,
+ .destroy = gma_crtc_destroy,
--- /dev/null
+From 5364653ef2e45b444029fe37e390b3f4401e0377 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 11 Jul 2013 00:54:45 +0200
+Subject: drm/gma500: Add generic encoder functions
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 593458470191e9226c2530c0e10f8e35604063dc)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/gma_display.c | 41 +++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 4 +++
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 10 ++++++++
+ 3 files changed, 55 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -519,6 +519,47 @@ void gma_crtc_destroy(struct drm_crtc *c
+ kfree(psb_intel_crtc);
+ }
+
++void gma_encoder_prepare(struct drm_encoder *encoder)
++{
++ struct drm_encoder_helper_funcs *encoder_funcs =
++ encoder->helper_private;
++ /* lvds has its own version of prepare see psb_intel_lvds_prepare */
++ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
++}
++
++void gma_encoder_commit(struct drm_encoder *encoder)
++{
++ struct drm_encoder_helper_funcs *encoder_funcs =
++ encoder->helper_private;
++ /* lvds has its own version of commit see psb_intel_lvds_commit */
++ encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
++}
++
++void gma_encoder_destroy(struct drm_encoder *encoder)
++{
++ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++
++ drm_encoder_cleanup(encoder);
++ kfree(intel_encoder);
++}
++
++/* Currently there is only a 1:1 mapping of encoders and connectors */
++struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
++{
++ struct psb_intel_encoder *psb_intel_encoder =
++ psb_intel_attached_encoder(connector);
++
++ return &psb_intel_encoder->base;
++}
++
++void gma_connector_attach_encoder(struct psb_intel_connector *connector,
++ struct psb_intel_encoder *encoder)
++{
++ connector->encoder = encoder;
++ drm_mode_connector_attach_encoder(&connector->base,
++ &encoder->base);
++}
++
+ #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
+
+ bool gma_pll_is_valid(struct drm_crtc *crtc,
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -81,6 +81,10 @@ extern void gma_crtc_commit(struct drm_c
+ extern void gma_crtc_disable(struct drm_crtc *crtc);
+ extern void gma_crtc_destroy(struct drm_crtc *crtc);
+
++extern void gma_encoder_prepare(struct drm_encoder *encoder);
++extern void gma_encoder_commit(struct drm_encoder *encoder);
++extern void gma_encoder_destroy(struct drm_encoder *encoder);
++
+ /* Common clock related functions */
+ extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
+ extern void gma_clock(int refclk, struct gma_clock_t *clock);
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -230,10 +230,20 @@ extern void psb_intel_encoder_prepare(st
+ extern void psb_intel_encoder_commit(struct drm_encoder *encoder);
+ extern void psb_intel_encoder_destroy(struct drm_encoder *encoder);
+
++extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector);
++extern void gma_connector_attach_encoder(struct psb_intel_connector *connector,
++ struct psb_intel_encoder *encoder);
++
+ static inline struct psb_intel_encoder *psb_intel_attached_encoder(
+ struct drm_connector *connector)
+ {
+ return to_psb_intel_connector(connector)->encoder;
++}
++
++static inline struct psb_intel_encoder *gma_attached_encoder(
++ struct drm_connector *connector)
++{
++ return to_psb_intel_connector(connector)->encoder;
+ }
+
+ extern void psb_intel_connector_attach_encoder(
--- /dev/null
+From 61564510cf3bd2e188071a3ec2fa32c0c09d6208 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 11 Jul 2013 01:02:01 +0200
+Subject: drm/gma500: Convert to generic encoder funcs
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit c9d4959000c0b11c4265af820434b868c4066e0e)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_crt.c | 13 +++----
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 4 +-
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 17 +++++----
+ drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 19 +++++-----
+ drivers/gpu/drm/gma500/cdv_intel_lvds.c | 9 ++---
+ drivers/gpu/drm/gma500/framebuffer.c | 2 -
+ drivers/gpu/drm/gma500/gma_display.c | 4 +-
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 2 -
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 2 -
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 9 ++---
+ drivers/gpu/drm/gma500/oaktrail_lvds.c | 3 -
+ drivers/gpu/drm/gma500/psb_drv.c | 2 -
+ drivers/gpu/drm/gma500/psb_intel_display.c | 47 +--------------------------
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 17 ---------
+ drivers/gpu/drm/gma500/psb_intel_lvds.c | 15 ++++----
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 17 ++++-----
+ 16 files changed, 58 insertions(+), 124 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_crt.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c
+@@ -198,7 +198,7 @@ static enum drm_connector_status cdv_int
+ static void cdv_intel_crt_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus);
+ drm_sysfs_connector_remove(connector);
+@@ -209,7 +209,7 @@ static void cdv_intel_crt_destroy(struct
+ static int cdv_intel_crt_get_modes(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ return psb_intel_ddc_get_modes(connector, &psb_intel_encoder->ddc_bus->adapter);
+ }
+
+@@ -227,8 +227,8 @@ static int cdv_intel_crt_set_property(st
+ static const struct drm_encoder_helper_funcs cdv_intel_crt_helper_funcs = {
+ .dpms = cdv_intel_crt_dpms,
+ .mode_fixup = cdv_intel_crt_mode_fixup,
+- .prepare = psb_intel_encoder_prepare,
+- .commit = psb_intel_encoder_commit,
++ .prepare = gma_encoder_prepare,
++ .commit = gma_encoder_commit,
+ .mode_set = cdv_intel_crt_mode_set,
+ };
+
+@@ -244,7 +244,7 @@ static const struct drm_connector_helper
+ cdv_intel_crt_connector_helper_funcs = {
+ .mode_valid = cdv_intel_crt_mode_valid,
+ .get_modes = cdv_intel_crt_get_modes,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static void cdv_intel_crt_enc_destroy(struct drm_encoder *encoder)
+@@ -284,8 +284,7 @@ void cdv_intel_crt_init(struct drm_devic
+ drm_encoder_init(dev, encoder,
+ &cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+
+ /* Set up the DDC bus. */
+ i2c_reg = GPIOA;
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -499,7 +499,7 @@ static bool is_pipeb_lvds(struct drm_dev
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+@@ -634,7 +634,7 @@ static int cdv_intel_crtc_mode_set(struc
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -315,7 +315,7 @@ static int
+ cdv_intel_dp_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+ {
+- struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
++ struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
+ int max_lanes = cdv_intel_dp_max_lane_count(encoder);
+@@ -1532,7 +1532,7 @@ cdv_dp_detect(struct psb_intel_encoder *
+ static enum drm_connector_status
+ cdv_intel_dp_detect(struct drm_connector *connector, bool force)
+ {
+- struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
++ struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ enum drm_connector_status status;
+ struct edid *edid = NULL;
+@@ -1566,7 +1566,8 @@ cdv_intel_dp_detect(struct drm_connector
+
+ static int cdv_intel_dp_get_modes(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
++ struct psb_intel_encoder *intel_encoder =
++ gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct edid *edid = NULL;
+ int ret = 0;
+@@ -1622,7 +1623,7 @@ static int cdv_intel_dp_get_modes(struct
+ static bool
+ cdv_intel_dp_detect_audio(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
++ struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ struct edid *edid;
+ bool has_audio = false;
+@@ -1648,7 +1649,7 @@ cdv_intel_dp_set_property(struct drm_con
+ uint64_t val)
+ {
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+- struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
++ struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+
+@@ -1702,7 +1703,7 @@ static void
+ cdv_intel_dp_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
+
+ if (is_edp(psb_intel_encoder)) {
+@@ -1742,7 +1743,7 @@ static const struct drm_connector_funcs
+ static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
+ .get_modes = cdv_intel_dp_get_modes,
+ .mode_valid = cdv_intel_dp_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
+@@ -1828,7 +1829,7 @@ cdv_intel_dp_init(struct drm_device *dev
+ drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
+ drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+
+ if (type == DRM_MODE_CONNECTOR_DisplayPort)
+ psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+--- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
+@@ -117,7 +117,7 @@ static void cdv_hdmi_save(struct drm_con
+ {
+ struct drm_device *dev = connector->dev;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
+
+ hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg);
+@@ -127,7 +127,7 @@ static void cdv_hdmi_restore(struct drm_
+ {
+ struct drm_device *dev = connector->dev;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
+
+ REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB);
+@@ -138,7 +138,7 @@ static enum drm_connector_status cdv_hdm
+ struct drm_connector *connector, bool force)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
+ struct edid *edid = NULL;
+ enum drm_connector_status status = connector_status_disconnected;
+@@ -222,7 +222,7 @@ static int cdv_hdmi_set_property(struct
+ static int cdv_hdmi_get_modes(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct edid *edid = NULL;
+ int ret = 0;
+
+@@ -257,7 +257,7 @@ static int cdv_hdmi_mode_valid(struct dr
+ static void cdv_hdmi_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ if (psb_intel_encoder->i2c_bus)
+ psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus);
+@@ -269,16 +269,16 @@ static void cdv_hdmi_destroy(struct drm_
+ static const struct drm_encoder_helper_funcs cdv_hdmi_helper_funcs = {
+ .dpms = cdv_hdmi_dpms,
+ .mode_fixup = cdv_hdmi_mode_fixup,
+- .prepare = psb_intel_encoder_prepare,
++ .prepare = gma_encoder_prepare,
+ .mode_set = cdv_hdmi_mode_set,
+- .commit = psb_intel_encoder_commit,
++ .commit = gma_encoder_commit,
+ };
+
+ static const struct drm_connector_helper_funcs
+ cdv_hdmi_connector_helper_funcs = {
+ .get_modes = cdv_hdmi_get_modes,
+ .mode_valid = cdv_hdmi_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static const struct drm_connector_funcs cdv_hdmi_connector_funcs = {
+@@ -328,8 +328,7 @@ void cdv_hdmi_init(struct drm_device *de
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
+ hdmi_priv->hdmi_reg = reg;
+ hdmi_priv->has_hdmi_sink = false;
+--- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
+@@ -408,7 +408,7 @@ static int cdv_intel_lvds_get_modes(stru
+ struct drm_device *dev = connector->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+ int ret;
+
+@@ -445,7 +445,7 @@ static int cdv_intel_lvds_get_modes(stru
+ static void cdv_intel_lvds_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ if (psb_intel_encoder->i2c_bus)
+ psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus);
+@@ -529,7 +529,7 @@ static const struct drm_connector_helper
+ cdv_intel_lvds_connector_helper_funcs = {
+ .get_modes = cdv_intel_lvds_get_modes,
+ .mode_valid = cdv_intel_lvds_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static const struct drm_connector_funcs cdv_intel_lvds_connector_funcs = {
+@@ -659,8 +659,7 @@ void cdv_intel_lvds_init(struct drm_devi
+ DRM_MODE_ENCODER_LVDS);
+
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs);
+--- a/drivers/gpu/drm/gma500/framebuffer.c
++++ b/drivers/gpu/drm/gma500/framebuffer.c
+@@ -704,7 +704,7 @@ static void psb_setup_outputs(struct drm
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct drm_encoder *encoder = &psb_intel_encoder->base;
+ int crtc_mask = 0, clone_mask = 0;
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -38,7 +38,7 @@ bool gma_pipe_has_type(struct drm_crtc *
+ list_for_each_entry(l_entry, &mode_config->connector_list, head) {
+ if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(l_entry);
++ gma_attached_encoder(l_entry);
+ if (psb_intel_encoder->type == type)
+ return true;
+ }
+@@ -547,7 +547,7 @@ void gma_encoder_destroy(struct drm_enco
+ struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ return &psb_intel_encoder->base;
+ }
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -747,7 +747,7 @@ static int mdfld_crtc_mode_set(struct dr
+ if (encoder->crtc != crtc)
+ continue;
+
+- psb_intel_encoder = psb_intel_attached_encoder(connector);
++ psb_intel_encoder = gma_attached_encoder(connector);
+
+ switch (psb_intel_encoder->type) {
+ case INTEL_OUTPUT_MIPI:
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -324,7 +324,7 @@ static int oaktrail_crtc_mode_set(struct
+ if (!connector->encoder || connector->encoder->crtc != crtc)
+ continue;
+
+- psb_intel_encoder = psb_intel_attached_encoder(connector);
++ psb_intel_encoder = gma_attached_encoder(connector);
+
+ switch (psb_intel_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -609,16 +609,16 @@ static void oaktrail_hdmi_destroy(struct
+ static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = {
+ .dpms = oaktrail_hdmi_dpms,
+ .mode_fixup = oaktrail_hdmi_mode_fixup,
+- .prepare = psb_intel_encoder_prepare,
++ .prepare = gma_encoder_prepare,
+ .mode_set = oaktrail_hdmi_mode_set,
+- .commit = psb_intel_encoder_commit,
++ .commit = gma_encoder_commit,
+ };
+
+ static const struct drm_connector_helper_funcs
+ oaktrail_hdmi_connector_helper_funcs = {
+ .get_modes = oaktrail_hdmi_get_modes,
+ .mode_valid = oaktrail_hdmi_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = {
+@@ -663,8 +663,7 @@ void oaktrail_hdmi_init(struct drm_devic
+ &oaktrail_hdmi_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+
+ psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
+ drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
+--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
++++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
+@@ -352,8 +352,7 @@ void oaktrail_lvds_init(struct drm_devic
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
+--- a/drivers/gpu/drm/gma500/psb_drv.c
++++ b/drivers/gpu/drm/gma500/psb_drv.c
+@@ -372,7 +372,7 @@ static int psb_driver_load(struct drm_de
+ /* Only add backlight support if we have LVDS output */
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+- psb_intel_encoder = psb_intel_attached_encoder(connector);
++ psb_intel_encoder = gma_attached_encoder(connector);
+
+ switch (psb_intel_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -82,30 +82,6 @@ static void psb_intel_clock(int refclk,
+ clock->dot = clock->vco / clock->p;
+ }
+
+-void psb_intel_encoder_prepare(struct drm_encoder *encoder)
+-{
+- struct drm_encoder_helper_funcs *encoder_funcs =
+- encoder->helper_private;
+- /* lvds has its own version of prepare see psb_intel_lvds_prepare */
+- encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
+-}
+-
+-void psb_intel_encoder_commit(struct drm_encoder *encoder)
+-{
+- struct drm_encoder_helper_funcs *encoder_funcs =
+- encoder->helper_private;
+- /* lvds has its own version of commit see psb_intel_lvds_commit */
+- encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+-}
+-
+-void psb_intel_encoder_destroy(struct drm_encoder *encoder)
+-{
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+-
+- drm_encoder_cleanup(encoder);
+- kfree(intel_encoder);
+-}
+-
+ /**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+@@ -152,7 +128,7 @@ static int psb_intel_crtc_mode_set(struc
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+@@ -752,29 +728,10 @@ int psb_intel_connector_clones(struct dr
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ if (type_mask & (1 << psb_intel_encoder->type))
+ index_mask |= (1 << entry);
+ entry++;
+ }
+ return index_mask;
+ }
+-
+-/* current intel driver doesn't take advantage of encoders
+- always give back the encoder for the connector
+-*/
+-struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
+-{
+- struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
+-
+- return &psb_intel_encoder->base;
+-}
+-
+-void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector,
+- struct psb_intel_encoder *encoder)
+-{
+- connector->encoder = encoder;
+- drm_mode_connector_attach_encoder(&connector->base,
+- &encoder->base);
+-}
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -226,33 +226,16 @@ extern void oaktrail_dsi_init(struct drm
+ extern void mid_dsi_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev, int dsi_num);
+
+-extern void psb_intel_encoder_prepare(struct drm_encoder *encoder);
+-extern void psb_intel_encoder_commit(struct drm_encoder *encoder);
+-extern void psb_intel_encoder_destroy(struct drm_encoder *encoder);
+-
+ extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector);
+ extern void gma_connector_attach_encoder(struct psb_intel_connector *connector,
+ struct psb_intel_encoder *encoder);
+
+-static inline struct psb_intel_encoder *psb_intel_attached_encoder(
+- struct drm_connector *connector)
+-{
+- return to_psb_intel_connector(connector)->encoder;
+-}
+-
+ static inline struct psb_intel_encoder *gma_attached_encoder(
+ struct drm_connector *connector)
+ {
+ return to_psb_intel_connector(connector)->encoder;
+ }
+
+-extern void psb_intel_connector_attach_encoder(
+- struct psb_intel_connector *connector,
+- struct psb_intel_encoder *encoder);
+-
+-extern struct drm_encoder *psb_intel_best_encoder(struct drm_connector
+- *connector);
+-
+ extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc);
+ extern int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
+--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
+@@ -268,7 +268,7 @@ static void psb_intel_lvds_save(struct d
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *)dev->dev_private;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv =
+ (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv;
+
+@@ -308,7 +308,7 @@ static void psb_intel_lvds_restore(struc
+ struct drm_device *dev = connector->dev;
+ u32 pp_status;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv =
+ (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv;
+
+@@ -350,7 +350,7 @@ int psb_intel_lvds_mode_valid(struct drm
+ {
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct drm_display_mode *fixed_mode =
+ dev_priv->mode_dev.panel_fixed_mode;
+
+@@ -526,7 +526,7 @@ static int psb_intel_lvds_get_modes(stru
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv;
+ int ret = 0;
+
+@@ -565,7 +565,7 @@ static int psb_intel_lvds_get_modes(stru
+ void psb_intel_lvds_destroy(struct drm_connector *connector)
+ {
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv;
+
+ if (lvds_priv->ddc_bus)
+@@ -656,7 +656,7 @@ const struct drm_connector_helper_funcs
+ psb_intel_lvds_connector_helper_funcs = {
+ .get_modes = psb_intel_lvds_get_modes,
+ .mode_valid = psb_intel_lvds_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ const struct drm_connector_funcs psb_intel_lvds_connector_funcs = {
+@@ -734,8 +734,7 @@ void psb_intel_lvds_init(struct drm_devi
+ &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- psb_intel_connector_attach_encoder(psb_intel_connector,
+- psb_intel_encoder);
++ gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs);
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -200,7 +200,7 @@ static struct psb_intel_sdvo *to_psb_int
+
+ static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
+ {
+- return container_of(psb_intel_attached_encoder(connector),
++ return container_of(gma_attached_encoder(connector),
+ struct psb_intel_sdvo, base);
+ }
+
+@@ -1837,7 +1837,7 @@ static void psb_intel_sdvo_save(struct d
+ {
+ struct drm_device *dev = connector->dev;
+ struct psb_intel_encoder *psb_intel_encoder =
+- psb_intel_attached_encoder(connector);
++ gma_attached_encoder(connector);
+ struct psb_intel_sdvo *sdvo =
+ to_psb_intel_sdvo(&psb_intel_encoder->base);
+
+@@ -1847,8 +1847,7 @@ static void psb_intel_sdvo_save(struct d
+ static void psb_intel_sdvo_restore(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+- struct drm_encoder *encoder =
+- &psb_intel_attached_encoder(connector)->base;
++ struct drm_encoder *encoder = &gma_attached_encoder(connector)->base;
+ struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
+
+@@ -1864,9 +1863,9 @@ static void psb_intel_sdvo_restore(struc
+ static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
+ .dpms = psb_intel_sdvo_dpms,
+ .mode_fixup = psb_intel_sdvo_mode_fixup,
+- .prepare = psb_intel_encoder_prepare,
++ .prepare = gma_encoder_prepare,
+ .mode_set = psb_intel_sdvo_mode_set,
+- .commit = psb_intel_encoder_commit,
++ .commit = gma_encoder_commit,
+ };
+
+ static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
+@@ -1882,7 +1881,7 @@ static const struct drm_connector_funcs
+ static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
+ .get_modes = psb_intel_sdvo_get_modes,
+ .mode_valid = psb_intel_sdvo_mode_valid,
+- .best_encoder = psb_intel_best_encoder,
++ .best_encoder = gma_best_encoder,
+ };
+
+ static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
+@@ -1894,7 +1893,7 @@ static void psb_intel_sdvo_enc_destroy(s
+ psb_intel_sdvo->sdvo_lvds_fixed_mode);
+
+ i2c_del_adapter(&psb_intel_sdvo->ddc);
+- psb_intel_encoder_destroy(encoder);
++ gma_encoder_destroy(encoder);
+ }
+
+ static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
+@@ -2055,7 +2054,7 @@ psb_intel_sdvo_connector_init(struct psb
+ connector->base.base.doublescan_allowed = 0;
+ connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
+
+- psb_intel_connector_attach_encoder(&connector->base, &encoder->base);
++ gma_connector_attach_encoder(&connector->base, &encoder->base);
+ drm_sysfs_connector_add(&connector->base.base);
+ }
+
--- /dev/null
+From f011afb070431eca1ff447509050ea942c4649e2 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:30:56 +0200
+Subject: drm/gma500: Add generic crtc save/restore funcs
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 2e775700a297982a3ffbfe72935982b6fb51e015)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/gma_display.c | 105 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 3 +
+ 2 files changed, 108 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -519,6 +519,111 @@ void gma_crtc_destroy(struct drm_crtc *c
+ kfree(psb_intel_crtc);
+ }
+
++/**
++ * Save HW states of given crtc
++ */
++void gma_crtc_save(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
++ const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ uint32_t palette_reg;
++ int i;
++
++ if (!crtc_state) {
++ dev_err(dev->dev, "No CRTC state found\n");
++ return;
++ }
++
++ crtc_state->saveDSPCNTR = REG_READ(map->cntr);
++ crtc_state->savePIPECONF = REG_READ(map->conf);
++ crtc_state->savePIPESRC = REG_READ(map->src);
++ crtc_state->saveFP0 = REG_READ(map->fp0);
++ crtc_state->saveFP1 = REG_READ(map->fp1);
++ crtc_state->saveDPLL = REG_READ(map->dpll);
++ crtc_state->saveHTOTAL = REG_READ(map->htotal);
++ crtc_state->saveHBLANK = REG_READ(map->hblank);
++ crtc_state->saveHSYNC = REG_READ(map->hsync);
++ crtc_state->saveVTOTAL = REG_READ(map->vtotal);
++ crtc_state->saveVBLANK = REG_READ(map->vblank);
++ crtc_state->saveVSYNC = REG_READ(map->vsync);
++ crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
++
++ /* NOTE: DSPSIZE DSPPOS only for psb */
++ crtc_state->saveDSPSIZE = REG_READ(map->size);
++ crtc_state->saveDSPPOS = REG_READ(map->pos);
++
++ crtc_state->saveDSPBASE = REG_READ(map->base);
++
++ palette_reg = map->palette;
++ for (i = 0; i < 256; ++i)
++ crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
++}
++
++/**
++ * Restore HW states of given crtc
++ */
++void gma_crtc_restore(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
++ const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ uint32_t palette_reg;
++ int i;
++
++ if (!crtc_state) {
++ dev_err(dev->dev, "No crtc state\n");
++ return;
++ }
++
++ if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
++ REG_WRITE(map->dpll,
++ crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
++ REG_READ(map->dpll);
++ udelay(150);
++ }
++
++ REG_WRITE(map->fp0, crtc_state->saveFP0);
++ REG_READ(map->fp0);
++
++ REG_WRITE(map->fp1, crtc_state->saveFP1);
++ REG_READ(map->fp1);
++
++ REG_WRITE(map->dpll, crtc_state->saveDPLL);
++ REG_READ(map->dpll);
++ udelay(150);
++
++ REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
++ REG_WRITE(map->hblank, crtc_state->saveHBLANK);
++ REG_WRITE(map->hsync, crtc_state->saveHSYNC);
++ REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
++ REG_WRITE(map->vblank, crtc_state->saveVBLANK);
++ REG_WRITE(map->vsync, crtc_state->saveVSYNC);
++ REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
++
++ REG_WRITE(map->size, crtc_state->saveDSPSIZE);
++ REG_WRITE(map->pos, crtc_state->saveDSPPOS);
++
++ REG_WRITE(map->src, crtc_state->savePIPESRC);
++ REG_WRITE(map->base, crtc_state->saveDSPBASE);
++ REG_WRITE(map->conf, crtc_state->savePIPECONF);
++
++ gma_wait_for_vblank(dev);
++
++ REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
++ REG_WRITE(map->base, crtc_state->saveDSPBASE);
++
++ gma_wait_for_vblank(dev);
++
++ palette_reg = map->palette;
++ for (i = 0; i < 256; ++i)
++ REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);
++}
++
+ void gma_encoder_prepare(struct drm_encoder *encoder)
+ {
+ struct drm_encoder_helper_funcs *encoder_funcs =
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -81,6 +81,9 @@ extern void gma_crtc_commit(struct drm_c
+ extern void gma_crtc_disable(struct drm_crtc *crtc);
+ extern void gma_crtc_destroy(struct drm_crtc *crtc);
+
++extern void gma_crtc_save(struct drm_crtc *crtc);
++extern void gma_crtc_restore(struct drm_crtc *crtc);
++
+ extern void gma_encoder_prepare(struct drm_encoder *encoder);
+ extern void gma_encoder_commit(struct drm_encoder *encoder);
+ extern void gma_encoder_destroy(struct drm_encoder *encoder);
--- /dev/null
+From a7e68e965aabd69108700bb922f2a7b70e6cadbe Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:32:18 +0200
+Subject: drm/gma500/psb: Convert to generic save/restore
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 0e5b26ab67bbc3f762444264cdc8be7db12f374c)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 109 -----------------------------
+ 1 file changed, 2 insertions(+), 107 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -305,111 +305,6 @@ static int psb_intel_crtc_mode_set(struc
+ return 0;
+ }
+
+-/**
+- * Save HW states of giving crtc
+- */
+-static void psb_intel_crtc_save(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
+- uint32_t paletteReg;
+- int i;
+-
+- if (!crtc_state) {
+- dev_err(dev->dev, "No CRTC state found\n");
+- return;
+- }
+-
+- crtc_state->saveDSPCNTR = REG_READ(map->cntr);
+- crtc_state->savePIPECONF = REG_READ(map->conf);
+- crtc_state->savePIPESRC = REG_READ(map->src);
+- crtc_state->saveFP0 = REG_READ(map->fp0);
+- crtc_state->saveFP1 = REG_READ(map->fp1);
+- crtc_state->saveDPLL = REG_READ(map->dpll);
+- crtc_state->saveHTOTAL = REG_READ(map->htotal);
+- crtc_state->saveHBLANK = REG_READ(map->hblank);
+- crtc_state->saveHSYNC = REG_READ(map->hsync);
+- crtc_state->saveVTOTAL = REG_READ(map->vtotal);
+- crtc_state->saveVBLANK = REG_READ(map->vblank);
+- crtc_state->saveVSYNC = REG_READ(map->vsync);
+- crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
+-
+- /*NOTE: DSPSIZE DSPPOS only for psb*/
+- crtc_state->saveDSPSIZE = REG_READ(map->size);
+- crtc_state->saveDSPPOS = REG_READ(map->pos);
+-
+- crtc_state->saveDSPBASE = REG_READ(map->base);
+-
+- paletteReg = map->palette;
+- for (i = 0; i < 256; ++i)
+- crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
+-}
+-
+-/**
+- * Restore HW states of giving crtc
+- */
+-static void psb_intel_crtc_restore(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
+- uint32_t paletteReg;
+- int i;
+-
+- if (!crtc_state) {
+- dev_err(dev->dev, "No crtc state\n");
+- return;
+- }
+-
+- if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
+- REG_WRITE(map->dpll,
+- crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- udelay(150);
+- }
+-
+- REG_WRITE(map->fp0, crtc_state->saveFP0);
+- REG_READ(map->fp0);
+-
+- REG_WRITE(map->fp1, crtc_state->saveFP1);
+- REG_READ(map->fp1);
+-
+- REG_WRITE(map->dpll, crtc_state->saveDPLL);
+- REG_READ(map->dpll);
+- udelay(150);
+-
+- REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
+- REG_WRITE(map->hblank, crtc_state->saveHBLANK);
+- REG_WRITE(map->hsync, crtc_state->saveHSYNC);
+- REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
+- REG_WRITE(map->vblank, crtc_state->saveVBLANK);
+- REG_WRITE(map->vsync, crtc_state->saveVSYNC);
+- REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
+-
+- REG_WRITE(map->size, crtc_state->saveDSPSIZE);
+- REG_WRITE(map->pos, crtc_state->saveDSPPOS);
+-
+- REG_WRITE(map->src, crtc_state->savePIPESRC);
+- REG_WRITE(map->base, crtc_state->saveDSPBASE);
+- REG_WRITE(map->conf, crtc_state->savePIPECONF);
+-
+- gma_wait_for_vblank(dev);
+-
+- REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
+- REG_WRITE(map->base, crtc_state->saveDSPBASE);
+-
+- gma_wait_for_vblank(dev);
+-
+- paletteReg = map->palette;
+- for (i = 0; i < 256; ++i)
+- REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
+-}
+-
+ static int psb_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret;
+@@ -560,8 +455,8 @@ const struct drm_crtc_helper_funcs psb_i
+ };
+
+ const struct drm_crtc_funcs psb_intel_crtc_funcs = {
+- .save = psb_intel_crtc_save,
+- .restore = psb_intel_crtc_restore,
++ .save = gma_crtc_save,
++ .restore = gma_crtc_restore,
+ .cursor_set = gma_crtc_cursor_set,
+ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
--- /dev/null
+From c058a962a6bc52772ef623b143c5b4d52d339158 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:33:47 +0200
+Subject: drm/gma500/cdv: Convert to generic save/restore
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit f0ff07b73b9b5be1f725f333d1516d569c697104)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 172 -----------------------------
+ 1 file changed, 2 insertions(+), 170 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -867,174 +867,6 @@ static int cdv_intel_crtc_mode_set(struc
+ return 0;
+ }
+
+-
+-/**
+- * Save HW states of giving crtc
+- */
+-static void cdv_intel_crtc_save(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
+- uint32_t paletteReg;
+- int i;
+-
+- if (!crtc_state) {
+- dev_dbg(dev->dev, "No CRTC state found\n");
+- return;
+- }
+-
+- crtc_state->saveDSPCNTR = REG_READ(map->cntr);
+- crtc_state->savePIPECONF = REG_READ(map->conf);
+- crtc_state->savePIPESRC = REG_READ(map->src);
+- crtc_state->saveFP0 = REG_READ(map->fp0);
+- crtc_state->saveFP1 = REG_READ(map->fp1);
+- crtc_state->saveDPLL = REG_READ(map->dpll);
+- crtc_state->saveHTOTAL = REG_READ(map->htotal);
+- crtc_state->saveHBLANK = REG_READ(map->hblank);
+- crtc_state->saveHSYNC = REG_READ(map->hsync);
+- crtc_state->saveVTOTAL = REG_READ(map->vtotal);
+- crtc_state->saveVBLANK = REG_READ(map->vblank);
+- crtc_state->saveVSYNC = REG_READ(map->vsync);
+- crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
+-
+- /*NOTE: DSPSIZE DSPPOS only for psb*/
+- crtc_state->saveDSPSIZE = REG_READ(map->size);
+- crtc_state->saveDSPPOS = REG_READ(map->pos);
+-
+- crtc_state->saveDSPBASE = REG_READ(map->base);
+-
+- DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
+- crtc_state->saveDSPCNTR,
+- crtc_state->savePIPECONF,
+- crtc_state->savePIPESRC,
+- crtc_state->saveFP0,
+- crtc_state->saveFP1,
+- crtc_state->saveDPLL,
+- crtc_state->saveHTOTAL,
+- crtc_state->saveHBLANK,
+- crtc_state->saveHSYNC,
+- crtc_state->saveVTOTAL,
+- crtc_state->saveVBLANK,
+- crtc_state->saveVSYNC,
+- crtc_state->saveDSPSTRIDE,
+- crtc_state->saveDSPSIZE,
+- crtc_state->saveDSPPOS,
+- crtc_state->saveDSPBASE
+- );
+-
+- paletteReg = map->palette;
+- for (i = 0; i < 256; ++i)
+- crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
+-}
+-
+-/**
+- * Restore HW states of giving crtc
+- */
+-static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
+-{
+- struct drm_device *dev = crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
+- uint32_t paletteReg;
+- int i;
+-
+- if (!crtc_state) {
+- dev_dbg(dev->dev, "No crtc state\n");
+- return;
+- }
+-
+- DRM_DEBUG(
+- "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
+- REG_READ(map->cntr),
+- REG_READ(map->conf),
+- REG_READ(map->src),
+- REG_READ(map->fp0),
+- REG_READ(map->fp1),
+- REG_READ(map->dpll),
+- REG_READ(map->htotal),
+- REG_READ(map->hblank),
+- REG_READ(map->hsync),
+- REG_READ(map->vtotal),
+- REG_READ(map->vblank),
+- REG_READ(map->vsync),
+- REG_READ(map->stride),
+- REG_READ(map->size),
+- REG_READ(map->pos),
+- REG_READ(map->base)
+- );
+-
+- DRM_DEBUG(
+- "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
+- crtc_state->saveDSPCNTR,
+- crtc_state->savePIPECONF,
+- crtc_state->savePIPESRC,
+- crtc_state->saveFP0,
+- crtc_state->saveFP1,
+- crtc_state->saveDPLL,
+- crtc_state->saveHTOTAL,
+- crtc_state->saveHBLANK,
+- crtc_state->saveHSYNC,
+- crtc_state->saveVTOTAL,
+- crtc_state->saveVBLANK,
+- crtc_state->saveVSYNC,
+- crtc_state->saveDSPSTRIDE,
+- crtc_state->saveDSPSIZE,
+- crtc_state->saveDSPPOS,
+- crtc_state->saveDSPBASE
+- );
+-
+-
+- if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
+- REG_WRITE(map->dpll,
+- crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- DRM_DEBUG("write dpll: %x\n",
+- REG_READ(map->dpll));
+- udelay(150);
+- }
+-
+- REG_WRITE(map->fp0, crtc_state->saveFP0);
+- REG_READ(map->fp0);
+-
+- REG_WRITE(map->fp1, crtc_state->saveFP1);
+- REG_READ(map->fp1);
+-
+- REG_WRITE(map->dpll, crtc_state->saveDPLL);
+- REG_READ(map->dpll);
+- udelay(150);
+-
+- REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
+- REG_WRITE(map->hblank, crtc_state->saveHBLANK);
+- REG_WRITE(map->hsync, crtc_state->saveHSYNC);
+- REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
+- REG_WRITE(map->vblank, crtc_state->saveVBLANK);
+- REG_WRITE(map->vsync, crtc_state->saveVSYNC);
+- REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
+-
+- REG_WRITE(map->size, crtc_state->saveDSPSIZE);
+- REG_WRITE(map->pos, crtc_state->saveDSPPOS);
+-
+- REG_WRITE(map->src, crtc_state->savePIPESRC);
+- REG_WRITE(map->base, crtc_state->saveDSPBASE);
+- REG_WRITE(map->conf, crtc_state->savePIPECONF);
+-
+- gma_wait_for_vblank(dev);
+-
+- REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
+- REG_WRITE(map->base, crtc_state->saveDSPBASE);
+-
+- gma_wait_for_vblank(dev);
+-
+- paletteReg = map->palette;
+- for (i = 0; i < 256; ++i)
+- REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
+-}
+-
+ static int cdv_crtc_set_config(struct drm_mode_set *set)
+ {
+ int ret = 0;
+@@ -1203,8 +1035,8 @@ const struct drm_crtc_helper_funcs cdv_i
+ };
+
+ const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
+- .save = cdv_intel_crtc_save,
+- .restore = cdv_intel_crtc_restore,
++ .save = gma_crtc_save,
++ .restore = gma_crtc_restore,
+ .cursor_set = gma_crtc_cursor_set,
+ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
--- /dev/null
+From 24ebca9495e8d9f8af9b2eedfca5f46c6f178860 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:38:52 +0200
+Subject: drm/gma500: Add generic set_config() function
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 924cb5ffd81d66cc6461de955f7cb144cb3b7b6d)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/gma_display.c | 16 ++++++++++++++++
+ drivers/gpu/drm/gma500/gma_display.h | 3 +++
+ 2 files changed, 19 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -519,6 +519,22 @@ void gma_crtc_destroy(struct drm_crtc *c
+ kfree(psb_intel_crtc);
+ }
+
++int gma_crtc_set_config(struct drm_mode_set *set)
++{
++ struct drm_device *dev = set->crtc->dev;
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ int ret;
++
++ if (!dev_priv->rpm_enabled)
++ return drm_crtc_helper_set_config(set);
++
++ pm_runtime_forbid(&dev->pdev->dev);
++ ret = drm_crtc_helper_set_config(set);
++ pm_runtime_allow(&dev->pdev->dev);
++
++ return ret;
++}
++
+ /**
+ * Save HW states of given crtc
+ */
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -22,6 +22,8 @@
+ #ifndef _GMA_DISPLAY_H_
+ #define _GMA_DISPLAY_H_
+
++#include <linux/pm_runtime.h>
++
+ struct gma_clock_t {
+ /* given values */
+ int n;
+@@ -80,6 +82,7 @@ extern void gma_crtc_prepare(struct drm_
+ extern void gma_crtc_commit(struct drm_crtc *crtc);
+ extern void gma_crtc_disable(struct drm_crtc *crtc);
+ extern void gma_crtc_destroy(struct drm_crtc *crtc);
++extern int gma_crtc_set_config(struct drm_mode_set *set);
+
+ extern void gma_crtc_save(struct drm_crtc *crtc);
+ extern void gma_crtc_restore(struct drm_crtc *crtc);
--- /dev/null
+From 0dae7ec3869d4524c8535ad075317c24d09385b5 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:41:36 +0200
+Subject: drm/gma500/psb: Convert to generic set_config()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 43a83027d4705bb6b6506f9467c9c4d3e2a1b504)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_display.c | 18 +-----------------
+ 1 file changed, 1 insertion(+), 17 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -19,7 +19,6 @@
+ */
+
+ #include <linux/i2c.h>
+-#include <linux/pm_runtime.h>
+
+ #include <drm/drmP.h>
+ #include "framebuffer.h"
+@@ -305,21 +304,6 @@ static int psb_intel_crtc_mode_set(struc
+ return 0;
+ }
+
+-static int psb_crtc_set_config(struct drm_mode_set *set)
+-{
+- int ret;
+- struct drm_device *dev = set->crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+-
+- if (!dev_priv->rpm_enabled)
+- return drm_crtc_helper_set_config(set);
+-
+- pm_runtime_forbid(&dev->pdev->dev);
+- ret = drm_crtc_helper_set_config(set);
+- pm_runtime_allow(&dev->pdev->dev);
+- return ret;
+-}
+-
+ /* Returns the clock of the currently programmed mode of the given pipe. */
+ static int psb_intel_crtc_clock_get(struct drm_device *dev,
+ struct drm_crtc *crtc)
+@@ -460,7 +444,7 @@ const struct drm_crtc_funcs psb_intel_cr
+ .cursor_set = gma_crtc_cursor_set,
+ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
+- .set_config = psb_crtc_set_config,
++ .set_config = gma_crtc_set_config,
+ .destroy = gma_crtc_destroy,
+ };
+
--- /dev/null
+From 0a69783bcec380e67781df416dc5bf11184b9ddb Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 12 Jul 2013 15:43:54 +0200
+Subject: drm/gma500/cdv: Convert to generic set_config()
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit c5c81f4e1bc9c8ee1c3637de51ee180efbbf629c)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 21 +--------------------
+ 1 file changed, 1 insertion(+), 20 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -19,7 +19,6 @@
+ */
+
+ #include <linux/i2c.h>
+-#include <linux/pm_runtime.h>
+
+ #include <drm/drmP.h>
+ #include "framebuffer.h"
+@@ -867,24 +866,6 @@ static int cdv_intel_crtc_mode_set(struc
+ return 0;
+ }
+
+-static int cdv_crtc_set_config(struct drm_mode_set *set)
+-{
+- int ret = 0;
+- struct drm_device *dev = set->crtc->dev;
+- struct drm_psb_private *dev_priv = dev->dev_private;
+-
+- if (!dev_priv->rpm_enabled)
+- return drm_crtc_helper_set_config(set);
+-
+- pm_runtime_forbid(&dev->pdev->dev);
+-
+- ret = drm_crtc_helper_set_config(set);
+-
+- pm_runtime_allow(&dev->pdev->dev);
+-
+- return ret;
+-}
+-
+ /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
+
+ /* FIXME: why are we using this, should it be cdv_ in this tree ? */
+@@ -1040,7 +1021,7 @@ const struct drm_crtc_funcs cdv_intel_cr
+ .cursor_set = gma_crtc_cursor_set,
+ .cursor_move = gma_crtc_cursor_move,
+ .gamma_set = gma_crtc_gamma_set,
+- .set_config = cdv_crtc_set_config,
++ .set_config = gma_crtc_set_config,
+ .destroy = gma_crtc_destroy,
+ };
+
--- /dev/null
+From 32b084d7bbef23ffbc8f9c1d40c7224f345d5c7d Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 22 Jul 2013 01:31:23 +0200
+Subject: drm/gma500: Rename psb_intel_crtc to gma_crtc
+
+The psb_intel_crtc is generic and should be named appropriately
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 6306865daf0283d1b13adea8be8d1ad4dd0ea1c3)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_crt.c | 7 -
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 28 +++----
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 10 +-
+ drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 6 -
+ drivers/gpu/drm/gma500/cdv_intel_lvds.c | 8 --
+ drivers/gpu/drm/gma500/framebuffer.c | 16 ++--
+ drivers/gpu/drm/gma500/gma_display.c | 105 +++++++++++++--------------
+ drivers/gpu/drm/gma500/mdfld_dsi_output.c | 15 +--
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 16 ++--
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 16 ++--
+ drivers/gpu/drm/gma500/psb_drv.c | 6 -
+ drivers/gpu/drm/gma500/psb_intel_display.c | 98 ++++++++++++-------------
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 6 -
+ drivers/gpu/drm/gma500/psb_intel_lvds.c | 10 +-
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 4 -
+ 15 files changed, 170 insertions(+), 181 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_crt.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c
+@@ -95,13 +95,12 @@ static void cdv_intel_crt_mode_set(struc
+
+ struct drm_device *dev = encoder->dev;
+ struct drm_crtc *crtc = encoder->crtc;
+- struct psb_intel_crtc *psb_intel_crtc =
+- to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ int dpll_md_reg;
+ u32 adpa, dpll_md;
+ u32 adpa_reg;
+
+- if (psb_intel_crtc->pipe == 0)
++ if (gma_crtc->pipe == 0)
+ dpll_md_reg = DPLL_A_MD;
+ else
+ dpll_md_reg = DPLL_B_MD;
+@@ -124,7 +123,7 @@ static void cdv_intel_crt_mode_set(struc
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ adpa |= ADPA_VSYNC_ACTIVE_HIGH;
+
+- if (psb_intel_crtc->pipe == 0)
++ if (gma_crtc->pipe == 0)
+ adpa |= ADPA_PIPE_A_SELECT;
+ else
+ adpa |= ADPA_PIPE_B_SELECT;
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -222,8 +222,8 @@ static int
+ cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
+ struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
+ {
+- struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ u32 m, n_vco, p;
+ int ret = 0;
+ int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+@@ -458,12 +458,12 @@ static bool cdv_intel_pipe_enabled(struc
+ {
+ struct drm_crtc *crtc;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = NULL;
++ struct gma_crtc *gma_crtc = NULL;
+
+ crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+- psb_intel_crtc = to_psb_intel_crtc(crtc);
++ gma_crtc = to_gma_crtc(crtc);
+
+- if (crtc->fb == NULL || !psb_intel_crtc->active)
++ if (crtc->fb == NULL || !gma_crtc->active)
+ return false;
+ return true;
+ }
+@@ -489,11 +489,11 @@ static bool cdv_intel_single_pipe_active
+
+ static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_connector *connector;
+
+- if (psb_intel_crtc->pipe != 1)
++ if (gma_crtc->pipe != 1)
+ return false;
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+@@ -616,8 +616,8 @@ static int cdv_intel_crtc_mode_set(struc
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk;
+ struct gma_clock_t clock;
+@@ -693,7 +693,7 @@ static int cdv_intel_crtc_mode_set(struc
+
+ drm_mode_debug_printmodeline(adjusted_mode);
+
+- limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
++ limit = gma_crtc->clock_funcs->limit(crtc, refclk);
+
+ ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
+ &clock);
+@@ -883,8 +883,8 @@ static int cdv_intel_crtc_clock_get(stru
+ struct drm_crtc *crtc)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 dpll;
+ u32 fp;
+@@ -961,8 +961,8 @@ static int cdv_intel_crtc_clock_get(stru
+ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -793,10 +793,10 @@ cdv_intel_dp_set_m_n(struct drm_crtc *cr
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct drm_encoder *encoder;
+- struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ int lane_count = 4, bpp = 24;
+ struct cdv_intel_dp_m_n m_n;
+- int pipe = intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+
+ /*
+ * Find the lane count in the intel_encoder private
+@@ -844,7 +844,7 @@ cdv_intel_dp_mode_set(struct drm_encoder
+ {
+ struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
+- struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct drm_device *dev = encoder->dev;
+
+@@ -886,7 +886,7 @@ cdv_intel_dp_mode_set(struct drm_encoder
+ }
+
+ /* CPT DP's pipe select is decided in TRANS_DP_CTL */
+- if (intel_crtc->pipe == 1)
++ if (gma_crtc->pipe == 1)
+ intel_dp->DP |= DP_PIPEB_SELECT;
+
+ REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
+@@ -901,7 +901,7 @@ cdv_intel_dp_mode_set(struct drm_encoder
+ else
+ pfit_control = 0;
+
+- pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT;
++ pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
+
+ REG_WRITE(PFIT_CONTROL, pfit_control);
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
+@@ -68,7 +68,7 @@ static void cdv_hdmi_mode_set(struct drm
+ struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
+ u32 hdmib;
+ struct drm_crtc *crtc = encoder->crtc;
+- struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+
+ hdmib = (2 << 10);
+
+@@ -77,7 +77,7 @@ static void cdv_hdmi_mode_set(struct drm
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ hdmib |= HDMI_HSYNC_ACTIVE_HIGH;
+
+- if (intel_crtc->pipe == 1)
++ if (gma_crtc->pipe == 1)
+ hdmib |= HDMIB_PIPE_B_SELECT;
+
+ if (hdmi_priv->has_hdmi_audio) {
+@@ -167,7 +167,7 @@ static int cdv_hdmi_set_property(struct
+ struct drm_encoder *encoder = connector->encoder;
+
+ if (!strcmp(property->name, "scaling mode") && encoder) {
+- struct psb_intel_crtc *crtc = to_psb_intel_crtc(encoder->crtc);
++ struct gma_crtc *crtc = to_gma_crtc(encoder->crtc);
+ bool centre;
+ uint64_t curValue;
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
+@@ -356,8 +356,7 @@ static void cdv_intel_lvds_mode_set(stru
+ {
+ struct drm_device *dev = encoder->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(
+- encoder->crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc);
+ u32 pfit_control;
+
+ /*
+@@ -379,7 +378,7 @@ static void cdv_intel_lvds_mode_set(stru
+ else
+ pfit_control = 0;
+
+- pfit_control |= psb_intel_crtc->pipe << PFIT_PIPE_SHIFT;
++ pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
+
+ if (dev_priv->lvds_dither)
+ pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+@@ -461,8 +460,7 @@ static int cdv_intel_lvds_set_property(s
+ struct drm_encoder *encoder = connector->encoder;
+
+ if (!strcmp(property->name, "scaling mode") && encoder) {
+- struct psb_intel_crtc *crtc =
+- to_psb_intel_crtc(encoder->crtc);
++ struct gma_crtc *crtc = to_gma_crtc(encoder->crtc);
+ uint64_t curValue;
+
+ if (!crtc)
+--- a/drivers/gpu/drm/gma500/framebuffer.c
++++ b/drivers/gpu/drm/gma500/framebuffer.c
+@@ -520,21 +520,21 @@ static struct drm_framebuffer *psb_user_
+ static void psbfb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+ u16 blue, int regno)
+ {
+- struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+
+- intel_crtc->lut_r[regno] = red >> 8;
+- intel_crtc->lut_g[regno] = green >> 8;
+- intel_crtc->lut_b[regno] = blue >> 8;
++ gma_crtc->lut_r[regno] = red >> 8;
++ gma_crtc->lut_g[regno] = green >> 8;
++ gma_crtc->lut_b[regno] = blue >> 8;
+ }
+
+ static void psbfb_gamma_get(struct drm_crtc *crtc, u16 *red,
+ u16 *green, u16 *blue, int regno)
+ {
+- struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+
+- *red = intel_crtc->lut_r[regno] << 8;
+- *green = intel_crtc->lut_g[regno] << 8;
+- *blue = intel_crtc->lut_b[regno] << 8;
++ *red = gma_crtc->lut_r[regno] << 8;
++ *green = gma_crtc->lut_g[regno] << 8;
++ *blue = gma_crtc->lut_b[regno] << 8;
+ }
+
+ static int psbfb_probe(struct drm_fb_helper *helper,
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -58,9 +58,9 @@ int gma_pipe_set_base(struct drm_crtc *c
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ unsigned long start, offset;
+ u32 dspcntr;
+@@ -140,8 +140,8 @@ void gma_crtc_load_lut(struct drm_crtc *
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
+ int palreg = map->palette;
+ int i;
+
+@@ -152,24 +152,24 @@ void gma_crtc_load_lut(struct drm_crtc *
+ if (gma_power_begin(dev, false)) {
+ for (i = 0; i < 256; i++) {
+ REG_WRITE(palreg + 4 * i,
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]));
++ ((gma_crtc->lut_r[i] +
++ gma_crtc->lut_adj[i]) << 16) |
++ ((gma_crtc->lut_g[i] +
++ gma_crtc->lut_adj[i]) << 8) |
++ (gma_crtc->lut_b[i] +
++ gma_crtc->lut_adj[i]));
+ }
+ gma_power_end(dev);
+ } else {
+ for (i = 0; i < 256; i++) {
+ /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
+ dev_priv->regs.pipe[0].palette[i] =
+- ((psb_intel_crtc->lut_r[i] +
+- psb_intel_crtc->lut_adj[i]) << 16) |
+- ((psb_intel_crtc->lut_g[i] +
+- psb_intel_crtc->lut_adj[i]) << 8) |
+- (psb_intel_crtc->lut_b[i] +
+- psb_intel_crtc->lut_adj[i]);
++ ((gma_crtc->lut_r[i] +
++ gma_crtc->lut_adj[i]) << 16) |
++ ((gma_crtc->lut_g[i] +
++ gma_crtc->lut_adj[i]) << 8) |
++ (gma_crtc->lut_b[i] +
++ gma_crtc->lut_adj[i]);
+ }
+
+ }
+@@ -178,14 +178,14 @@ void gma_crtc_load_lut(struct drm_crtc *
+ void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
+ u32 start, u32 size)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ int i;
+ int end = (start + size > 256) ? 256 : start + size;
+
+ for (i = start; i < end; i++) {
+- psb_intel_crtc->lut_r[i] = red[i] >> 8;
+- psb_intel_crtc->lut_g[i] = green[i] >> 8;
+- psb_intel_crtc->lut_b[i] = blue[i] >> 8;
++ gma_crtc->lut_r[i] = red[i] >> 8;
++ gma_crtc->lut_g[i] = green[i] >> 8;
++ gma_crtc->lut_b[i] = blue[i] >> 8;
+ }
+
+ gma_crtc_load_lut(crtc);
+@@ -201,8 +201,8 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 temp;
+
+@@ -217,10 +217,10 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ case DRM_MODE_DPMS_ON:
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+- if (psb_intel_crtc->active)
++ if (gma_crtc->active)
+ break;
+
+- psb_intel_crtc->active = true;
++ gma_crtc->active = true;
+
+ /* Enable the DPLL */
+ temp = REG_READ(map->dpll);
+@@ -268,10 +268,10 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ /* psb_intel_crtc_dpms_video(crtc, true); TODO */
+ break;
+ case DRM_MODE_DPMS_OFF:
+- if (!psb_intel_crtc->active)
++ if (!gma_crtc->active)
+ break;
+
+- psb_intel_crtc->active = false;
++ gma_crtc->active = false;
+
+ /* Give the overlay scaler a chance to disable
+ * if it's on this pipe */
+@@ -334,14 +334,14 @@ int gma_crtc_cursor_set(struct drm_crtc
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
+ uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
+ uint32_t temp;
+ size_t addr = 0;
+ struct gtt_range *gt;
+- struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
++ struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
+ struct drm_gem_object *obj;
+ void *tmp_dst, *tmp_src;
+ int ret = 0, i, cursor_pages;
+@@ -357,12 +357,12 @@ int gma_crtc_cursor_set(struct drm_crtc
+ }
+
+ /* Unpin the old GEM object */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
++ if (gma_crtc->cursor_obj) {
++ gt = container_of(gma_crtc->cursor_obj,
+ struct gtt_range, gem);
+ psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+- psb_intel_crtc->cursor_obj = NULL;
++ drm_gem_object_unreference(gma_crtc->cursor_obj);
++ gma_crtc->cursor_obj = NULL;
+ }
+
+ return 0;
+@@ -415,10 +415,10 @@ int gma_crtc_cursor_set(struct drm_crtc
+ tmp_dst += PAGE_SIZE;
+ }
+
+- addr = psb_intel_crtc->cursor_addr;
++ addr = gma_crtc->cursor_addr;
+ } else {
+ addr = gt->offset;
+- psb_intel_crtc->cursor_addr = addr;
++ gma_crtc->cursor_addr = addr;
+ }
+
+ temp = 0;
+@@ -433,14 +433,13 @@ int gma_crtc_cursor_set(struct drm_crtc
+ }
+
+ /* unpin the old bo */
+- if (psb_intel_crtc->cursor_obj) {
+- gt = container_of(psb_intel_crtc->cursor_obj,
+- struct gtt_range, gem);
++ if (gma_crtc->cursor_obj) {
++ gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem);
+ psb_gtt_unpin(gt);
+- drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
++ drm_gem_object_unreference(gma_crtc->cursor_obj);
+ }
+
+- psb_intel_crtc->cursor_obj = obj;
++ gma_crtc->cursor_obj = obj;
+ return ret;
+
+ unref_cursor:
+@@ -451,8 +450,8 @@ unref_cursor:
+ int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ uint32_t temp = 0;
+ uint32_t addr;
+
+@@ -468,7 +467,7 @@ int gma_crtc_cursor_move(struct drm_crtc
+ temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
+ temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
+
+- addr = psb_intel_crtc->cursor_addr;
++ addr = gma_crtc->cursor_addr;
+
+ if (gma_power_begin(dev, false)) {
+ REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
+@@ -512,11 +511,11 @@ void gma_crtc_disable(struct drm_crtc *c
+
+ void gma_crtc_destroy(struct drm_crtc *crtc)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+
+- kfree(psb_intel_crtc->crtc_state);
++ kfree(gma_crtc->crtc_state);
+ drm_crtc_cleanup(crtc);
+- kfree(psb_intel_crtc);
++ kfree(gma_crtc);
+ }
+
+ int gma_crtc_set_config(struct drm_mode_set *set)
+@@ -542,9 +541,9 @@ void gma_crtc_save(struct drm_crtc *crtc
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
++ const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
+ uint32_t palette_reg;
+ int i;
+
+@@ -585,9 +584,9 @@ void gma_crtc_restore(struct drm_crtc *c
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
+- const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
++ const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
+ uint32_t palette_reg;
+ int i;
+
+@@ -720,7 +719,7 @@ bool gma_find_best_pll(const struct gma_
+ {
+ struct drm_device *dev = crtc->dev;
+ const struct gma_clock_funcs *clock_funcs =
+- to_psb_intel_crtc(crtc)->clock_funcs;
++ to_gma_crtc(crtc)->clock_funcs;
+ struct gma_clock_t clock;
+ int err = target;
+
+--- a/drivers/gpu/drm/gma500/mdfld_dsi_output.c
++++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.c
+@@ -249,12 +249,11 @@ static int mdfld_dsi_connector_set_prope
+ struct drm_encoder *encoder = connector->encoder;
+
+ if (!strcmp(property->name, "scaling mode") && encoder) {
+- struct psb_intel_crtc *psb_crtc =
+- to_psb_intel_crtc(encoder->crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc);
+ bool centerechange;
+ uint64_t val;
+
+- if (!psb_crtc)
++ if (!gma_crtc)
+ goto set_prop_error;
+
+ switch (value) {
+@@ -281,11 +280,11 @@ static int mdfld_dsi_connector_set_prope
+ centerechange = (val == DRM_MODE_SCALE_NO_SCALE) ||
+ (value == DRM_MODE_SCALE_NO_SCALE);
+
+- if (psb_crtc->saved_mode.hdisplay != 0 &&
+- psb_crtc->saved_mode.vdisplay != 0) {
++ if (gma_crtc->saved_mode.hdisplay != 0 &&
++ gma_crtc->saved_mode.vdisplay != 0) {
+ if (centerechange) {
+ if (!drm_crtc_helper_set_mode(encoder->crtc,
+- &psb_crtc->saved_mode,
++ &gma_crtc->saved_mode,
+ encoder->crtc->x,
+ encoder->crtc->y,
+ encoder->crtc->fb))
+@@ -294,8 +293,8 @@ static int mdfld_dsi_connector_set_prope
+ struct drm_encoder_helper_funcs *funcs =
+ encoder->helper_private;
+ funcs->mode_set(encoder,
+- &psb_crtc->saved_mode,
+- &psb_crtc->saved_adjusted_mode);
++ &gma_crtc->saved_mode,
++ &gma_crtc->saved_adjusted_mode);
+ }
+ }
+ } else if (!strcmp(property->name, "backlight") && encoder) {
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -165,9 +165,9 @@ static int mdfld__intel_pipe_set_base(st
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ unsigned long start, offset;
+ u32 dspcntr;
+@@ -305,8 +305,8 @@ static void mdfld_crtc_dpms(struct drm_c
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 pipeconf = dev_priv->pipeconf[pipe];
+ u32 temp;
+@@ -669,9 +669,9 @@ static int mdfld_crtc_mode_set(struct dr
+ struct drm_framebuffer *old_fb)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk = 0;
+ int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0,
+@@ -730,9 +730,9 @@ static int mdfld_crtc_mode_set(struct dr
+ if (!gma_power_begin(dev, true))
+ return 0;
+
+- memcpy(&psb_intel_crtc->saved_mode, mode,
++ memcpy(&gma_crtc->saved_mode, mode,
+ sizeof(struct drm_display_mode));
+- memcpy(&psb_intel_crtc->saved_adjusted_mode, adjusted_mode,
++ memcpy(&gma_crtc->saved_adjusted_mode, adjusted_mode,
+ sizeof(struct drm_display_mode));
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -163,8 +163,8 @@ static void oaktrail_crtc_dpms(struct dr
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 temp;
+
+@@ -292,9 +292,9 @@ static int oaktrail_crtc_mode_set(struct
+ struct drm_framebuffer *old_fb)
+ {
+ struct drm_device *dev = crtc->dev;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk = 0;
+ struct oaktrail_clock_t clock;
+@@ -313,10 +313,10 @@ static int oaktrail_crtc_mode_set(struct
+ if (!gma_power_begin(dev, true))
+ return 0;
+
+- memcpy(&psb_intel_crtc->saved_mode,
++ memcpy(&gma_crtc->saved_mode,
+ mode,
+ sizeof(struct drm_display_mode));
+- memcpy(&psb_intel_crtc->saved_adjusted_mode,
++ memcpy(&gma_crtc->saved_adjusted_mode,
+ adjusted_mode,
+ sizeof(struct drm_display_mode));
+
+@@ -499,9 +499,9 @@ static int oaktrail_pipe_set_base(struct
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ unsigned long start, offset;
+
+--- a/drivers/gpu/drm/gma500/psb_drv.c
++++ b/drivers/gpu/drm/gma500/psb_drv.c
+@@ -441,7 +441,7 @@ static int psb_gamma_ioctl(struct drm_de
+ struct drm_mode_object *obj;
+ struct drm_crtc *crtc;
+ struct drm_connector *connector;
+- struct psb_intel_crtc *psb_intel_crtc;
++ struct gma_crtc *gma_crtc;
+ int i = 0;
+ int32_t obj_id;
+
+@@ -454,10 +454,10 @@ static int psb_gamma_ioctl(struct drm_de
+
+ connector = obj_to_connector(obj);
+ crtc = connector->encoder->crtc;
+- psb_intel_crtc = to_psb_intel_crtc(crtc);
++ gma_crtc = to_gma_crtc(crtc);
+
+ for (i = 0; i < 256; i++)
+- psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
++ gma_crtc->lut_adj[i] = lut_arg->lut[i];
+
+ gma_crtc_load_lut(crtc);
+
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -106,9 +106,9 @@ static int psb_intel_crtc_mode_set(struc
+ {
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk;
+ struct gma_clock_t clock;
+@@ -148,7 +148,7 @@ static int psb_intel_crtc_mode_set(struc
+
+ refclk = 96000;
+
+- limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
++ limit = gma_crtc->clock_funcs->limit(crtc, refclk);
+
+ ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
+ &clock);
+@@ -308,9 +308,9 @@ static int psb_intel_crtc_mode_set(struc
+ static int psb_intel_crtc_clock_get(struct drm_device *dev,
+ struct drm_crtc *crtc)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- int pipe = psb_intel_crtc->pipe;
++ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 dpll;
+ u32 fp;
+@@ -384,8 +384,8 @@ static int psb_intel_crtc_clock_get(stru
+ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc)
+ {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- int pipe = psb_intel_crtc->pipe;
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ int pipe = gma_crtc->pipe;
+ struct drm_display_mode *mode;
+ int htot;
+ int hsync;
+@@ -459,7 +459,7 @@ const struct gma_clock_funcs psb_clock_f
+ * to zero. This is a workaround for h/w defect on Oaktrail
+ */
+ static void psb_intel_cursor_init(struct drm_device *dev,
+- struct psb_intel_crtc *psb_intel_crtc)
++ struct gma_crtc *gma_crtc)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
+@@ -472,91 +472,87 @@ static void psb_intel_cursor_init(struct
+ */
+ cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1);
+ if (!cursor_gt) {
+- psb_intel_crtc->cursor_gt = NULL;
++ gma_crtc->cursor_gt = NULL;
+ goto out;
+ }
+- psb_intel_crtc->cursor_gt = cursor_gt;
+- psb_intel_crtc->cursor_addr = dev_priv->stolen_base +
++ gma_crtc->cursor_gt = cursor_gt;
++ gma_crtc->cursor_addr = dev_priv->stolen_base +
+ cursor_gt->offset;
+ } else {
+- psb_intel_crtc->cursor_gt = NULL;
++ gma_crtc->cursor_gt = NULL;
+ }
+
+ out:
+- REG_WRITE(control[psb_intel_crtc->pipe], 0);
+- REG_WRITE(base[psb_intel_crtc->pipe], 0);
++ REG_WRITE(control[gma_crtc->pipe], 0);
++ REG_WRITE(base[gma_crtc->pipe], 0);
+ }
+
+ void psb_intel_crtc_init(struct drm_device *dev, int pipe,
+ struct psb_intel_mode_device *mode_dev)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_crtc *psb_intel_crtc;
++ struct gma_crtc *gma_crtc;
+ int i;
+ uint16_t *r_base, *g_base, *b_base;
+
+ /* We allocate a extra array of drm_connector pointers
+ * for fbdev after the crtc */
+- psb_intel_crtc =
+- kzalloc(sizeof(struct psb_intel_crtc) +
+- (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
+- GFP_KERNEL);
+- if (psb_intel_crtc == NULL)
++ gma_crtc = kzalloc(sizeof(struct gma_crtc) +
++ (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
++ GFP_KERNEL);
++ if (gma_crtc == NULL)
+ return;
+
+- psb_intel_crtc->crtc_state =
++ gma_crtc->crtc_state =
+ kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
+- if (!psb_intel_crtc->crtc_state) {
++ if (!gma_crtc->crtc_state) {
+ dev_err(dev->dev, "Crtc state error: No memory\n");
+- kfree(psb_intel_crtc);
++ kfree(gma_crtc);
+ return;
+ }
+
+ /* Set the CRTC operations from the chip specific data */
+- drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
++ drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
+
+ /* Set the CRTC clock functions from chip specific data */
+- psb_intel_crtc->clock_funcs = dev_priv->ops->clock_funcs;
++ gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
+
+- drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
+- psb_intel_crtc->pipe = pipe;
+- psb_intel_crtc->plane = pipe;
++ drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
++ gma_crtc->pipe = pipe;
++ gma_crtc->plane = pipe;
+
+- r_base = psb_intel_crtc->base.gamma_store;
++ r_base = gma_crtc->base.gamma_store;
+ g_base = r_base + 256;
+ b_base = g_base + 256;
+ for (i = 0; i < 256; i++) {
+- psb_intel_crtc->lut_r[i] = i;
+- psb_intel_crtc->lut_g[i] = i;
+- psb_intel_crtc->lut_b[i] = i;
++ gma_crtc->lut_r[i] = i;
++ gma_crtc->lut_g[i] = i;
++ gma_crtc->lut_b[i] = i;
+ r_base[i] = i << 8;
+ g_base[i] = i << 8;
+ b_base[i] = i << 8;
+
+- psb_intel_crtc->lut_adj[i] = 0;
++ gma_crtc->lut_adj[i] = 0;
+ }
+
+- psb_intel_crtc->mode_dev = mode_dev;
+- psb_intel_crtc->cursor_addr = 0;
++ gma_crtc->mode_dev = mode_dev;
++ gma_crtc->cursor_addr = 0;
+
+- drm_crtc_helper_add(&psb_intel_crtc->base,
++ drm_crtc_helper_add(&gma_crtc->base,
+ dev_priv->ops->crtc_helper);
+
+ /* Setup the array of drm_connector pointer array */
+- psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
++ gma_crtc->mode_set.crtc = &gma_crtc->base;
+ BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
+- dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
+- dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] =
+- &psb_intel_crtc->base;
+- dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] =
+- &psb_intel_crtc->base;
+- psb_intel_crtc->mode_set.connectors =
+- (struct drm_connector **) (psb_intel_crtc + 1);
+- psb_intel_crtc->mode_set.num_connectors = 0;
+- psb_intel_cursor_init(dev, psb_intel_crtc);
++ dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
++ dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
++ dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
++ gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
++ gma_crtc->mode_set.num_connectors = 0;
++ psb_intel_cursor_init(dev, gma_crtc);
+
+ /* Set to true so that the pipe is forced off on initial config. */
+- psb_intel_crtc->active = true;
++ gma_crtc->active = true;
+ }
+
+ int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
+@@ -565,7 +561,7 @@ int psb_intel_get_pipe_from_crtc_id(stru
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
+ struct drm_mode_object *drmmode_obj;
+- struct psb_intel_crtc *crtc;
++ struct gma_crtc *crtc;
+
+ if (!dev_priv) {
+ dev_err(dev->dev, "called with no initialization\n");
+@@ -580,7 +576,7 @@ int psb_intel_get_pipe_from_crtc_id(stru
+ return -EINVAL;
+ }
+
+- crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
++ crtc = to_gma_crtc(obj_to_crtc(drmmode_obj));
+ pipe_from_crtc_id->pipe = crtc->pipe;
+
+ return 0;
+@@ -591,8 +587,8 @@ struct drm_crtc *psb_intel_get_crtc_from
+ struct drm_crtc *crtc = NULL;
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+- if (psb_intel_crtc->pipe == pipe)
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
++ if (gma_crtc->pipe == pipe)
+ break;
+ }
+ return crtc;
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -162,7 +162,7 @@ struct psb_intel_crtc_state {
+ uint32_t savePalette[256];
+ };
+
+-struct psb_intel_crtc {
++struct gma_crtc {
+ struct drm_crtc base;
+ int pipe;
+ int plane;
+@@ -193,8 +193,8 @@ struct psb_intel_crtc {
+ const struct gma_clock_funcs *clock_funcs;
+ };
+
+-#define to_psb_intel_crtc(x) \
+- container_of(x, struct psb_intel_crtc, base)
++#define to_gma_crtc(x) \
++ container_of(x, struct gma_crtc, base)
+ #define to_psb_intel_connector(x) \
+ container_of(x, struct psb_intel_connector, base)
+ #define to_psb_intel_encoder(x) \
+--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
+@@ -381,8 +381,7 @@ bool psb_intel_lvds_mode_fixup(struct dr
+ struct drm_device *dev = encoder->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+- struct psb_intel_crtc *psb_intel_crtc =
+- to_psb_intel_crtc(encoder->crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc);
+ struct drm_encoder *tmp_encoder;
+ struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode;
+ struct psb_intel_encoder *psb_intel_encoder =
+@@ -392,11 +391,11 @@ bool psb_intel_lvds_mode_fixup(struct dr
+ panel_fixed_mode = mode_dev->panel_fixed_mode2;
+
+ /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
+- if (!IS_MRST(dev) && psb_intel_crtc->pipe == 0) {
++ if (!IS_MRST(dev) && gma_crtc->pipe == 0) {
+ printk(KERN_ERR "Can't support LVDS on pipe A\n");
+ return false;
+ }
+- if (IS_MRST(dev) && psb_intel_crtc->pipe != 0) {
++ if (IS_MRST(dev) && gma_crtc->pipe != 0) {
+ printk(KERN_ERR "Must use PIPE A\n");
+ return false;
+ }
+@@ -585,8 +584,7 @@ int psb_intel_lvds_set_property(struct d
+ return -1;
+
+ if (!strcmp(property->name, "scaling mode")) {
+- struct psb_intel_crtc *crtc =
+- to_psb_intel_crtc(encoder->crtc);
++ struct gma_crtc *crtc = to_gma_crtc(encoder->crtc);
+ uint64_t curval;
+
+ if (!crtc)
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -987,7 +987,7 @@ static void psb_intel_sdvo_mode_set(stru
+ {
+ struct drm_device *dev = encoder->dev;
+ struct drm_crtc *crtc = encoder->crtc;
+- struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
++ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
+ u32 sdvox;
+ struct psb_intel_sdvo_in_out_map in_out;
+@@ -1070,7 +1070,7 @@ static void psb_intel_sdvo_mode_set(stru
+ }
+ sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
+
+- if (psb_intel_crtc->pipe == 1)
++ if (gma_crtc->pipe == 1)
+ sdvox |= SDVO_PIPE_B_SELECT;
+ if (psb_intel_sdvo->has_hdmi_audio)
+ sdvox |= SDVO_AUDIO_ENABLE;
--- /dev/null
+From e58e08ae8483015454b0fe1f6f1d68fd65d34650 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 22 Jul 2013 17:05:25 +0200
+Subject: drm/gma500: Rename psb_intel_connector to gma_connector
+
+The psb_intel_connector is generic and should be named appropriately
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit a3d5d75f694396aa574c4dadbd6008e2cc9a2bbb)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_crt.c | 14 +++++++-------
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 16 ++++++++--------
+ drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 12 ++++++------
+ drivers/gpu/drm/gma500/cdv_intel_lvds.c | 12 ++++++------
+ drivers/gpu/drm/gma500/framebuffer.c | 2 +-
+ drivers/gpu/drm/gma500/framebuffer.h | 2 +-
+ drivers/gpu/drm/gma500/gma_display.c | 2 +-
+ drivers/gpu/drm/gma500/mdfld_dsi_output.h | 8 ++++----
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 10 +++++-----
+ drivers/gpu/drm/gma500/oaktrail_lvds.c | 12 ++++++------
+ drivers/gpu/drm/gma500/psb_intel_display.c | 2 +-
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 10 +++++-----
+ drivers/gpu/drm/gma500/psb_intel_lvds.c | 15 +++++++--------
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 12 ++++++------
+ 14 files changed, 64 insertions(+), 65 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_crt.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c
+@@ -259,7 +259,7 @@ void cdv_intel_crt_init(struct drm_devic
+ struct psb_intel_mode_device *mode_dev)
+ {
+
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct psb_intel_encoder *psb_intel_encoder;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+@@ -270,11 +270,11 @@ void cdv_intel_crt_init(struct drm_devic
+ if (!psb_intel_encoder)
+ return;
+
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+- if (!psb_intel_connector)
++ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
++ if (!gma_connector)
+ goto failed_connector;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ drm_connector_init(dev, connector,
+ &cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
+@@ -283,7 +283,7 @@ void cdv_intel_crt_init(struct drm_devic
+ drm_encoder_init(dev, encoder,
+ &cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+
+ /* Set up the DDC bus. */
+ i2c_reg = GPIOA;
+@@ -317,8 +317,8 @@ void cdv_intel_crt_init(struct drm_devic
+ return;
+ failed_ddc:
+ drm_encoder_cleanup(&psb_intel_encoder->base);
+- drm_connector_cleanup(&psb_intel_connector->base);
+- kfree(psb_intel_connector);
++ drm_connector_cleanup(&gma_connector->base);
++ kfree(gma_connector);
+ failed_connector:
+ kfree(psb_intel_encoder);
+ return;
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -648,7 +648,7 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapt
+ }
+
+ static int
+-cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
++cdv_intel_dp_i2c_init(struct gma_connector *connector, struct psb_intel_encoder *encoder, const char *name)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+@@ -1803,7 +1803,7 @@ void
+ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct cdv_intel_dp *intel_dp;
+@@ -1813,8 +1813,8 @@ cdv_intel_dp_init(struct drm_device *dev
+ psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+ if (!psb_intel_encoder)
+ return;
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+- if (!psb_intel_connector)
++ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
++ if (!gma_connector)
+ goto err_connector;
+ intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
+ if (!intel_dp)
+@@ -1823,13 +1823,13 @@ cdv_intel_dp_init(struct drm_device *dev
+ if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
+ type = DRM_MODE_CONNECTOR_eDP;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ encoder = &psb_intel_encoder->base;
+
+ drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
+ drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+
+ if (type == DRM_MODE_CONNECTOR_DisplayPort)
+ psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+@@ -1864,7 +1864,7 @@ cdv_intel_dp_init(struct drm_device *dev
+
+ cdv_disable_intel_clock_gating(dev);
+
+- cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
++ cdv_intel_dp_i2c_init(gma_connector, psb_intel_encoder, name);
+ /* FIXME:fail check */
+ cdv_intel_dp_add_properties(connector);
+
+@@ -1947,7 +1947,7 @@ cdv_intel_dp_init(struct drm_device *dev
+ return;
+
+ err_priv:
+- kfree(psb_intel_connector);
++ kfree(gma_connector);
+ err_connector:
+ kfree(psb_intel_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
+@@ -295,7 +295,7 @@ void cdv_hdmi_init(struct drm_device *de
+ struct psb_intel_mode_device *mode_dev, int reg)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct mid_intel_hdmi_priv *hdmi_priv;
+@@ -307,10 +307,10 @@ void cdv_hdmi_init(struct drm_device *de
+ if (!psb_intel_encoder)
+ return;
+
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector),
++ gma_connector = kzalloc(sizeof(struct gma_connector),
+ GFP_KERNEL);
+
+- if (!psb_intel_connector)
++ if (!gma_connector)
+ goto err_connector;
+
+ hdmi_priv = kzalloc(sizeof(struct mid_intel_hdmi_priv), GFP_KERNEL);
+@@ -318,7 +318,7 @@ void cdv_hdmi_init(struct drm_device *de
+ if (!hdmi_priv)
+ goto err_priv;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+ encoder = &psb_intel_encoder->base;
+ drm_connector_init(dev, connector,
+@@ -328,7 +328,7 @@ void cdv_hdmi_init(struct drm_device *de
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
+ hdmi_priv->hdmi_reg = reg;
+ hdmi_priv->has_hdmi_sink = false;
+@@ -378,7 +378,7 @@ failed_ddc:
+ drm_encoder_cleanup(encoder);
+ drm_connector_cleanup(connector);
+ err_priv:
+- kfree(psb_intel_connector);
++ kfree(gma_connector);
+ err_connector:
+ kfree(psb_intel_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
+@@ -611,7 +611,7 @@ void cdv_intel_lvds_init(struct drm_devi
+ struct psb_intel_mode_device *mode_dev)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct cdv_intel_lvds_priv *lvds_priv;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+@@ -633,9 +633,9 @@ void cdv_intel_lvds_init(struct drm_devi
+ if (!psb_intel_encoder)
+ return;
+
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector),
++ gma_connector = kzalloc(sizeof(struct gma_connector),
+ GFP_KERNEL);
+- if (!psb_intel_connector)
++ if (!gma_connector)
+ goto failed_connector;
+
+ lvds_priv = kzalloc(sizeof(struct cdv_intel_lvds_priv), GFP_KERNEL);
+@@ -644,7 +644,7 @@ void cdv_intel_lvds_init(struct drm_devi
+
+ psb_intel_encoder->dev_priv = lvds_priv;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ encoder = &psb_intel_encoder->base;
+
+
+@@ -657,7 +657,7 @@ void cdv_intel_lvds_init(struct drm_devi
+ DRM_MODE_ENCODER_LVDS);
+
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs);
+@@ -791,7 +791,7 @@ failed_blc_i2c:
+ drm_connector_cleanup(connector);
+ kfree(lvds_priv);
+ failed_lvds_priv:
+- kfree(psb_intel_connector);
++ kfree(gma_connector);
+ failed_connector:
+ kfree(psb_intel_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/framebuffer.c
++++ b/drivers/gpu/drm/gma500/framebuffer.c
+@@ -744,7 +744,7 @@ static void psb_setup_outputs(struct drm
+ }
+ encoder->possible_crtcs = crtc_mask;
+ encoder->possible_clones =
+- psb_intel_connector_clones(dev, clone_mask);
++ gma_connector_clones(dev, clone_mask);
+ }
+ }
+
+--- a/drivers/gpu/drm/gma500/framebuffer.h
++++ b/drivers/gpu/drm/gma500/framebuffer.h
+@@ -41,7 +41,7 @@ struct psb_fbdev {
+
+ #define to_psb_fb(x) container_of(x, struct psb_framebuffer, base)
+
+-extern int psb_intel_connector_clones(struct drm_device *dev, int type_mask);
++extern int gma_connector_clones(struct drm_device *dev, int type_mask);
+
+ #endif
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -672,7 +672,7 @@ struct drm_encoder *gma_best_encoder(str
+ return &psb_intel_encoder->base;
+ }
+
+-void gma_connector_attach_encoder(struct psb_intel_connector *connector,
++void gma_connector_attach_encoder(struct gma_connector *connector,
+ struct psb_intel_encoder *encoder)
+ {
+ connector->encoder = encoder;
+--- a/drivers/gpu/drm/gma500/mdfld_dsi_output.h
++++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h
+@@ -227,7 +227,7 @@ enum {
+ #define DSI_DPI_DISABLE_BTA BIT(3)
+
+ struct mdfld_dsi_connector {
+- struct psb_intel_connector base;
++ struct gma_connector base;
+
+ int pipe;
+ void *private;
+@@ -269,11 +269,11 @@ struct mdfld_dsi_config {
+ static inline struct mdfld_dsi_connector *mdfld_dsi_connector(
+ struct drm_connector *connector)
+ {
+- struct psb_intel_connector *psb_connector;
++ struct gma_connector *gma_connector;
+
+- psb_connector = to_psb_intel_connector(connector);
++ gma_connector = to_gma_connector(connector);
+
+- return container_of(psb_connector, struct mdfld_dsi_connector, base);
++ return container_of(gma_connector, struct mdfld_dsi_connector, base);
+ }
+
+ static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder(
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -641,7 +641,7 @@ void oaktrail_hdmi_init(struct drm_devic
+ struct psb_intel_mode_device *mode_dev)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+
+@@ -649,11 +649,11 @@ void oaktrail_hdmi_init(struct drm_devic
+ if (!psb_intel_encoder)
+ return;
+
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+- if (!psb_intel_connector)
++ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
++ if (!gma_connector)
+ goto failed_connector;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ encoder = &psb_intel_encoder->base;
+ drm_connector_init(dev, connector,
+ &oaktrail_hdmi_connector_funcs,
+@@ -663,7 +663,7 @@ void oaktrail_hdmi_init(struct drm_devic
+ &oaktrail_hdmi_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+
+ psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
+ drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
+--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
++++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
+@@ -326,7 +326,7 @@ void oaktrail_lvds_init(struct drm_devic
+ struct psb_intel_mode_device *mode_dev)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+@@ -338,11 +338,11 @@ void oaktrail_lvds_init(struct drm_devic
+ if (!psb_intel_encoder)
+ return;
+
+- psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+- if (!psb_intel_connector)
++ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
++ if (!gma_connector)
+ goto failed_connector;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ encoder = &psb_intel_encoder->base;
+ dev_priv->is_lvds_on = true;
+ drm_connector_init(dev, connector,
+@@ -352,7 +352,7 @@ void oaktrail_lvds_init(struct drm_devic
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
+@@ -440,7 +440,7 @@ failed_find:
+
+ drm_encoder_cleanup(encoder);
+ drm_connector_cleanup(connector);
+- kfree(psb_intel_connector);
++ kfree(gma_connector);
+ failed_connector:
+ kfree(psb_intel_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -594,7 +594,7 @@ struct drm_crtc *psb_intel_get_crtc_from
+ return crtc;
+ }
+
+-int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
++int gma_connector_clones(struct drm_device *dev, int type_mask)
+ {
+ int index_mask = 0;
+ struct drm_connector *connector;
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -137,7 +137,7 @@ struct psb_intel_encoder {
+ struct psb_intel_i2c_chan *ddc_bus;
+ };
+
+-struct psb_intel_connector {
++struct gma_connector {
+ struct drm_connector base;
+ struct psb_intel_encoder *encoder;
+ };
+@@ -195,8 +195,8 @@ struct gma_crtc {
+
+ #define to_gma_crtc(x) \
+ container_of(x, struct gma_crtc, base)
+-#define to_psb_intel_connector(x) \
+- container_of(x, struct psb_intel_connector, base)
++#define to_gma_connector(x) \
++ container_of(x, struct gma_connector, base)
+ #define to_psb_intel_encoder(x) \
+ container_of(x, struct psb_intel_encoder, base)
+ #define to_psb_intel_framebuffer(x) \
+@@ -227,13 +227,13 @@ extern void mid_dsi_init(struct drm_devi
+ struct psb_intel_mode_device *mode_dev, int dsi_num);
+
+ extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector);
+-extern void gma_connector_attach_encoder(struct psb_intel_connector *connector,
++extern void gma_connector_attach_encoder(struct gma_connector *connector,
+ struct psb_intel_encoder *encoder);
+
+ static inline struct psb_intel_encoder *gma_attached_encoder(
+ struct drm_connector *connector)
+ {
+- return to_psb_intel_connector(connector)->encoder;
++ return to_gma_connector(connector)->encoder;
+ }
+
+ extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
+--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
+@@ -690,7 +690,7 @@ void psb_intel_lvds_init(struct drm_devi
+ struct psb_intel_mode_device *mode_dev)
+ {
+ struct psb_intel_encoder *psb_intel_encoder;
+- struct psb_intel_connector *psb_intel_connector;
++ struct gma_connector *gma_connector;
+ struct psb_intel_lvds_priv *lvds_priv;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+@@ -707,10 +707,9 @@ void psb_intel_lvds_init(struct drm_devi
+ return;
+ }
+
+- psb_intel_connector =
+- kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
+- if (!psb_intel_connector) {
+- dev_err(dev->dev, "psb_intel_connector allocation error\n");
++ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
++ if (!gma_connector) {
++ dev_err(dev->dev, "gma_connector allocation error\n");
+ goto failed_encoder;
+ }
+
+@@ -722,7 +721,7 @@ void psb_intel_lvds_init(struct drm_devi
+
+ psb_intel_encoder->dev_priv = lvds_priv;
+
+- connector = &psb_intel_connector->base;
++ connector = &gma_connector->base;
+ encoder = &psb_intel_encoder->base;
+ drm_connector_init(dev, connector,
+ &psb_intel_lvds_connector_funcs,
+@@ -732,7 +731,7 @@ void psb_intel_lvds_init(struct drm_devi
+ &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- gma_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+ psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs);
+@@ -848,7 +847,7 @@ failed_blc_i2c:
+ drm_encoder_cleanup(encoder);
+ drm_connector_cleanup(connector);
+ failed_connector:
+- kfree(psb_intel_connector);
++ kfree(gma_connector);
+ failed_encoder:
+ kfree(psb_intel_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -140,7 +140,7 @@ struct psb_intel_sdvo {
+ };
+
+ struct psb_intel_sdvo_connector {
+- struct psb_intel_connector base;
++ struct gma_connector base;
+
+ /* Mark the type of connector */
+ uint16_t output_flag;
+@@ -206,7 +206,7 @@ static struct psb_intel_sdvo *intel_atta
+
+ static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
+ {
+- return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base);
++ return container_of(to_gma_connector(connector), struct psb_intel_sdvo_connector, base);
+ }
+
+ static bool
+@@ -2074,7 +2074,7 @@ psb_intel_sdvo_dvi_init(struct psb_intel
+ {
+ struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
+ struct drm_connector *connector;
+- struct psb_intel_connector *intel_connector;
++ struct gma_connector *intel_connector;
+ struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
+
+ psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
+@@ -2114,7 +2114,7 @@ psb_intel_sdvo_tv_init(struct psb_intel_
+ {
+ struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
+ struct drm_connector *connector;
+- struct psb_intel_connector *intel_connector;
++ struct gma_connector *intel_connector;
+ struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
+
+ psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
+@@ -2153,7 +2153,7 @@ psb_intel_sdvo_analog_init(struct psb_in
+ {
+ struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
+ struct drm_connector *connector;
+- struct psb_intel_connector *intel_connector;
++ struct gma_connector *intel_connector;
+ struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
+
+ psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
+@@ -2187,7 +2187,7 @@ psb_intel_sdvo_lvds_init(struct psb_inte
+ {
+ struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
+ struct drm_connector *connector;
+- struct psb_intel_connector *intel_connector;
++ struct gma_connector *intel_connector;
+ struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
+
+ psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
--- /dev/null
+From 3113ad31b81b38d96614faaf3e6618ba01840f37 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 22 Jul 2013 17:45:26 +0200
+Subject: drm/gma500: Rename psb_intel_encoder to gma_encoder
+
+The psb_intel_encoder is generic and should be named appropriately
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 367e44080e20f77fa7b0f2db83fd6367da59b6c3)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_intel_crt.c | 31 +++---
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 10 +-
+ drivers/gpu/drm/gma500/cdv_intel_dp.c | 130 +++++++++++++--------------
+ drivers/gpu/drm/gma500/cdv_intel_hdmi.c | 66 ++++++-------
+ drivers/gpu/drm/gma500/cdv_intel_lvds.c | 50 ++++------
+ drivers/gpu/drm/gma500/framebuffer.c | 7 -
+ drivers/gpu/drm/gma500/gma_display.c | 13 +-
+ drivers/gpu/drm/gma500/mdfld_dsi_output.h | 8 -
+ drivers/gpu/drm/gma500/mdfld_intel_display.c | 8 -
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 8 -
+ drivers/gpu/drm/gma500/oaktrail_hdmi.c | 14 +-
+ drivers/gpu/drm/gma500/oaktrail_lvds.c | 37 +++----
+ drivers/gpu/drm/gma500/psb_drv.c | 6 -
+ drivers/gpu/drm/gma500/psb_intel_display.c | 10 --
+ drivers/gpu/drm/gma500/psb_intel_drv.h | 14 +-
+ drivers/gpu/drm/gma500/psb_intel_lvds.c | 49 ++++------
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 20 +---
+ 17 files changed, 226 insertions(+), 255 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_intel_crt.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c
+@@ -196,10 +196,9 @@ static enum drm_connector_status cdv_int
+
+ static void cdv_intel_crt_destroy(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+
+- psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus);
++ psb_intel_i2c_destroy(gma_encoder->ddc_bus);
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+@@ -207,9 +206,9 @@ static void cdv_intel_crt_destroy(struct
+
+ static int cdv_intel_crt_get_modes(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- return psb_intel_ddc_get_modes(connector, &psb_intel_encoder->ddc_bus->adapter);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ return psb_intel_ddc_get_modes(connector,
++ &gma_encoder->ddc_bus->adapter);
+ }
+
+ static int cdv_intel_crt_set_property(struct drm_connector *connector,
+@@ -260,14 +259,14 @@ void cdv_intel_crt_init(struct drm_devic
+ {
+
+ struct gma_connector *gma_connector;
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+
+ u32 i2c_reg;
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+- if (!psb_intel_encoder)
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
++ if (!gma_encoder)
+ return;
+
+ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
+@@ -279,11 +278,11 @@ void cdv_intel_crt_init(struct drm_devic
+ drm_connector_init(dev, connector,
+ &cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
+
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+ drm_encoder_init(dev, encoder,
+ &cdv_intel_crt_enc_funcs, DRM_MODE_ENCODER_DAC);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
+
+ /* Set up the DDC bus. */
+ i2c_reg = GPIOA;
+@@ -292,15 +291,15 @@ void cdv_intel_crt_init(struct drm_devic
+ if (dev_priv->crt_ddc_bus != 0)
+ i2c_reg = dev_priv->crt_ddc_bus;
+ }*/
+- psb_intel_encoder->ddc_bus = psb_intel_i2c_create(dev,
++ gma_encoder->ddc_bus = psb_intel_i2c_create(dev,
+ i2c_reg, "CRTDDC_A");
+- if (!psb_intel_encoder->ddc_bus) {
++ if (!gma_encoder->ddc_bus) {
+ dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
+ "failed.\n");
+ goto failed_ddc;
+ }
+
+- psb_intel_encoder->type = INTEL_OUTPUT_ANALOG;
++ gma_encoder->type = INTEL_OUTPUT_ANALOG;
+ /*
+ psb_intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT);
+ psb_intel_output->crtc_mask = (1 << 0) | (1 << 1);
+@@ -316,10 +315,10 @@ void cdv_intel_crt_init(struct drm_devic
+
+ return;
+ failed_ddc:
+- drm_encoder_cleanup(&psb_intel_encoder->base);
++ drm_encoder_cleanup(&gma_encoder->base);
+ drm_connector_cleanup(&gma_connector->base);
+ kfree(gma_connector);
+ failed_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ return;
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -497,14 +497,14 @@ static bool is_pipeb_lvds(struct drm_dev
+ return false;
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+- struct psb_intel_encoder *psb_intel_encoder =
++ struct gma_encoder *gma_encoder =
+ gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+ continue;
+
+- if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
++ if (gma_encoder->type == INTEL_OUTPUT_LVDS)
+ return true;
+ }
+
+@@ -632,15 +632,15 @@ static int cdv_intel_crtc_mode_set(struc
+ bool is_edp = false;
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+- struct psb_intel_encoder *psb_intel_encoder =
++ struct gma_encoder *gma_encoder =
+ gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+ continue;
+
+- ddi_select = psb_intel_encoder->ddi_select;
+- switch (psb_intel_encoder->type) {
++ ddi_select = gma_encoder->ddi_select;
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ is_lvds = true;
+ break;
+--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
+@@ -69,7 +69,7 @@ struct cdv_intel_dp {
+ uint8_t link_bw;
+ uint8_t lane_count;
+ uint8_t dpcd[4];
+- struct psb_intel_encoder *encoder;
++ struct gma_encoder *encoder;
+ struct i2c_adapter adapter;
+ struct i2c_algo_dp_aux_data algo;
+ uint8_t train_set[4];
+@@ -115,18 +115,18 @@ static uint32_t dp_vswing_premph_table[]
+ * If a CPU or PCH DP output is attached to an eDP panel, this function
+ * will return true, and false otherwise.
+ */
+-static bool is_edp(struct psb_intel_encoder *encoder)
++static bool is_edp(struct gma_encoder *encoder)
+ {
+ return encoder->type == INTEL_OUTPUT_EDP;
+ }
+
+
+-static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
+-static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
+-static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
++static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder);
++static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder);
++static void cdv_intel_dp_link_down(struct gma_encoder *encoder);
+
+ static int
+-cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
++cdv_intel_dp_max_lane_count(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_lane_count = 4;
+@@ -144,7 +144,7 @@ cdv_intel_dp_max_lane_count(struct psb_i
+ }
+
+ static int
+-cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
++cdv_intel_dp_max_link_bw(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
+@@ -181,7 +181,7 @@ cdv_intel_dp_max_data_rate(int max_link_
+ return (max_link_clock * max_lanes * 19) / 20;
+ }
+
+-static void cdv_intel_edp_panel_vdd_on(struct psb_intel_encoder *intel_encoder)
++static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+@@ -201,7 +201,7 @@ static void cdv_intel_edp_panel_vdd_on(s
+ msleep(intel_dp->panel_power_up_delay);
+ }
+
+-static void cdv_intel_edp_panel_vdd_off(struct psb_intel_encoder *intel_encoder)
++static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp;
+@@ -216,7 +216,7 @@ static void cdv_intel_edp_panel_vdd_off(
+ }
+
+ /* Returns true if the panel was already on when called */
+-static bool cdv_intel_edp_panel_on(struct psb_intel_encoder *intel_encoder)
++static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+@@ -243,7 +243,7 @@ static bool cdv_intel_edp_panel_on(struc
+ return false;
+ }
+
+-static void cdv_intel_edp_panel_off (struct psb_intel_encoder *intel_encoder)
++static void cdv_intel_edp_panel_off (struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp, idle_off_mask = PP_ON ;
+@@ -275,7 +275,7 @@ static void cdv_intel_edp_panel_off (str
+ DRM_DEBUG_KMS("Over\n");
+ }
+
+-static void cdv_intel_edp_backlight_on (struct psb_intel_encoder *intel_encoder)
++static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ u32 pp;
+@@ -295,7 +295,7 @@ static void cdv_intel_edp_backlight_on (
+ gma_backlight_enable(dev);
+ }
+
+-static void cdv_intel_edp_backlight_off (struct psb_intel_encoder *intel_encoder)
++static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder)
+ {
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+@@ -315,7 +315,7 @@ static int
+ cdv_intel_dp_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+ {
+- struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
++ struct gma_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
+ int max_lanes = cdv_intel_dp_max_lane_count(encoder);
+@@ -371,7 +371,7 @@ unpack_aux(uint32_t src, uint8_t *dst, i
+ }
+
+ static int
+-cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
++cdv_intel_dp_aux_ch(struct gma_encoder *encoder,
+ uint8_t *send, int send_bytes,
+ uint8_t *recv, int recv_size)
+ {
+@@ -473,7 +473,7 @@ cdv_intel_dp_aux_ch(struct psb_intel_enc
+
+ /* Write data to the aux channel in native mode */
+ static int
+-cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
++cdv_intel_dp_aux_native_write(struct gma_encoder *encoder,
+ uint16_t address, uint8_t *send, int send_bytes)
+ {
+ int ret;
+@@ -505,7 +505,7 @@ cdv_intel_dp_aux_native_write(struct psb
+
+ /* Write a single byte to the aux channel in native mode */
+ static int
+-cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
++cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder,
+ uint16_t address, uint8_t byte)
+ {
+ return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
+@@ -513,7 +513,7 @@ cdv_intel_dp_aux_native_write_1(struct p
+
+ /* read bytes from a native aux channel */
+ static int
+-cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
++cdv_intel_dp_aux_native_read(struct gma_encoder *encoder,
+ uint16_t address, uint8_t *recv, int recv_bytes)
+ {
+ uint8_t msg[4];
+@@ -558,7 +558,7 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapt
+ struct cdv_intel_dp *intel_dp = container_of(adapter,
+ struct cdv_intel_dp,
+ adapter);
+- struct psb_intel_encoder *encoder = intel_dp->encoder;
++ struct gma_encoder *encoder = intel_dp->encoder;
+ uint16_t address = algo_data->address;
+ uint8_t msg[5];
+ uint8_t reply[2];
+@@ -648,7 +648,8 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapt
+ }
+
+ static int
+-cdv_intel_dp_i2c_init(struct gma_connector *connector, struct psb_intel_encoder *encoder, const char *name)
++cdv_intel_dp_i2c_init(struct gma_connector *connector,
++ struct gma_encoder *encoder, const char *name)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+@@ -699,7 +700,7 @@ cdv_intel_dp_mode_fixup(struct drm_encod
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct drm_psb_private *dev_priv = encoder->dev->dev_private;
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ int lane_count, clock;
+ int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
+@@ -802,13 +803,13 @@ cdv_intel_dp_set_m_n(struct drm_crtc *cr
+ * Find the lane count in the intel_encoder private
+ */
+ list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+- struct psb_intel_encoder *intel_encoder;
++ struct gma_encoder *intel_encoder;
+ struct cdv_intel_dp *intel_dp;
+
+ if (encoder->crtc != crtc)
+ continue;
+
+- intel_encoder = to_psb_intel_encoder(encoder);
++ intel_encoder = to_gma_encoder(encoder);
+ intel_dp = intel_encoder->dev_priv;
+ if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
+ lane_count = intel_dp->lane_count;
+@@ -842,7 +843,7 @@ static void
+ cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+ {
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
+ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+@@ -909,7 +910,7 @@ cdv_intel_dp_mode_set(struct drm_encoder
+
+
+ /* If the sink supports it, try to set the power state appropriately */
+-static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
++static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder, int mode)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret, i;
+@@ -941,7 +942,7 @@ static void cdv_intel_dp_sink_dpms(struc
+
+ static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
+ {
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+ int edp = is_edp(intel_encoder);
+
+ if (edp) {
+@@ -958,7 +959,7 @@ static void cdv_intel_dp_prepare(struct
+
+ static void cdv_intel_dp_commit(struct drm_encoder *encoder)
+ {
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+ int edp = is_edp(intel_encoder);
+
+ if (edp)
+@@ -972,7 +973,7 @@ static void cdv_intel_dp_commit(struct d
+ static void
+ cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
+ {
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct drm_device *dev = encoder->dev;
+ uint32_t dp_reg = REG_READ(intel_dp->output_reg);
+@@ -1007,7 +1008,7 @@ cdv_intel_dp_dpms(struct drm_encoder *en
+ * cases where the sink may still be asleep.
+ */
+ static bool
+-cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
++cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address,
+ uint8_t *recv, int recv_bytes)
+ {
+ int ret, i;
+@@ -1032,7 +1033,7 @@ cdv_intel_dp_aux_native_read_retry(struc
+ * link status information
+ */
+ static bool
+-cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
++cdv_intel_dp_get_link_status(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ return cdv_intel_dp_aux_native_read_retry(encoder,
+@@ -1106,7 +1107,7 @@ cdv_intel_dp_pre_emphasis_max(uint8_t vo
+ }
+ */
+ static void
+-cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
++cdv_intel_get_adjust_train(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint8_t v = 0;
+@@ -1165,7 +1166,7 @@ cdv_intel_clock_recovery_ok(uint8_t link
+ DP_LANE_CHANNEL_EQ_DONE|\
+ DP_LANE_SYMBOL_LOCKED)
+ static bool
+-cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
++cdv_intel_channel_eq_ok(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ uint8_t lane_align;
+@@ -1185,7 +1186,7 @@ cdv_intel_channel_eq_ok(struct psb_intel
+ }
+
+ static bool
+-cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
++cdv_intel_dp_set_link_train(struct gma_encoder *encoder,
+ uint32_t dp_reg_value,
+ uint8_t dp_train_pat)
+ {
+@@ -1212,7 +1213,7 @@ cdv_intel_dp_set_link_train(struct psb_i
+
+
+ static bool
+-cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
++cdv_intel_dplink_set_level(struct gma_encoder *encoder,
+ uint8_t dp_train_pat)
+ {
+
+@@ -1233,7 +1234,7 @@ cdv_intel_dplink_set_level(struct psb_in
+ }
+
+ static void
+-cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
++cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+@@ -1299,7 +1300,7 @@ cdv_intel_dp_set_vswing_premph(struct ps
+
+ /* Enable corresponding port and start training pattern 1 */
+ static void
+-cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
++cdv_intel_dp_start_link_train(struct gma_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+@@ -1393,7 +1394,7 @@ cdv_intel_dp_start_link_train(struct psb
+ }
+
+ static void
+-cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
++cdv_intel_dp_complete_link_train(struct gma_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+@@ -1479,7 +1480,7 @@ cdv_intel_dp_complete_link_train(struct
+ }
+
+ static void
+-cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
++cdv_intel_dp_link_down(struct gma_encoder *encoder)
+ {
+ struct drm_device *dev = encoder->base.dev;
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+@@ -1503,8 +1504,7 @@ cdv_intel_dp_link_down(struct psb_intel_
+ REG_READ(intel_dp->output_reg);
+ }
+
+-static enum drm_connector_status
+-cdv_dp_detect(struct psb_intel_encoder *encoder)
++static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder)
+ {
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ enum drm_connector_status status;
+@@ -1532,7 +1532,7 @@ cdv_dp_detect(struct psb_intel_encoder *
+ static enum drm_connector_status
+ cdv_intel_dp_detect(struct drm_connector *connector, bool force)
+ {
+- struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
++ struct gma_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ enum drm_connector_status status;
+ struct edid *edid = NULL;
+@@ -1566,8 +1566,7 @@ cdv_intel_dp_detect(struct drm_connector
+
+ static int cdv_intel_dp_get_modes(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *intel_encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
+ struct edid *edid = NULL;
+ int ret = 0;
+@@ -1623,7 +1622,7 @@ static int cdv_intel_dp_get_modes(struct
+ static bool
+ cdv_intel_dp_detect_audio(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
++ struct gma_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ struct edid *edid;
+ bool has_audio = false;
+@@ -1649,7 +1648,7 @@ cdv_intel_dp_set_property(struct drm_con
+ uint64_t val)
+ {
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+- struct psb_intel_encoder *encoder = gma_attached_encoder(connector);
++ struct gma_encoder *encoder = gma_attached_encoder(connector);
+ struct cdv_intel_dp *intel_dp = encoder->dev_priv;
+ int ret;
+
+@@ -1702,11 +1701,10 @@ done:
+ static void
+ cdv_intel_dp_destroy(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;
+
+- if (is_edp(psb_intel_encoder)) {
++ if (is_edp(gma_encoder)) {
+ /* cdv_intel_panel_destroy_backlight(connector->dev); */
+ if (intel_dp->panel_fixed_mode) {
+ kfree(intel_dp->panel_fixed_mode);
+@@ -1802,7 +1800,7 @@ static void cdv_disable_intel_clock_gati
+ void
+ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+@@ -1810,8 +1808,8 @@ cdv_intel_dp_init(struct drm_device *dev
+ const char *name = NULL;
+ int type = DRM_MODE_CONNECTOR_DisplayPort;
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+- if (!psb_intel_encoder)
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
++ if (!gma_encoder)
+ return;
+ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
+ if (!gma_connector)
+@@ -1824,21 +1822,21 @@ cdv_intel_dp_init(struct drm_device *dev
+ type = DRM_MODE_CONNECTOR_eDP;
+
+ connector = &gma_connector->base;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+
+ drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
+ drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
+
+ if (type == DRM_MODE_CONNECTOR_DisplayPort)
+- psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
++ gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
+ else
+- psb_intel_encoder->type = INTEL_OUTPUT_EDP;
++ gma_encoder->type = INTEL_OUTPUT_EDP;
+
+
+- psb_intel_encoder->dev_priv=intel_dp;
+- intel_dp->encoder = psb_intel_encoder;
++ gma_encoder->dev_priv=intel_dp;
++ intel_dp->encoder = gma_encoder;
+ intel_dp->output_reg = output_reg;
+
+ drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
+@@ -1854,21 +1852,21 @@ cdv_intel_dp_init(struct drm_device *dev
+ switch (output_reg) {
+ case DP_B:
+ name = "DPDDC-B";
+- psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
++ gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
+ break;
+ case DP_C:
+ name = "DPDDC-C";
+- psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
++ gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
+ break;
+ }
+
+ cdv_disable_intel_clock_gating(dev);
+
+- cdv_intel_dp_i2c_init(gma_connector, psb_intel_encoder, name);
++ cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name);
+ /* FIXME:fail check */
+ cdv_intel_dp_add_properties(connector);
+
+- if (is_edp(psb_intel_encoder)) {
++ if (is_edp(gma_encoder)) {
+ int ret;
+ struct edp_power_seq cur;
+ u32 pp_on, pp_off, pp_div;
+@@ -1922,11 +1920,11 @@ cdv_intel_dp_init(struct drm_device *dev
+ intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
+
+
+- cdv_intel_edp_panel_vdd_on(psb_intel_encoder);
+- ret = cdv_intel_dp_aux_native_read(psb_intel_encoder, DP_DPCD_REV,
++ cdv_intel_edp_panel_vdd_on(gma_encoder);
++ ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV,
+ intel_dp->dpcd,
+ sizeof(intel_dp->dpcd));
+- cdv_intel_edp_panel_vdd_off(psb_intel_encoder);
++ cdv_intel_edp_panel_vdd_off(gma_encoder);
+ if (ret == 0) {
+ /* if this fails, presume the device is a ghost */
+ DRM_INFO("failed to retrieve link info, disabling eDP\n");
+@@ -1949,5 +1947,5 @@ cdv_intel_dp_init(struct drm_device *dev
+ err_priv:
+ kfree(gma_connector);
+ err_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c
+@@ -64,8 +64,8 @@ static void cdv_hdmi_mode_set(struct drm
+ struct drm_display_mode *adjusted_mode)
+ {
+ struct drm_device *dev = encoder->dev;
+- struct psb_intel_encoder *psb_intel_encoder = to_psb_intel_encoder(encoder);
+- struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
++ struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
+ u32 hdmib;
+ struct drm_crtc *crtc = encoder->crtc;
+ struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
+@@ -99,9 +99,8 @@ static bool cdv_hdmi_mode_fixup(struct d
+ static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode)
+ {
+ struct drm_device *dev = encoder->dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- to_psb_intel_encoder(encoder);
+- struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
++ struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
+ u32 hdmib;
+
+ hdmib = REG_READ(hdmi_priv->hdmi_reg);
+@@ -116,9 +115,8 @@ static void cdv_hdmi_dpms(struct drm_enc
+ static void cdv_hdmi_save(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
+
+ hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg);
+ }
+@@ -126,9 +124,8 @@ static void cdv_hdmi_save(struct drm_con
+ static void cdv_hdmi_restore(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
+
+ REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB);
+ REG_READ(hdmi_priv->hdmi_reg);
+@@ -137,13 +134,12 @@ static void cdv_hdmi_restore(struct drm_
+ static enum drm_connector_status cdv_hdmi_detect(
+ struct drm_connector *connector, bool force)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct mid_intel_hdmi_priv *hdmi_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
+ struct edid *edid = NULL;
+ enum drm_connector_status status = connector_status_disconnected;
+
+- edid = drm_get_edid(connector, &psb_intel_encoder->i2c_bus->adapter);
++ edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter);
+
+ hdmi_priv->has_hdmi_sink = false;
+ hdmi_priv->has_hdmi_audio = false;
+@@ -221,12 +217,11 @@ static int cdv_hdmi_set_property(struct
+ */
+ static int cdv_hdmi_get_modes(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+ struct edid *edid = NULL;
+ int ret = 0;
+
+- edid = drm_get_edid(connector, &psb_intel_encoder->i2c_bus->adapter);
++ edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter);
+ if (edid) {
+ drm_mode_connector_update_edid_property(connector, edid);
+ ret = drm_add_edid_modes(connector, edid);
+@@ -256,11 +251,10 @@ static int cdv_hdmi_mode_valid(struct dr
+
+ static void cdv_hdmi_destroy(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+
+- if (psb_intel_encoder->i2c_bus)
+- psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus);
++ if (gma_encoder->i2c_bus)
++ psb_intel_i2c_destroy(gma_encoder->i2c_bus);
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+@@ -294,17 +288,16 @@ static const struct drm_connector_funcs
+ void cdv_hdmi_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev, int reg)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct mid_intel_hdmi_priv *hdmi_priv;
+ int ddc_bus;
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder),
+- GFP_KERNEL);
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
+
+- if (!psb_intel_encoder)
++ if (!gma_encoder)
+ return;
+
+ gma_connector = kzalloc(sizeof(struct gma_connector),
+@@ -320,7 +313,7 @@ void cdv_hdmi_init(struct drm_device *de
+
+ connector = &gma_connector->base;
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+ drm_connector_init(dev, connector,
+ &cdv_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_DVID);
+@@ -328,11 +321,11 @@ void cdv_hdmi_init(struct drm_device *de
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+- psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
++ gma_encoder->type = INTEL_OUTPUT_HDMI;
+ hdmi_priv->hdmi_reg = reg;
+ hdmi_priv->has_hdmi_sink = false;
+- psb_intel_encoder->dev_priv = hdmi_priv;
++ gma_encoder->dev_priv = hdmi_priv;
+
+ drm_encoder_helper_add(encoder, &cdv_hdmi_helper_funcs);
+ drm_connector_helper_add(connector,
+@@ -348,11 +341,11 @@ void cdv_hdmi_init(struct drm_device *de
+ switch (reg) {
+ case SDVOB:
+ ddc_bus = GPIOE;
+- psb_intel_encoder->ddi_select = DDI0_SELECT;
++ gma_encoder->ddi_select = DDI0_SELECT;
+ break;
+ case SDVOC:
+ ddc_bus = GPIOD;
+- psb_intel_encoder->ddi_select = DDI1_SELECT;
++ gma_encoder->ddi_select = DDI1_SELECT;
+ break;
+ default:
+ DRM_ERROR("unknown reg 0x%x for HDMI\n", reg);
+@@ -360,16 +353,15 @@ void cdv_hdmi_init(struct drm_device *de
+ break;
+ }
+
+- psb_intel_encoder->i2c_bus = psb_intel_i2c_create(dev,
++ gma_encoder->i2c_bus = psb_intel_i2c_create(dev,
+ ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC");
+
+- if (!psb_intel_encoder->i2c_bus) {
++ if (!gma_encoder->i2c_bus) {
+ dev_err(dev->dev, "No ddc adapter available!\n");
+ goto failed_ddc;
+ }
+
+- hdmi_priv->hdmi_i2c_adapter =
+- &(psb_intel_encoder->i2c_bus->adapter);
++ hdmi_priv->hdmi_i2c_adapter = &(gma_encoder->i2c_bus->adapter);
+ hdmi_priv->dev = dev;
+ drm_sysfs_connector_add(connector);
+ return;
+@@ -380,5 +372,5 @@ failed_ddc:
+ err_priv:
+ kfree(gma_connector);
+ err_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/cdv_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c
+@@ -406,12 +406,11 @@ static int cdv_intel_lvds_get_modes(stru
+ {
+ struct drm_device *dev = connector->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+ int ret;
+
+- ret = psb_intel_ddc_get_modes(connector, &psb_intel_encoder->i2c_bus->adapter);
++ ret = psb_intel_ddc_get_modes(connector, &gma_encoder->i2c_bus->adapter);
+
+ if (ret)
+ return ret;
+@@ -443,11 +442,10 @@ static int cdv_intel_lvds_get_modes(stru
+ */
+ static void cdv_intel_lvds_destroy(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+
+- if (psb_intel_encoder->i2c_bus)
+- psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus);
++ if (gma_encoder->i2c_bus)
++ psb_intel_i2c_destroy(gma_encoder->i2c_bus);
+ drm_sysfs_connector_remove(connector);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+@@ -610,7 +608,7 @@ static bool lvds_is_present_in_vbt(struc
+ void cdv_intel_lvds_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct cdv_intel_lvds_priv *lvds_priv;
+ struct drm_connector *connector;
+@@ -628,9 +626,9 @@ void cdv_intel_lvds_init(struct drm_devi
+ return;
+ }
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder),
++ gma_encoder = kzalloc(sizeof(struct gma_encoder),
+ GFP_KERNEL);
+- if (!psb_intel_encoder)
++ if (!gma_encoder)
+ return;
+
+ gma_connector = kzalloc(sizeof(struct gma_connector),
+@@ -642,10 +640,10 @@ void cdv_intel_lvds_init(struct drm_devi
+ if (!lvds_priv)
+ goto failed_lvds_priv;
+
+- psb_intel_encoder->dev_priv = lvds_priv;
++ gma_encoder->dev_priv = lvds_priv;
+
+ connector = &gma_connector->base;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+
+
+ drm_connector_init(dev, connector,
+@@ -657,8 +655,8 @@ void cdv_intel_lvds_init(struct drm_devi
+ DRM_MODE_ENCODER_LVDS);
+
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+- psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
++ gma_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &cdv_intel_lvds_helper_funcs);
+ drm_connector_helper_add(connector,
+@@ -679,16 +677,16 @@ void cdv_intel_lvds_init(struct drm_devi
+ * Set up I2C bus
+ * FIXME: distroy i2c_bus when exit
+ */
+- psb_intel_encoder->i2c_bus = psb_intel_i2c_create(dev,
++ gma_encoder->i2c_bus = psb_intel_i2c_create(dev,
+ GPIOB,
+ "LVDSBLC_B");
+- if (!psb_intel_encoder->i2c_bus) {
++ if (!gma_encoder->i2c_bus) {
+ dev_printk(KERN_ERR,
+ &dev->pdev->dev, "I2C bus registration failed.\n");
+ goto failed_blc_i2c;
+ }
+- psb_intel_encoder->i2c_bus->slave_addr = 0x2C;
+- dev_priv->lvds_i2c_bus = psb_intel_encoder->i2c_bus;
++ gma_encoder->i2c_bus->slave_addr = 0x2C;
++ dev_priv->lvds_i2c_bus = gma_encoder->i2c_bus;
+
+ /*
+ * LVDS discovery:
+@@ -701,10 +699,10 @@ void cdv_intel_lvds_init(struct drm_devi
+ */
+
+ /* Set up the DDC bus. */
+- psb_intel_encoder->ddc_bus = psb_intel_i2c_create(dev,
++ gma_encoder->ddc_bus = psb_intel_i2c_create(dev,
+ GPIOC,
+ "LVDSDDC_C");
+- if (!psb_intel_encoder->ddc_bus) {
++ if (!gma_encoder->ddc_bus) {
+ dev_printk(KERN_ERR, &dev->pdev->dev,
+ "DDC bus registration " "failed.\n");
+ goto failed_ddc;
+@@ -715,7 +713,7 @@ void cdv_intel_lvds_init(struct drm_devi
+ * preferred mode is the right one.
+ */
+ psb_intel_ddc_get_modes(connector,
+- &psb_intel_encoder->ddc_bus->adapter);
++ &gma_encoder->ddc_bus->adapter);
+ list_for_each_entry(scan, &connector->probed_modes, head) {
+ if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+ mode_dev->panel_fixed_mode =
+@@ -779,12 +777,12 @@ out:
+
+ failed_find:
+ printk(KERN_ERR "Failed find\n");
+- if (psb_intel_encoder->ddc_bus)
+- psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus);
++ if (gma_encoder->ddc_bus)
++ psb_intel_i2c_destroy(gma_encoder->ddc_bus);
+ failed_ddc:
+ printk(KERN_ERR "Failed DDC\n");
+- if (psb_intel_encoder->i2c_bus)
+- psb_intel_i2c_destroy(psb_intel_encoder->i2c_bus);
++ if (gma_encoder->i2c_bus)
++ psb_intel_i2c_destroy(gma_encoder->i2c_bus);
+ failed_blc_i2c:
+ printk(KERN_ERR "Failed BLC\n");
+ drm_encoder_cleanup(encoder);
+@@ -793,5 +791,5 @@ failed_blc_i2c:
+ failed_lvds_priv:
+ kfree(gma_connector);
+ failed_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+--- a/drivers/gpu/drm/gma500/framebuffer.c
++++ b/drivers/gpu/drm/gma500/framebuffer.c
+@@ -703,13 +703,12 @@ static void psb_setup_outputs(struct drm
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct drm_encoder *encoder = &psb_intel_encoder->base;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct drm_encoder *encoder = &gma_encoder->base;
+ int crtc_mask = 0, clone_mask = 0;
+
+ /* valid crtcs */
+- switch (psb_intel_encoder->type) {
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_ANALOG:
+ crtc_mask = (1 << 0);
+ clone_mask = (1 << INTEL_OUTPUT_ANALOG);
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -37,9 +37,9 @@ bool gma_pipe_has_type(struct drm_crtc *
+
+ list_for_each_entry(l_entry, &mode_config->connector_list, head) {
+ if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
+- struct psb_intel_encoder *psb_intel_encoder =
++ struct gma_encoder *gma_encoder =
+ gma_attached_encoder(l_entry);
+- if (psb_intel_encoder->type == type)
++ if (gma_encoder->type == type)
+ return true;
+ }
+ }
+@@ -657,7 +657,7 @@ void gma_encoder_commit(struct drm_encod
+
+ void gma_encoder_destroy(struct drm_encoder *encoder)
+ {
+- struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
++ struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
+
+ drm_encoder_cleanup(encoder);
+ kfree(intel_encoder);
+@@ -666,14 +666,13 @@ void gma_encoder_destroy(struct drm_enco
+ /* Currently there is only a 1:1 mapping of encoders and connectors */
+ struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+
+- return &psb_intel_encoder->base;
++ return &gma_encoder->base;
+ }
+
+ void gma_connector_attach_encoder(struct gma_connector *connector,
+- struct psb_intel_encoder *encoder)
++ struct gma_encoder *encoder)
+ {
+ connector->encoder = encoder;
+ drm_mode_connector_attach_encoder(&connector->base,
+--- a/drivers/gpu/drm/gma500/mdfld_dsi_output.h
++++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h
+@@ -238,7 +238,7 @@ struct mdfld_dsi_connector {
+ };
+
+ struct mdfld_dsi_encoder {
+- struct psb_intel_encoder base;
++ struct gma_encoder base;
+ void *private;
+ };
+
+@@ -279,11 +279,11 @@ static inline struct mdfld_dsi_connector
+ static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder(
+ struct drm_encoder *encoder)
+ {
+- struct psb_intel_encoder *psb_encoder;
++ struct gma_encoder *gma_encoder;
+
+- psb_encoder = to_psb_intel_encoder(encoder);
++ gma_encoder = to_gma_encoder(encoder);
+
+- return container_of(psb_encoder, struct mdfld_dsi_encoder, base);
++ return container_of(gma_encoder, struct mdfld_dsi_encoder, base);
+ }
+
+ static inline struct mdfld_dsi_config *
+--- a/drivers/gpu/drm/gma500/mdfld_intel_display.c
++++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c
+@@ -681,7 +681,7 @@ static int mdfld_crtc_mode_set(struct dr
+ u32 dpll = 0, fp = 0;
+ bool is_mipi = false, is_mipi2 = false, is_hdmi = false;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+- struct psb_intel_encoder *psb_intel_encoder = NULL;
++ struct gma_encoder *gma_encoder = NULL;
+ uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+@@ -747,9 +747,9 @@ static int mdfld_crtc_mode_set(struct dr
+ if (encoder->crtc != crtc)
+ continue;
+
+- psb_intel_encoder = gma_attached_encoder(connector);
++ gma_encoder = gma_attached_encoder(connector);
+
+- switch (psb_intel_encoder->type) {
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_MIPI:
+ is_mipi = true;
+ break;
+@@ -800,7 +800,7 @@ static int mdfld_crtc_mode_set(struct dr
+
+ REG_WRITE(map->pos, 0);
+
+- if (psb_intel_encoder)
++ if (gma_encoder)
+ drm_object_property_get_value(&connector->base,
+ dev->mode_config.scaling_mode_property, &scalingType);
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -303,7 +303,7 @@ static int oaktrail_crtc_mode_set(struct
+ bool is_lvds = false;
+ bool is_mipi = false;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+- struct psb_intel_encoder *psb_intel_encoder = NULL;
++ struct gma_encoder *gma_encoder = NULL;
+ uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
+ struct drm_connector *connector;
+
+@@ -324,9 +324,9 @@ static int oaktrail_crtc_mode_set(struct
+ if (!connector->encoder || connector->encoder->crtc != crtc)
+ continue;
+
+- psb_intel_encoder = gma_attached_encoder(connector);
++ gma_encoder = gma_attached_encoder(connector);
+
+- switch (psb_intel_encoder->type) {
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ is_lvds = true;
+ break;
+@@ -350,7 +350,7 @@ static int oaktrail_crtc_mode_set(struct
+ ((mode->crtc_hdisplay - 1) << 16) |
+ (mode->crtc_vdisplay - 1));
+
+- if (psb_intel_encoder)
++ if (gma_encoder)
+ drm_object_property_get_value(&connector->base,
+ dev->mode_config.scaling_mode_property, &scalingType);
+
+--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
++++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+@@ -640,13 +640,13 @@ static const struct drm_encoder_funcs oa
+ void oaktrail_hdmi_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+- if (!psb_intel_encoder)
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
++ if (!gma_encoder)
+ return;
+
+ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
+@@ -654,7 +654,7 @@ void oaktrail_hdmi_init(struct drm_devic
+ goto failed_connector;
+
+ connector = &gma_connector->base;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+ drm_connector_init(dev, connector,
+ &oaktrail_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_DVID);
+@@ -663,9 +663,9 @@ void oaktrail_hdmi_init(struct drm_devic
+ &oaktrail_hdmi_enc_funcs,
+ DRM_MODE_ENCODER_TMDS);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
+
+- psb_intel_encoder->type = INTEL_OUTPUT_HDMI;
++ gma_encoder->type = INTEL_OUTPUT_HDMI;
+ drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs);
+ drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs);
+
+@@ -678,7 +678,7 @@ void oaktrail_hdmi_init(struct drm_devic
+ return;
+
+ failed_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+
+ static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = {
+--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
++++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
+@@ -43,7 +43,7 @@
+ * Sets the power state for the panel.
+ */
+ static void oaktrail_lvds_set_power(struct drm_device *dev,
+- struct psb_intel_encoder *psb_intel_encoder,
++ struct gma_encoder *gma_encoder,
+ bool on)
+ {
+ u32 pp_status;
+@@ -78,13 +78,12 @@ static void oaktrail_lvds_set_power(stru
+ static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
+ {
+ struct drm_device *dev = encoder->dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- to_psb_intel_encoder(encoder);
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
+
+ if (mode == DRM_MODE_DPMS_ON)
+- oaktrail_lvds_set_power(dev, psb_intel_encoder, true);
++ oaktrail_lvds_set_power(dev, gma_encoder, true);
+ else
+- oaktrail_lvds_set_power(dev, psb_intel_encoder, false);
++ oaktrail_lvds_set_power(dev, gma_encoder, false);
+
+ /* XXX: We never power down the LVDS pairs. */
+ }
+@@ -166,8 +165,7 @@ static void oaktrail_lvds_prepare(struct
+ {
+ struct drm_device *dev = encoder->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder =
+- to_psb_intel_encoder(encoder);
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+
+ if (!gma_power_begin(dev, true))
+@@ -176,7 +174,7 @@ static void oaktrail_lvds_prepare(struct
+ mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
+ mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
+ BACKLIGHT_DUTY_CYCLE_MASK);
+- oaktrail_lvds_set_power(dev, psb_intel_encoder, false);
++ oaktrail_lvds_set_power(dev, gma_encoder, false);
+ gma_power_end(dev);
+ }
+
+@@ -203,14 +201,13 @@ static void oaktrail_lvds_commit(struct
+ {
+ struct drm_device *dev = encoder->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder =
+- to_psb_intel_encoder(encoder);
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+
+ if (mode_dev->backlight_duty_cycle == 0)
+ mode_dev->backlight_duty_cycle =
+ oaktrail_lvds_get_max_backlight(dev);
+- oaktrail_lvds_set_power(dev, psb_intel_encoder, true);
++ oaktrail_lvds_set_power(dev, gma_encoder, true);
+ }
+
+ static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
+@@ -325,7 +322,7 @@ static void oaktrail_lvds_get_configurat
+ void oaktrail_lvds_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+@@ -334,8 +331,8 @@ void oaktrail_lvds_init(struct drm_devic
+ struct i2c_adapter *i2c_adap;
+ struct drm_display_mode *scan; /* *modes, *bios_mode; */
+
+- psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+- if (!psb_intel_encoder)
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
++ if (!gma_encoder)
+ return;
+
+ gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
+@@ -343,7 +340,7 @@ void oaktrail_lvds_init(struct drm_devic
+ goto failed_connector;
+
+ connector = &gma_connector->base;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+ dev_priv->is_lvds_on = true;
+ drm_connector_init(dev, connector,
+ &psb_intel_lvds_connector_funcs,
+@@ -352,8 +349,8 @@ void oaktrail_lvds_init(struct drm_devic
+ drm_encoder_init(dev, encoder, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+- psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
++ gma_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
+ drm_connector_helper_add(connector,
+@@ -433,8 +430,8 @@ out:
+
+ failed_find:
+ dev_dbg(dev->dev, "No LVDS modes found, disabling.\n");
+- if (psb_intel_encoder->ddc_bus)
+- psb_intel_i2c_destroy(psb_intel_encoder->ddc_bus);
++ if (gma_encoder->ddc_bus)
++ psb_intel_i2c_destroy(gma_encoder->ddc_bus);
+
+ /* failed_ddc: */
+
+@@ -442,6 +439,6 @@ failed_find:
+ drm_connector_cleanup(connector);
+ kfree(gma_connector);
+ failed_connector:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+
+--- a/drivers/gpu/drm/gma500/psb_drv.c
++++ b/drivers/gpu/drm/gma500/psb_drv.c
+@@ -270,7 +270,7 @@ static int psb_driver_load(struct drm_de
+ unsigned long irqflags;
+ int ret = -ENOMEM;
+ struct drm_connector *connector;
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+
+ dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
+ if (dev_priv == NULL)
+@@ -372,9 +372,9 @@ static int psb_driver_load(struct drm_de
+ /* Only add backlight support if we have LVDS output */
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+- psb_intel_encoder = gma_attached_encoder(connector);
++ gma_encoder = gma_attached_encoder(connector);
+
+- switch (psb_intel_encoder->type) {
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ case INTEL_OUTPUT_MIPI:
+ ret = gma_backlight_init(dev);
+--- a/drivers/gpu/drm/gma500/psb_intel_display.c
++++ b/drivers/gpu/drm/gma500/psb_intel_display.c
+@@ -126,14 +126,13 @@ static int psb_intel_crtc_mode_set(struc
+ }
+
+ list_for_each_entry(connector, &mode_config->connector_list, head) {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+
+ if (!connector->encoder
+ || connector->encoder->crtc != crtc)
+ continue;
+
+- switch (psb_intel_encoder->type) {
++ switch (gma_encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ is_lvds = true;
+ break;
+@@ -602,9 +601,8 @@ int gma_connector_clones(struct drm_devi
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list,
+ head) {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- if (type_mask & (1 << psb_intel_encoder->type))
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ if (type_mask & (1 << gma_encoder->type))
+ index_mask |= (1 << entry);
+ entry++;
+ }
+--- a/drivers/gpu/drm/gma500/psb_intel_drv.h
++++ b/drivers/gpu/drm/gma500/psb_intel_drv.h
+@@ -117,11 +117,11 @@ struct psb_intel_i2c_chan {
+ u8 slave_addr;
+ };
+
+-struct psb_intel_encoder {
++struct gma_encoder {
+ struct drm_encoder base;
+ int type;
+ bool needs_tv_clock;
+- void (*hot_plug)(struct psb_intel_encoder *);
++ void (*hot_plug)(struct gma_encoder *);
+ int crtc_mask;
+ int clone_mask;
+ u32 ddi_select; /* Channel info */
+@@ -139,7 +139,7 @@ struct psb_intel_encoder {
+
+ struct gma_connector {
+ struct drm_connector base;
+- struct psb_intel_encoder *encoder;
++ struct gma_encoder *encoder;
+ };
+
+ struct psb_intel_crtc_state {
+@@ -197,8 +197,8 @@ struct gma_crtc {
+ container_of(x, struct gma_crtc, base)
+ #define to_gma_connector(x) \
+ container_of(x, struct gma_connector, base)
+-#define to_psb_intel_encoder(x) \
+- container_of(x, struct psb_intel_encoder, base)
++#define to_gma_encoder(x) \
++ container_of(x, struct gma_encoder, base)
+ #define to_psb_intel_framebuffer(x) \
+ container_of(x, struct psb_intel_framebuffer, base)
+
+@@ -228,9 +228,9 @@ extern void mid_dsi_init(struct drm_devi
+
+ extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector);
+ extern void gma_connector_attach_encoder(struct gma_connector *connector,
+- struct psb_intel_encoder *encoder);
++ struct gma_encoder *encoder);
+
+-static inline struct psb_intel_encoder *gma_attached_encoder(
++static inline struct gma_encoder *gma_attached_encoder(
+ struct drm_connector *connector)
+ {
+ return to_gma_connector(connector)->encoder;
+--- a/drivers/gpu/drm/gma500/psb_intel_lvds.c
++++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c
+@@ -267,10 +267,9 @@ static void psb_intel_lvds_save(struct d
+ struct drm_device *dev = connector->dev;
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *)dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv =
+- (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv;
++ (struct psb_intel_lvds_priv *)gma_encoder->dev_priv;
+
+ lvds_priv->savePP_ON = REG_READ(LVDSPP_ON);
+ lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF);
+@@ -307,10 +306,9 @@ static void psb_intel_lvds_restore(struc
+ {
+ struct drm_device *dev = connector->dev;
+ u32 pp_status;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+ struct psb_intel_lvds_priv *lvds_priv =
+- (struct psb_intel_lvds_priv *)psb_intel_encoder->dev_priv;
++ (struct psb_intel_lvds_priv *)gma_encoder->dev_priv;
+
+ dev_dbg(dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n",
+ lvds_priv->savePP_ON,
+@@ -349,12 +347,11 @@ int psb_intel_lvds_mode_valid(struct drm
+ struct drm_display_mode *mode)
+ {
+ struct drm_psb_private *dev_priv = connector->dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
+ struct drm_display_mode *fixed_mode =
+ dev_priv->mode_dev.panel_fixed_mode;
+
+- if (psb_intel_encoder->type == INTEL_OUTPUT_MIPI2)
++ if (gma_encoder->type == INTEL_OUTPUT_MIPI2)
+ fixed_mode = dev_priv->mode_dev.panel_fixed_mode2;
+
+ /* just in case */
+@@ -384,10 +381,9 @@ bool psb_intel_lvds_mode_fixup(struct dr
+ struct gma_crtc *gma_crtc = to_gma_crtc(encoder->crtc);
+ struct drm_encoder *tmp_encoder;
+ struct drm_display_mode *panel_fixed_mode = mode_dev->panel_fixed_mode;
+- struct psb_intel_encoder *psb_intel_encoder =
+- to_psb_intel_encoder(encoder);
++ struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
+
+- if (psb_intel_encoder->type == INTEL_OUTPUT_MIPI2)
++ if (gma_encoder->type == INTEL_OUTPUT_MIPI2)
+ panel_fixed_mode = mode_dev->panel_fixed_mode2;
+
+ /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
+@@ -524,9 +520,8 @@ static int psb_intel_lvds_get_modes(stru
+ struct drm_device *dev = connector->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv;
+ int ret = 0;
+
+ if (!IS_MRST(dev))
+@@ -563,9 +558,8 @@ static int psb_intel_lvds_get_modes(stru
+ */
+ void psb_intel_lvds_destroy(struct drm_connector *connector)
+ {
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct psb_intel_lvds_priv *lvds_priv = psb_intel_encoder->dev_priv;
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct psb_intel_lvds_priv *lvds_priv = gma_encoder->dev_priv;
+
+ if (lvds_priv->ddc_bus)
+ psb_intel_i2c_destroy(lvds_priv->ddc_bus);
+@@ -689,7 +683,7 @@ const struct drm_encoder_funcs psb_intel
+ void psb_intel_lvds_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev)
+ {
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct gma_connector *gma_connector;
+ struct psb_intel_lvds_priv *lvds_priv;
+ struct drm_connector *connector;
+@@ -700,10 +694,9 @@ void psb_intel_lvds_init(struct drm_devi
+ u32 lvds;
+ int pipe;
+
+- psb_intel_encoder =
+- kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
+- if (!psb_intel_encoder) {
+- dev_err(dev->dev, "psb_intel_encoder allocation error\n");
++ gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
++ if (!gma_encoder) {
++ dev_err(dev->dev, "gma_encoder allocation error\n");
+ return;
+ }
+
+@@ -719,10 +712,10 @@ void psb_intel_lvds_init(struct drm_devi
+ goto failed_connector;
+ }
+
+- psb_intel_encoder->dev_priv = lvds_priv;
++ gma_encoder->dev_priv = lvds_priv;
+
+ connector = &gma_connector->base;
+- encoder = &psb_intel_encoder->base;
++ encoder = &gma_encoder->base;
+ drm_connector_init(dev, connector,
+ &psb_intel_lvds_connector_funcs,
+ DRM_MODE_CONNECTOR_LVDS);
+@@ -731,8 +724,8 @@ void psb_intel_lvds_init(struct drm_devi
+ &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+- gma_connector_attach_encoder(gma_connector, psb_intel_encoder);
+- psb_intel_encoder->type = INTEL_OUTPUT_LVDS;
++ gma_connector_attach_encoder(gma_connector, gma_encoder);
++ gma_encoder->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &psb_intel_lvds_helper_funcs);
+ drm_connector_helper_add(connector,
+@@ -849,6 +842,6 @@ failed_blc_i2c:
+ failed_connector:
+ kfree(gma_connector);
+ failed_encoder:
+- kfree(psb_intel_encoder);
++ kfree(gma_encoder);
+ }
+
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -65,7 +65,7 @@ static const char *tv_format_names[] = {
+ #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
+
+ struct psb_intel_sdvo {
+- struct psb_intel_encoder base;
++ struct gma_encoder base;
+
+ struct i2c_adapter *i2c;
+ u8 slave_addr;
+@@ -1836,10 +1836,8 @@ done:
+ static void psb_intel_sdvo_save(struct drm_connector *connector)
+ {
+ struct drm_device *dev = connector->dev;
+- struct psb_intel_encoder *psb_intel_encoder =
+- gma_attached_encoder(connector);
+- struct psb_intel_sdvo *sdvo =
+- to_psb_intel_sdvo(&psb_intel_encoder->base);
++ struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
++ struct psb_intel_sdvo *sdvo = to_psb_intel_sdvo(&gma_encoder->base);
+
+ sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg);
+ }
+@@ -2539,7 +2537,7 @@ psb_intel_sdvo_init_ddc_proxy(struct psb
+ bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+- struct psb_intel_encoder *psb_intel_encoder;
++ struct gma_encoder *gma_encoder;
+ struct psb_intel_sdvo *psb_intel_sdvo;
+ int i;
+
+@@ -2556,9 +2554,9 @@ bool psb_intel_sdvo_init(struct drm_devi
+ }
+
+ /* encoder type will be decided later */
+- psb_intel_encoder = &psb_intel_sdvo->base;
+- psb_intel_encoder->type = INTEL_OUTPUT_SDVO;
+- drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
++ gma_encoder = &psb_intel_sdvo->base;
++ gma_encoder->type = INTEL_OUTPUT_SDVO;
++ drm_encoder_init(dev, &gma_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
+
+ /* Read the regs to test if we can talk to the device */
+ for (i = 0; i < 0x40; i++) {
+@@ -2576,7 +2574,7 @@ bool psb_intel_sdvo_init(struct drm_devi
+ else
+ dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
+
+- drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs);
++ drm_encoder_helper_add(&gma_encoder->base, &psb_intel_sdvo_helper_funcs);
+
+ /* In default case sdvo lvds is false */
+ if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
+@@ -2619,7 +2617,7 @@ bool psb_intel_sdvo_init(struct drm_devi
+ return true;
+
+ err:
+- drm_encoder_cleanup(&psb_intel_encoder->base);
++ drm_encoder_cleanup(&gma_encoder->base);
+ i2c_del_adapter(&psb_intel_sdvo->ddc);
+ kfree(psb_intel_sdvo);
+
--- /dev/null
+From 3721f5e9619b532b1f6ee5adee86ee2872c86704 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 16 Sep 2013 17:46:17 +0200
+Subject: drm/gma500: Add Minnowboard to the IS_MRST() macro
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 9d3e2f5304c77c2f4dcb96f03307575b25597b9a)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+
+Conflicts:
+ drivers/gpu/drm/gma500/psb_drv.h
+---
+ drivers/gpu/drm/gma500/psb_drv.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -45,7 +45,7 @@ enum {
+ };
+
+ #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
+-#define IS_MRST(dev) (((dev)->pdev->device & 0xfffc) == 0x4100)
++#define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
+ #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
+ #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
+
--- /dev/null
+From f087ce4489b32e493cdb98a5e47ed6c6ba65745f Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 16 Sep 2013 17:54:54 +0200
+Subject: drm/gma500: Add chip specific sdvo masks
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit cf8efd3afeff02fed2e2937ab3006618919bf65a)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_device.c | 1 +
+ drivers/gpu/drm/gma500/framebuffer.c | 2 +-
+ drivers/gpu/drm/gma500/oaktrail_device.c | 1 +
+ drivers/gpu/drm/gma500/psb_device.c | 1 +
+ drivers/gpu/drm/gma500/psb_drv.h | 1 +
+ 5 files changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_device.c
++++ b/drivers/gpu/drm/gma500/cdv_device.c
+@@ -634,6 +634,7 @@ const struct psb_ops cdv_chip_ops = {
+ .crtcs = 2,
+ .hdmi_mask = (1 << 0) | (1 << 1),
+ .lvds_mask = (1 << 1),
++ .sdvo_mask = (1 << 0),
+ .cursor_needs_phys = 0,
+ .sgx_offset = MRST_SGX_OFFSET,
+ .chip_setup = cdv_chip_setup,
+--- a/drivers/gpu/drm/gma500/framebuffer.c
++++ b/drivers/gpu/drm/gma500/framebuffer.c
+@@ -714,7 +714,7 @@ static void psb_setup_outputs(struct drm
+ clone_mask = (1 << INTEL_OUTPUT_ANALOG);
+ break;
+ case INTEL_OUTPUT_SDVO:
+- crtc_mask = ((1 << 0) | (1 << 1));
++ crtc_mask = dev_priv->ops->sdvo_mask;
+ clone_mask = (1 << INTEL_OUTPUT_SDVO);
+ break;
+ case INTEL_OUTPUT_LVDS:
+--- a/drivers/gpu/drm/gma500/oaktrail_device.c
++++ b/drivers/gpu/drm/gma500/oaktrail_device.c
+@@ -546,6 +546,7 @@ const struct psb_ops oaktrail_chip_ops =
+ .crtcs = 2,
+ .hdmi_mask = (1 << 1),
+ .lvds_mask = (1 << 0),
++ .sdvo_mask = (1 << 1),
+ .cursor_needs_phys = 0,
+ .sgx_offset = MRST_SGX_OFFSET,
+
+--- a/drivers/gpu/drm/gma500/psb_device.c
++++ b/drivers/gpu/drm/gma500/psb_device.c
+@@ -373,6 +373,7 @@ const struct psb_ops psb_chip_ops = {
+ .crtcs = 2,
+ .hdmi_mask = (1 << 0),
+ .lvds_mask = (1 << 1),
++ .sdvo_mask = (1 << 0),
+ .cursor_needs_phys = 1,
+ .sgx_offset = PSB_SGX_OFFSET,
+ .chip_setup = psb_chip_setup,
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -672,6 +672,7 @@ struct psb_ops {
+ int sgx_offset; /* Base offset of SGX device */
+ int hdmi_mask; /* Mask of HDMI CRTCs */
+ int lvds_mask; /* Mask of LVDS CRTCs */
++ int sdvo_mask; /* Mask of SDVO CRTCs */
+ int cursor_needs_phys; /* If cursor base reg need physical address */
+
+ /* Sub functions */
--- /dev/null
+From d1fb3e7a23996a053ebd6075cc622b27111108f1 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 16 Sep 2013 18:02:40 +0200
+Subject: drm/gma500: Add support for aux pci vdc device
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 2657929d4e7c0a4db5456cc2c9a230a68b07813d)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_drv.c | 32 +++++++++++++++++++++++++++++++-
+ drivers/gpu/drm/gma500/psb_drv.h | 21 ++++++++++++++++++++-
+ 2 files changed, 51 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_drv.c
++++ b/drivers/gpu/drm/gma500/psb_drv.c
+@@ -251,6 +251,12 @@ static int psb_driver_unload(struct drm_
+ iounmap(dev_priv->sgx_reg);
+ dev_priv->sgx_reg = NULL;
+ }
++ if (dev_priv->aux_reg) {
++ iounmap(dev_priv->aux_reg);
++ dev_priv->aux_reg = NULL;
++ }
++ if (dev_priv->aux_pdev)
++ pci_dev_put(dev_priv->aux_pdev);
+
+ /* Destroy VBT data */
+ psb_intel_destroy_bios(dev);
+@@ -266,7 +272,7 @@ static int psb_driver_unload(struct drm_
+ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
+ {
+ struct drm_psb_private *dev_priv;
+- unsigned long resource_start;
++ unsigned long resource_start, resource_len;
+ unsigned long irqflags;
+ int ret = -ENOMEM;
+ struct drm_connector *connector;
+@@ -296,6 +302,30 @@ static int psb_driver_load(struct drm_de
+ if (!dev_priv->sgx_reg)
+ goto out_err;
+
++ if (IS_MRST(dev)) {
++ dev_priv->aux_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(3, 0));
++
++ if (dev_priv->aux_pdev) {
++ resource_start = pci_resource_start(dev_priv->aux_pdev,
++ PSB_AUX_RESOURCE);
++ resource_len = pci_resource_len(dev_priv->aux_pdev,
++ PSB_AUX_RESOURCE);
++ dev_priv->aux_reg = ioremap_nocache(resource_start,
++ resource_len);
++ if (!dev_priv->aux_reg)
++ goto out_err;
++
++ DRM_DEBUG_KMS("Found aux vdc");
++ } else {
++ /* Couldn't find the aux vdc so map to primary vdc */
++ dev_priv->aux_reg = dev_priv->vdc_reg;
++ DRM_DEBUG_KMS("Couldn't find aux pci device");
++ }
++ dev_priv->gmbus_reg = dev_priv->aux_reg;
++ } else {
++ dev_priv->gmbus_reg = dev_priv->vdc_reg;
++ }
++
+ psb_intel_opregion_setup(dev);
+
+ ret = dev_priv->ops->chip_setup(dev);
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -75,6 +75,7 @@ enum {
+ * PCI resource identifiers
+ */
+ #define PSB_MMIO_RESOURCE 0
++#define PSB_AUX_RESOURCE 0
+ #define PSB_GATT_RESOURCE 2
+ #define PSB_GTT_RESOURCE 3
+ /*
+@@ -455,6 +456,7 @@ struct psb_ops;
+
+ struct drm_psb_private {
+ struct drm_device *dev;
++ struct pci_dev *aux_pdev; /* Currently only used by mrst */
+ const struct psb_ops *ops;
+ const struct psb_offset *regmap;
+
+@@ -486,6 +488,7 @@ struct drm_psb_private {
+
+ uint8_t __iomem *sgx_reg;
+ uint8_t __iomem *vdc_reg;
++ uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
+ uint32_t gatt_free_offset;
+
+ /*
+@@ -532,6 +535,7 @@ struct drm_psb_private {
+
+ /* gmbus */
+ struct intel_gmbus *gmbus;
++ uint8_t __iomem *gmbus_reg;
+
+ /* Used by SDVO */
+ int crt_ddc_pin;
+@@ -927,16 +931,31 @@ static inline uint32_t REGISTER_READ(str
+ return ioread32(dev_priv->vdc_reg + reg);
+ }
+
++static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
++{
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ return ioread32(dev_priv->aux_reg + reg);
++}
++
+ #define REG_READ(reg) REGISTER_READ(dev, (reg))
++#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
+
+ static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
+- uint32_t val)
++ uint32_t val)
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ iowrite32((val), dev_priv->vdc_reg + (reg));
+ }
+
++static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
++ uint32_t val)
++{
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ iowrite32((val), dev_priv->aux_reg + (reg));
++}
++
+ #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
++#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
+
+ static inline void REGISTER_WRITE16(struct drm_device *dev,
+ uint32_t reg, uint32_t val)
--- /dev/null
+From 2c4dc642afaf225b91275ec7264510a973c472f7 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Mon, 16 Sep 2013 18:36:37 +0200
+Subject: drm/gma500: Add aux device support for gmbus
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 86bd4103254adf7f3d32fa5c2578162c9e27b205)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/intel_gmbus.c | 90 +++++++++++++++++++----------------
+ 1 file changed, 49 insertions(+), 41 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/intel_gmbus.c
++++ b/drivers/gpu/drm/gma500/intel_gmbus.c
+@@ -51,6 +51,9 @@
+ #define wait_for(COND, MS) _wait_for(COND, MS, 1)
+ #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
+
++#define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
++#define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
++
+ /* Intel GPIO access functions */
+
+ #define I2C_RISEFALL_TIME 20
+@@ -71,7 +74,8 @@ struct intel_gpio {
+ void
+ gma_intel_i2c_reset(struct drm_device *dev)
+ {
+- REG_WRITE(GMBUS0, 0);
++ struct drm_psb_private *dev_priv = dev->dev_private;
++ GMBUS_REG_WRITE(GMBUS0, 0);
+ }
+
+ static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
+@@ -98,11 +102,10 @@ static void intel_i2c_quirk_set(struct d
+ static u32 get_reserved(struct intel_gpio *gpio)
+ {
+ struct drm_psb_private *dev_priv = gpio->dev_priv;
+- struct drm_device *dev = dev_priv->dev;
+ u32 reserved = 0;
+
+ /* On most chips, these bits must be preserved in software. */
+- reserved = REG_READ(gpio->reg) &
++ reserved = GMBUS_REG_READ(gpio->reg) &
+ (GPIO_DATA_PULLUP_DISABLE |
+ GPIO_CLOCK_PULLUP_DISABLE);
+
+@@ -113,29 +116,26 @@ static int get_clock(void *data)
+ {
+ struct intel_gpio *gpio = data;
+ struct drm_psb_private *dev_priv = gpio->dev_priv;
+- struct drm_device *dev = dev_priv->dev;
+ u32 reserved = get_reserved(gpio);
+- REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
+- REG_WRITE(gpio->reg, reserved);
+- return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
++ GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
++ GMBUS_REG_WRITE(gpio->reg, reserved);
++ return (GMBUS_REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
+ }
+
+ static int get_data(void *data)
+ {
+ struct intel_gpio *gpio = data;
+ struct drm_psb_private *dev_priv = gpio->dev_priv;
+- struct drm_device *dev = dev_priv->dev;
+ u32 reserved = get_reserved(gpio);
+- REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
+- REG_WRITE(gpio->reg, reserved);
+- return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
++ GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
++ GMBUS_REG_WRITE(gpio->reg, reserved);
++ return (GMBUS_REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
+ }
+
+ static void set_clock(void *data, int state_high)
+ {
+ struct intel_gpio *gpio = data;
+ struct drm_psb_private *dev_priv = gpio->dev_priv;
+- struct drm_device *dev = dev_priv->dev;
+ u32 reserved = get_reserved(gpio);
+ u32 clock_bits;
+
+@@ -145,15 +145,14 @@ static void set_clock(void *data, int st
+ clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
+ GPIO_CLOCK_VAL_MASK;
+
+- REG_WRITE(gpio->reg, reserved | clock_bits);
+- REG_READ(gpio->reg); /* Posting */
++ GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits);
++ GMBUS_REG_READ(gpio->reg); /* Posting */
+ }
+
+ static void set_data(void *data, int state_high)
+ {
+ struct intel_gpio *gpio = data;
+ struct drm_psb_private *dev_priv = gpio->dev_priv;
+- struct drm_device *dev = dev_priv->dev;
+ u32 reserved = get_reserved(gpio);
+ u32 data_bits;
+
+@@ -163,8 +162,8 @@ static void set_data(void *data, int sta
+ data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
+ GPIO_DATA_VAL_MASK;
+
+- REG_WRITE(gpio->reg, reserved | data_bits);
+- REG_READ(gpio->reg);
++ GMBUS_REG_WRITE(gpio->reg, reserved | data_bits);
++ GMBUS_REG_READ(gpio->reg);
+ }
+
+ static struct i2c_adapter *
+@@ -251,7 +250,6 @@ gmbus_xfer(struct i2c_adapter *adapter,
+ struct intel_gmbus,
+ adapter);
+ struct drm_psb_private *dev_priv = adapter->algo_data;
+- struct drm_device *dev = dev_priv->dev;
+ int i, reg_offset;
+
+ if (bus->force_bit)
+@@ -260,28 +258,30 @@ gmbus_xfer(struct i2c_adapter *adapter,
+
+ reg_offset = 0;
+
+- REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
++ GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
+
+ for (i = 0; i < num; i++) {
+ u16 len = msgs[i].len;
+ u8 *buf = msgs[i].buf;
+
+ if (msgs[i].flags & I2C_M_RD) {
+- REG_WRITE(GMBUS1 + reg_offset,
+- GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
+- (len << GMBUS_BYTE_COUNT_SHIFT) |
+- (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
+- GMBUS_SLAVE_READ | GMBUS_SW_RDY);
+- REG_READ(GMBUS2+reg_offset);
++ GMBUS_REG_WRITE(GMBUS1 + reg_offset,
++ GMBUS_CYCLE_WAIT |
++ (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
++ (len << GMBUS_BYTE_COUNT_SHIFT) |
++ (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
++ GMBUS_SLAVE_READ | GMBUS_SW_RDY);
++ GMBUS_REG_READ(GMBUS2+reg_offset);
+ do {
+ u32 val, loop = 0;
+
+- if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
++ if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
++ (GMBUS_SATOER | GMBUS_HW_RDY), 50))
+ goto timeout;
+- if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
++ if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
+ goto clear_err;
+
+- val = REG_READ(GMBUS3 + reg_offset);
++ val = GMBUS_REG_READ(GMBUS3 + reg_offset);
+ do {
+ *buf++ = val & 0xff;
+ val >>= 8;
+@@ -295,18 +295,20 @@ gmbus_xfer(struct i2c_adapter *adapter,
+ val |= *buf++ << (8 * loop);
+ } while (--len && ++loop < 4);
+
+- REG_WRITE(GMBUS3 + reg_offset, val);
+- REG_WRITE(GMBUS1 + reg_offset,
++ GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
++ GMBUS_REG_WRITE(GMBUS1 + reg_offset,
+ (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
+ (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
+ (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
+ GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
+- REG_READ(GMBUS2+reg_offset);
++ GMBUS_REG_READ(GMBUS2+reg_offset);
+
+ while (len) {
+- if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
++ if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) &
++ (GMBUS_SATOER | GMBUS_HW_RDY), 50))
+ goto timeout;
+- if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
++ if (GMBUS_REG_READ(GMBUS2 + reg_offset) &
++ GMBUS_SATOER)
+ goto clear_err;
+
+ val = loop = 0;
+@@ -314,14 +316,14 @@ gmbus_xfer(struct i2c_adapter *adapter,
+ val |= *buf++ << (8 * loop);
+ } while (--len && ++loop < 4);
+
+- REG_WRITE(GMBUS3 + reg_offset, val);
+- REG_READ(GMBUS2+reg_offset);
++ GMBUS_REG_WRITE(GMBUS3 + reg_offset, val);
++ GMBUS_REG_READ(GMBUS2+reg_offset);
+ }
+ }
+
+- if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
++ if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
+ goto timeout;
+- if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
++ if (GMBUS_REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
+ goto clear_err;
+ }
+
+@@ -332,20 +334,20 @@ clear_err:
+ * of resetting the GMBUS controller and so clearing the
+ * BUS_ERROR raised by the slave's NAK.
+ */
+- REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
+- REG_WRITE(GMBUS1 + reg_offset, 0);
++ GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
++ GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0);
+
+ done:
+ /* Mark the GMBUS interface as disabled. We will re-enable it at the
+ * start of the next xfer, till then let it sleep.
+ */
+- REG_WRITE(GMBUS0 + reg_offset, 0);
++ GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
+ return i;
+
+ timeout:
+ DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
+ bus->reg0 & 0xff, bus->adapter.name);
+- REG_WRITE(GMBUS0 + reg_offset, 0);
++ GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0);
+
+ /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
+ bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
+@@ -399,6 +401,11 @@ int gma_intel_setup_gmbus(struct drm_dev
+ if (dev_priv->gmbus == NULL)
+ return -ENOMEM;
+
++ if (IS_MRST(dev))
++ dev_priv->gmbus_reg = dev_priv->aux_reg;
++ else
++ dev_priv->gmbus_reg = dev_priv->vdc_reg;
++
+ for (i = 0; i < GMBUS_NUM_PORTS; i++) {
+ struct intel_gmbus *bus = &dev_priv->gmbus[i];
+
+@@ -487,6 +494,7 @@ void gma_intel_teardown_gmbus(struct drm
+ i2c_del_adapter(&bus->adapter);
+ }
+
++ dev_priv->gmbus_reg = NULL; /* iounmap is done in driver_unload */
+ kfree(dev_priv->gmbus);
+ dev_priv->gmbus = NULL;
+ }
--- /dev/null
+From cf71491555e61294cdb3a341db4c7d1af7b2d537 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 6 Nov 2013 22:31:18 +0100
+Subject: drm/gma500/mrst: Add SDVO clock calculation
+
+We start off by adding SDVO limits and converting all limits to the
+generic gma_limit_t stuct. Then we separate clock calculations for
+LVDS and SDVO. This will be cleaned up later but keep it simple for now.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit ac6113ebb70d4bc7018db4e73f923653347da743)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 175 +++++++++++++++++++++++----------
+ 1 file changed, 126 insertions(+), 49 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -26,24 +26,10 @@
+ #include "gma_display.h"
+ #include "power.h"
+
+-struct psb_intel_range_t {
+- int min, max;
+-};
+-
+-struct oaktrail_limit_t {
+- struct psb_intel_range_t dot, m, p1;
+-};
+-
+-struct oaktrail_clock_t {
+- /* derived values */
+- int dot;
+- int m;
+- int p1;
+-};
+-
+-#define MRST_LIMIT_LVDS_100L 0
+-#define MRST_LIMIT_LVDS_83 1
+-#define MRST_LIMIT_LVDS_100 2
++#define MRST_LIMIT_LVDS_100L 0
++#define MRST_LIMIT_LVDS_83 1
++#define MRST_LIMIT_LVDS_100 2
++#define MRST_LIMIT_SDVO 3
+
+ #define MRST_DOT_MIN 19750
+ #define MRST_DOT_MAX 120000
+@@ -57,21 +43,40 @@ struct oaktrail_clock_t {
+ #define MRST_P1_MAX_0 7
+ #define MRST_P1_MAX_1 8
+
+-static const struct oaktrail_limit_t oaktrail_limits[] = {
++static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk, struct gma_clock_t *best_clock);
++
++static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk, struct gma_clock_t *best_clock);
++
++static const struct gma_limit_t mrst_limits[] = {
+ { /* MRST_LIMIT_LVDS_100L */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
++ .find_pll = mrst_lvds_find_best_pll,
+ },
+ { /* MRST_LIMIT_LVDS_83L */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
++ .find_pll = mrst_lvds_find_best_pll,
+ },
+ { /* MRST_LIMIT_LVDS_100 */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
++ .find_pll = mrst_lvds_find_best_pll,
++ },
++ { /* MRST_LIMIT_SDVO */
++ .vco = {.min = 1400000, .max = 2800000},
++ .n = {.min = 3, .max = 7},
++ .m = {.min = 80, .max = 137},
++ .p1 = {.min = 1, .max = 2},
++ .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10},
++ .find_pll = mrst_sdvo_find_best_pll,
+ },
+ };
+
+@@ -82,9 +87,10 @@ static const u32 oaktrail_m_converts[] =
+ 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
+ };
+
+-static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc)
++static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc,
++ int refclk)
+ {
+- const struct oaktrail_limit_t *limit = NULL;
++ const struct gma_limit_t *limit = NULL;
+ struct drm_device *dev = crtc->dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+@@ -92,45 +98,100 @@ static const struct oaktrail_limit_t *oa
+ || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
+ switch (dev_priv->core_freq) {
+ case 100:
+- limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L];
++ limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
+ break;
+ case 166:
+- limit = &oaktrail_limits[MRST_LIMIT_LVDS_83];
++ limit = &mrst_limits[MRST_LIMIT_LVDS_83];
+ break;
+ case 200:
+- limit = &oaktrail_limits[MRST_LIMIT_LVDS_100];
++ limit = &mrst_limits[MRST_LIMIT_LVDS_100];
+ break;
+ }
++ } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
++ limit = &mrst_limits[MRST_LIMIT_SDVO];
+ } else {
+ limit = NULL;
+- dev_err(dev->dev, "oaktrail_limit Wrong display type.\n");
++ dev_err(dev->dev, "mrst_limit Wrong display type.\n");
+ }
+
+ return limit;
+ }
+
+ /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
+-static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock)
++static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock)
+ {
+ clock->dot = (refclk * clock->m) / (14 * clock->p1);
+ }
+
+-static void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock)
++static void mrst_print_pll(struct gma_clock_t *clock)
++{
++ DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n",
++ clock->dot, clock->m, clock->m1, clock->m2, clock->n,
++ clock->p1, clock->p2);
++}
++
++static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk, struct gma_clock_t *best_clock)
+ {
+- pr_debug("%s: dotclock = %d, m = %d, p1 = %d.\n",
+- prefix, clock->dot, clock->m, clock->p1);
++ struct gma_clock_t clock;
++ u32 target_vco, actual_freq;
++ s32 freq_error, min_error = 100000;
++
++ memset(best_clock, 0, sizeof(*best_clock));
++
++ for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
++ for (clock.n = limit->n.min; clock.n <= limit->n.max;
++ clock.n++) {
++ for (clock.p1 = limit->p1.min;
++ clock.p1 <= limit->p1.max; clock.p1++) {
++ /* p2 value always stored in p2_slow on SDVO */
++ clock.p = clock.p1 * limit->p2.p2_slow;
++ target_vco = target * clock.p;
++
++ /* VCO will increase at this point so break */
++ if (target_vco > limit->vco.max)
++ break;
++
++ if (target_vco < limit->vco.min)
++ continue;
++
++ actual_freq = (refclk * clock.m) /
++ (clock.n * clock.p);
++ freq_error = 10000 -
++ ((target * 10000) / actual_freq);
++
++ if (freq_error < -min_error) {
++ /* freq_error will start to decrease at
++ this point so break */
++ break;
++ }
++
++ if (freq_error < 0)
++ freq_error = -freq_error;
++
++ if (freq_error < min_error) {
++ min_error = freq_error;
++ *best_clock = clock;
++ }
++ }
++ }
++ if (min_error == 0)
++ break;
++ }
++
++ return min_error == 0;
+ }
+
+ /**
+ * Returns a set of divisors for the desired target clock with the given refclk,
+ * or FALSE. Divisor values are the actual divisors for
+ */
+-static bool
+-mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
+- struct oaktrail_clock_t *best_clock)
++static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit,
++ struct drm_crtc *crtc, int target,
++ int refclk, struct gma_clock_t *best_clock)
+ {
+- struct oaktrail_clock_t clock;
+- const struct oaktrail_limit_t *limit = oaktrail_limit(crtc);
++ struct gma_clock_t clock;
+ int err = target;
+
+ memset(best_clock, 0, sizeof(*best_clock));
+@@ -140,7 +201,7 @@ mrstFindBestPLL(struct drm_crtc *crtc, i
+ clock.p1++) {
+ int this_err;
+
+- oaktrail_clock(refclk, &clock);
++ mrst_lvds_clock(refclk, &clock);
+
+ this_err = abs(clock.dot - target);
+ if (this_err < err) {
+@@ -149,7 +210,6 @@ mrstFindBestPLL(struct drm_crtc *crtc, i
+ }
+ }
+ }
+- dev_dbg(crtc->dev->dev, "mrstFindBestPLL err = %d.\n", err);
+ return err != target;
+ }
+
+@@ -297,7 +357,8 @@ static int oaktrail_crtc_mode_set(struct
+ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ int refclk = 0;
+- struct oaktrail_clock_t clock;
++ struct gma_clock_t clock;
++ const struct gma_limit_t *limit;
+ u32 dpll = 0, fp = 0, dspcntr, pipeconf;
+ bool ok, is_sdvo = false;
+ bool is_lvds = false;
+@@ -418,21 +479,30 @@ static int oaktrail_crtc_mode_set(struct
+ if (is_mipi)
+ goto oaktrail_crtc_mode_set_exit;
+
+- refclk = dev_priv->core_freq * 1000;
+
+ dpll = 0; /*BIT16 = 0 for 100MHz reference */
+
+- ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
++ refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000;
++ limit = mrst_limit(crtc, refclk);
++ ok = limit->find_pll(limit, crtc, adjusted_mode->clock,
++ refclk, &clock);
+
+- if (!ok) {
+- dev_dbg(dev->dev, "mrstFindBestPLL fail in oaktrail_crtc_mode_set.\n");
+- } else {
+- dev_dbg(dev->dev, "oaktrail_crtc_mode_set pixel clock = %d,"
+- "m = %x, p1 = %x.\n", clock.dot, clock.m,
+- clock.p1);
++ if (is_sdvo) {
++ /* Convert calculated values to register values */
++ clock.p1 = (1L << (clock.p1 - 1));
++ clock.m -= 2;
++ clock.n = (1L << (clock.n - 1));
+ }
+
+- fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
++ if (!ok)
++ DRM_ERROR("Failed to find proper PLL settings");
++
++ mrst_print_pll(&clock);
++
++ if (is_sdvo)
++ fp = clock.n << 16 | clock.m;
++ else
++ fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
+
+ dpll |= DPLL_VGA_MODE_DIS;
+
+@@ -456,12 +526,13 @@ static int oaktrail_crtc_mode_set(struct
+
+
+ /* compute bitmask from p1 value */
+- dpll |= (1 << (clock.p1 - 2)) << 17;
++ if (is_sdvo)
++ dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;
++ else
++ dpll |= (1 << (clock.p1 - 2)) << 17;
+
+ dpll |= DPLL_VCO_ENABLE;
+
+- mrstPrintPll("chosen", &clock);
+-
+ if (dpll & DPLL_VCO_ENABLE) {
+ REG_WRITE(map->fp0, fp);
+ REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
+@@ -565,3 +636,9 @@ const struct drm_crtc_helper_funcs oaktr
+ .commit = gma_crtc_commit,
+ };
+
++/* Not used yet */
++const struct gma_clock_funcs mrst_clock_funcs = {
++ .clock = mrst_lvds_clock,
++ .limit = mrst_limit,
++ .pll_is_valid = gma_pll_is_valid,
++};
--- /dev/null
+From e8321eb5f0641cd1b9d875b4c6c9dba063974c28 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 7 Nov 2013 00:14:18 +0100
+Subject: drm/gma500/mrst: Add aux register writes when programming pipe
+
+On SDVO pipes (always Pipe B on mrst) we have to sequentially write the
+aux vdc. We might be able to skip programming the primary vdc in
+some/most places but we don't care about that now.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit b97b8287a39d1fe6f8aa1b83405f669634ff8401)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 247 ++++++++++++++++++---------------
+ drivers/gpu/drm/gma500/psb_drv.h | 27 +++
+ 2 files changed, 165 insertions(+), 109 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -227,6 +227,8 @@ static void oaktrail_crtc_dpms(struct dr
+ int pipe = gma_crtc->pipe;
+ const struct psb_offset *map = &dev_priv->regmap[pipe];
+ u32 temp;
++ int i;
++ int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
+
+ if (pipe == 1) {
+ oaktrail_crtc_hdmi_dpms(crtc, mode);
+@@ -243,35 +245,45 @@ static void oaktrail_crtc_dpms(struct dr
+ case DRM_MODE_DPMS_ON:
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+- /* Enable the DPLL */
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) == 0) {
+- REG_WRITE(map->dpll, temp);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+- }
+- /* Enable the pipe */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) == 0)
+- REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
+- /* Enable the plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
+- REG_WRITE(map->cntr,
+- temp | DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- }
++ for (i = 0; i <= need_aux; i++) {
++ /* Enable the DPLL */
++ temp = REG_READ_WITH_AUX(map->dpll, i);
++ if ((temp & DPLL_VCO_ENABLE) == 0) {
++ REG_WRITE_WITH_AUX(map->dpll, temp, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ REG_WRITE_WITH_AUX(map->dpll,
++ temp | DPLL_VCO_ENABLE, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ REG_WRITE_WITH_AUX(map->dpll,
++ temp | DPLL_VCO_ENABLE, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++ }
++
++ /* Enable the pipe */
++ temp = REG_READ_WITH_AUX(map->conf, i);
++ if ((temp & PIPEACONF_ENABLE) == 0) {
++ REG_WRITE_WITH_AUX(map->conf,
++ temp | PIPEACONF_ENABLE, i);
++ }
++
++ /* Enable the plane */
++ temp = REG_READ_WITH_AUX(map->cntr, i);
++ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
++ REG_WRITE_WITH_AUX(map->cntr,
++ temp | DISPLAY_PLANE_ENABLE,
++ i);
++ /* Flush the plane changes */
++ REG_WRITE_WITH_AUX(map->base,
++ REG_READ_WITH_AUX(map->base, i), i);
++ }
+
++ }
+ gma_crtc_load_lut(crtc);
+
+ /* Give the overlay scaler a chance to enable
+@@ -283,35 +295,40 @@ static void oaktrail_crtc_dpms(struct dr
+ * if it's on this pipe */
+ /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
+
+- /* Disable the VGA plane that we never use */
+- REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+- /* Disable display plane */
+- temp = REG_READ(map->cntr);
+- if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
+- REG_WRITE(map->cntr,
+- temp & ~DISPLAY_PLANE_ENABLE);
+- /* Flush the plane changes */
+- REG_WRITE(map->base, REG_READ(map->base));
+- REG_READ(map->base);
+- }
++ for (i = 0; i <= need_aux; i++) {
++ /* Disable the VGA plane that we never use */
++ REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
++ /* Disable display plane */
++ temp = REG_READ_WITH_AUX(map->cntr, i);
++ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
++ REG_WRITE_WITH_AUX(map->cntr,
++ temp & ~DISPLAY_PLANE_ENABLE, i);
++ /* Flush the plane changes */
++ REG_WRITE_WITH_AUX(map->base,
++ REG_READ(map->base), i);
++ REG_READ_WITH_AUX(map->base, i);
++ }
++
++ /* Next, disable display pipes */
++ temp = REG_READ_WITH_AUX(map->conf, i);
++ if ((temp & PIPEACONF_ENABLE) != 0) {
++ REG_WRITE_WITH_AUX(map->conf,
++ temp & ~PIPEACONF_ENABLE, i);
++ REG_READ_WITH_AUX(map->conf, i);
++ }
++ /* Wait for for the pipe disable to take effect. */
++ gma_wait_for_vblank(dev);
++
++ temp = REG_READ_WITH_AUX(map->dpll, i);
++ if ((temp & DPLL_VCO_ENABLE) != 0) {
++ REG_WRITE_WITH_AUX(map->dpll,
++ temp & ~DPLL_VCO_ENABLE, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ }
+
+- /* Next, disable display pipes */
+- temp = REG_READ(map->conf);
+- if ((temp & PIPEACONF_ENABLE) != 0) {
+- REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
+- REG_READ(map->conf);
+- }
+- /* Wait for for the pipe disable to take effect. */
+- gma_wait_for_vblank(dev);
+-
+- temp = REG_READ(map->dpll);
+- if ((temp & DPLL_VCO_ENABLE) != 0) {
+- REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
++ /* Wait for the clocks to turn off. */
++ udelay(150);
+ }
+-
+- /* Wait for the clocks to turn off. */
+- udelay(150);
+ break;
+ }
+
+@@ -367,6 +384,8 @@ static int oaktrail_crtc_mode_set(struct
+ struct gma_encoder *gma_encoder = NULL;
+ uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
+ struct drm_connector *connector;
++ int i;
++ int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
+
+ if (pipe == 1)
+ return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
+@@ -401,15 +420,17 @@ static int oaktrail_crtc_mode_set(struct
+ }
+
+ /* Disable the VGA plane that we never use */
+- REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
++ for (i = 0; i <= need_aux; i++)
++ REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i);
+
+ /* Disable the panel fitter if it was on our pipe */
+ if (oaktrail_panel_fitter_pipe(dev) == pipe)
+ REG_WRITE(PFIT_CONTROL, 0);
+
+- REG_WRITE(map->src,
+- ((mode->crtc_hdisplay - 1) << 16) |
+- (mode->crtc_vdisplay - 1));
++ for (i = 0; i <= need_aux; i++) {
++ REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) |
++ (mode->crtc_vdisplay - 1), i);
++ }
+
+ if (gma_encoder)
+ drm_object_property_get_value(&connector->base,
+@@ -426,35 +447,39 @@ static int oaktrail_crtc_mode_set(struct
+ offsetY = (adjusted_mode->crtc_vdisplay -
+ mode->crtc_vdisplay) / 2;
+
+- REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
+- ((adjusted_mode->crtc_htotal - 1) << 16));
+- REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
+- ((adjusted_mode->crtc_vtotal - 1) << 16));
+- REG_WRITE(map->hblank,
+- (adjusted_mode->crtc_hblank_start - offsetX - 1) |
+- ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
+- REG_WRITE(map->hsync,
+- (adjusted_mode->crtc_hsync_start - offsetX - 1) |
+- ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
+- REG_WRITE(map->vblank,
+- (adjusted_mode->crtc_vblank_start - offsetY - 1) |
+- ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
+- REG_WRITE(map->vsync,
+- (adjusted_mode->crtc_vsync_start - offsetY - 1) |
+- ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
++ for (i = 0; i <= need_aux; i++) {
++ REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) |
++ ((adjusted_mode->crtc_htotal - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) |
++ ((adjusted_mode->crtc_vtotal - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->hblank,
++ (adjusted_mode->crtc_hblank_start - offsetX - 1) |
++ ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->hsync,
++ (adjusted_mode->crtc_hsync_start - offsetX - 1) |
++ ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vblank,
++ (adjusted_mode->crtc_vblank_start - offsetY - 1) |
++ ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vsync,
++ (adjusted_mode->crtc_vsync_start - offsetY - 1) |
++ ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i);
++ }
+ } else {
+- REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
+- ((adjusted_mode->crtc_htotal - 1) << 16));
+- REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
+- ((adjusted_mode->crtc_vtotal - 1) << 16));
+- REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
+- ((adjusted_mode->crtc_hblank_end - 1) << 16));
+- REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
+- ((adjusted_mode->crtc_hsync_end - 1) << 16));
+- REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
+- ((adjusted_mode->crtc_vblank_end - 1) << 16));
+- REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
+- ((adjusted_mode->crtc_vsync_end - 1) << 16));
++ for (i = 0; i <= need_aux; i++) {
++ REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
++ ((adjusted_mode->crtc_htotal - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
++ ((adjusted_mode->crtc_vtotal - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
++ ((adjusted_mode->crtc_hblank_end - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
++ ((adjusted_mode->crtc_hsync_end - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
++ ((adjusted_mode->crtc_vblank_end - 1) << 16), i);
++ REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
++ ((adjusted_mode->crtc_vsync_end - 1) << 16), i);
++ }
+ }
+
+ /* Flush the plane changes */
+@@ -534,31 +559,35 @@ static int oaktrail_crtc_mode_set(struct
+ dpll |= DPLL_VCO_ENABLE;
+
+ if (dpll & DPLL_VCO_ENABLE) {
+- REG_WRITE(map->fp0, fp);
+- REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
+- REG_READ(map->dpll);
+- /* Check the DPLLA lock bit PIPEACONF[29] */
+- udelay(150);
++ for (i = 0; i <= need_aux; i++) {
++ REG_WRITE_WITH_AUX(map->fp0, fp, i);
++ REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Check the DPLLA lock bit PIPEACONF[29] */
++ udelay(150);
++ }
+ }
+
+- REG_WRITE(map->fp0, fp);
+- REG_WRITE(map->dpll, dpll);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+-
+- /* write it again -- the BIOS does, after all */
+- REG_WRITE(map->dpll, dpll);
+- REG_READ(map->dpll);
+- /* Wait for the clocks to stabilize. */
+- udelay(150);
+-
+- REG_WRITE(map->conf, pipeconf);
+- REG_READ(map->conf);
+- gma_wait_for_vblank(dev);
++ for (i = 0; i <= need_aux; i++) {
++ REG_WRITE_WITH_AUX(map->fp0, fp, i);
++ REG_WRITE_WITH_AUX(map->dpll, dpll, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
+
+- REG_WRITE(map->cntr, dspcntr);
+- gma_wait_for_vblank(dev);
++ /* write it again -- the BIOS does, after all */
++ REG_WRITE_WITH_AUX(map->dpll, dpll, i);
++ REG_READ_WITH_AUX(map->dpll, i);
++ /* Wait for the clocks to stabilize. */
++ udelay(150);
++
++ REG_WRITE_WITH_AUX(map->conf, pipeconf, i);
++ REG_READ_WITH_AUX(map->conf, i);
++ gma_wait_for_vblank(dev);
++
++ REG_WRITE_WITH_AUX(map->cntr, dspcntr, i);
++ gma_wait_for_vblank(dev);
++ }
+
+ oaktrail_crtc_mode_set_exit:
+ gma_power_end(dev);
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -940,6 +940,22 @@ static inline uint32_t REGISTER_READ_AUX
+ #define REG_READ(reg) REGISTER_READ(dev, (reg))
+ #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
+
++/* Useful for post reads */
++static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
++ uint32_t reg, int aux)
++{
++ uint32_t val;
++
++ if (aux)
++ val = REG_READ_AUX(reg);
++ else
++ val = REG_READ(reg);
++
++ return val;
++}
++
++#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
++
+ static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
+ uint32_t val)
+ {
+@@ -957,6 +973,17 @@ static inline void REGISTER_WRITE_AUX(st
+ #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
+ #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
+
++static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
++ uint32_t val, int aux)
++{
++ if (aux)
++ REG_WRITE_AUX(reg, val);
++ else
++ REG_WRITE(reg, val);
++}
++
++#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
++
+ static inline void REGISTER_WRITE16(struct drm_device *dev,
+ uint32_t reg, uint32_t val)
+ {
--- /dev/null
+From bf579becc39ff67c7ce82109da2f881e9944adc8 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 7 Nov 2013 00:22:59 +0100
+Subject: drm/gma500/mrst: Properly route oaktrail hdmi hooks
+
+Since we can have SDVO on Pipe B we better check the output type instead
+of pipe number for Oaktrail HDMI.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 5aac788323dfdd61a6be31734170d644e5d7cb4f)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -230,7 +230,7 @@ static void oaktrail_crtc_dpms(struct dr
+ int i;
+ int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
+
+- if (pipe == 1) {
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
+ oaktrail_crtc_hdmi_dpms(crtc, mode);
+ return;
+ }
+@@ -387,7 +387,7 @@ static int oaktrail_crtc_mode_set(struct
+ int i;
+ int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0;
+
+- if (pipe == 1)
++ if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+ return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
+
+ if (!gma_power_begin(dev, true))
--- /dev/null
+From a7e0738a9067d027251134a1830130d98f5ff791 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 7 Nov 2013 02:21:07 +0100
+Subject: drm/gma500/mrst: Add aux register writes to SDVO
+
+This turned out to be tricky. Writing to SDVOB on the primary vdc also
+writes to SDVOB on the aux vdc, but reading it back on the primary vdc
+always fails. Basically we never read from the primary vdc since we
+will end up trashing the aux vdc.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit fb8e34d561d58297af06b7350d9fdcafced8e1c5)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/psb_intel_sdvo.c | 59 ++++++++++++++++++++------------
+ 1 file changed, 38 insertions(+), 21 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/psb_intel_sdvo.c
++++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c
+@@ -228,24 +228,26 @@ static void psb_intel_sdvo_write_sdvox(s
+ {
+ struct drm_device *dev = psb_intel_sdvo->base.base.dev;
+ u32 bval = val, cval = val;
+- int i;
++ int i, j;
++ int need_aux = IS_MRST(dev) ? 1 : 0;
+
+- if (psb_intel_sdvo->sdvo_reg == SDVOB) {
+- cval = REG_READ(SDVOC);
+- } else {
+- bval = REG_READ(SDVOB);
+- }
+- /*
+- * Write the registers twice for luck. Sometimes,
+- * writing them only once doesn't appear to 'stick'.
+- * The BIOS does this too. Yay, magic
+- */
+- for (i = 0; i < 2; i++)
+- {
+- REG_WRITE(SDVOB, bval);
+- REG_READ(SDVOB);
+- REG_WRITE(SDVOC, cval);
+- REG_READ(SDVOC);
++ for (j = 0; j <= need_aux; j++) {
++ if (psb_intel_sdvo->sdvo_reg == SDVOB)
++ cval = REG_READ_WITH_AUX(SDVOC, j);
++ else
++ bval = REG_READ_WITH_AUX(SDVOB, j);
++
++ /*
++ * Write the registers twice for luck. Sometimes,
++ * writing them only once doesn't appear to 'stick'.
++ * The BIOS does this too. Yay, magic
++ */
++ for (i = 0; i < 2; i++) {
++ REG_WRITE_WITH_AUX(SDVOB, bval, j);
++ REG_READ_WITH_AUX(SDVOB, j);
++ REG_WRITE_WITH_AUX(SDVOC, cval, j);
++ REG_READ_WITH_AUX(SDVOC, j);
++ }
+ }
+ }
+
+@@ -994,6 +996,7 @@ static void psb_intel_sdvo_mode_set(stru
+ struct psb_intel_sdvo_dtd input_dtd;
+ int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
+ int rate;
++ int need_aux = IS_MRST(dev) ? 1 : 0;
+
+ if (!mode)
+ return;
+@@ -1059,7 +1062,11 @@ static void psb_intel_sdvo_mode_set(stru
+ return;
+
+ /* Set the SDVO control regs. */
+- sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
++ if (need_aux)
++ sdvox = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
++ else
++ sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
++
+ switch (psb_intel_sdvo->sdvo_reg) {
+ case SDVOB:
+ sdvox &= SDVOB_PRESERVE_MASK;
+@@ -1089,6 +1096,8 @@ static void psb_intel_sdvo_dpms(struct d
+ struct drm_device *dev = encoder->dev;
+ struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
+ u32 temp;
++ int i;
++ int need_aux = IS_MRST(dev) ? 1 : 0;
+
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+@@ -1107,19 +1116,27 @@ static void psb_intel_sdvo_dpms(struct d
+ psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
+
+ if (mode == DRM_MODE_DPMS_OFF) {
+- temp = REG_READ(psb_intel_sdvo->sdvo_reg);
++ if (need_aux)
++ temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
++ else
++ temp = REG_READ(psb_intel_sdvo->sdvo_reg);
++
+ if ((temp & SDVO_ENABLE) != 0) {
+ psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
+ }
+ }
+ } else {
+ bool input1, input2;
+- int i;
+ u8 status;
+
+- temp = REG_READ(psb_intel_sdvo->sdvo_reg);
++ if (need_aux)
++ temp = REG_READ_AUX(psb_intel_sdvo->sdvo_reg);
++ else
++ temp = REG_READ(psb_intel_sdvo->sdvo_reg);
++
+ if ((temp & SDVO_ENABLE) == 0)
+ psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
++
+ for (i = 0; i < 2; i++)
+ gma_wait_for_vblank(dev);
+
--- /dev/null
+From e2a79affcdc3b27fedd04e7a7c1020e0a2c512ac Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 7 Nov 2013 02:34:12 +0100
+Subject: drm/gma500/mrst: Replace WMs and chickenbits with values from EMGD
+
+For the minnowboard to work the values found in EMGD are required.
+This might break Oaktrail but without hardware to test with I cannot
+really tell (and do not really care).
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 99d754bb46e41cf88f6e5d96dd3c6c3b9c3bddb3)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_crtc.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_crtc.c
++++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c
+@@ -332,16 +332,15 @@ static void oaktrail_crtc_dpms(struct dr
+ break;
+ }
+
+- /*Set FIFO Watermarks*/
+- REG_WRITE(DSPARB, 0x3FFF);
+- REG_WRITE(DSPFW1, 0x3F88080A);
+- REG_WRITE(DSPFW2, 0x0b060808);
++ /* Set FIFO Watermarks (values taken from EMGD) */
++ REG_WRITE(DSPARB, 0x3f80);
++ REG_WRITE(DSPFW1, 0x3f8f0404);
++ REG_WRITE(DSPFW2, 0x04040f04);
+ REG_WRITE(DSPFW3, 0x0);
+- REG_WRITE(DSPFW4, 0x08030404);
++ REG_WRITE(DSPFW4, 0x04040404);
+ REG_WRITE(DSPFW5, 0x04040404);
+ REG_WRITE(DSPFW6, 0x78);
+- REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
+- /* Must write Bit 14 of the Chicken Bit Register */
++ REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040);
+
+ gma_power_end(dev);
+ }
--- /dev/null
+From cff86f3d04f6e9c10cd70cdc288f7d52a66c5395 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 7 Nov 2013 03:04:04 +0100
+Subject: drm/gma500/mrst: Setup GMBUS for oaktrail/mrst
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 6528c897966c7d520f18ed4804c31a1f1aa8a3d9)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_device.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_device.c
++++ b/drivers/gpu/drm/gma500/oaktrail_device.c
+@@ -526,6 +526,7 @@ static int oaktrail_chip_setup(struct dr
+ psb_intel_opregion_init(dev);
+ psb_intel_init_bios(dev);
+ }
++ gma_intel_setup_gmbus(dev);
+ oaktrail_hdmi_setup(dev);
+ return 0;
+ }
+@@ -534,6 +535,7 @@ static void oaktrail_teardown(struct drm
+ {
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
++ gma_intel_teardown_gmbus(dev);
+ oaktrail_hdmi_teardown(dev);
+ if (!dev_priv->has_gct)
+ psb_intel_destroy_bios(dev);
--- /dev/null
+From 07666a317c817b655077cd5a5f07a5fa78442f20 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 8 Nov 2013 16:00:33 +0100
+Subject: drm/gma500/mrst: Don't blindly guess a mode for LVDS
+
+Previously we always had something hooked up to LVDS so we tried very
+hard to get a mode. With the Minnowboard this is no longer the case.
+If no mode can be found over DDC or the firmware we just ignore LVDS.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 49a5d87a894681321d43ed80acb1edf705df0aea)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_lvds.c | 30 +++---------------------------
+ 1 file changed, 3 insertions(+), 27 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_lvds.c
++++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c
+@@ -218,30 +218,6 @@ static const struct drm_encoder_helper_f
+ .commit = oaktrail_lvds_commit,
+ };
+
+-static struct drm_display_mode lvds_configuration_modes[] = {
+- /* hard coded fixed mode for TPO LTPS LPJ040K001A */
+- { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
+- 846, 1056, 0, 480, 489, 491, 525, 0, 0) },
+- /* hard coded fixed mode for LVDS 800x480 */
+- { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
+- 802, 1024, 0, 480, 481, 482, 525, 0, 0) },
+- /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
+- { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
+- 1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
+- /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
+- { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
+- 1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
+- /* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
+- { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
+- 1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
+- /* hard coded fixed mode for LVDS 1024x768 */
+- { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
+- 1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
+- /* hard coded fixed mode for LVDS 1366x768 */
+- { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
+- 1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
+-};
+-
+ /* Returns the panel fixed mode from configuration. */
+
+ static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
+@@ -303,10 +279,10 @@ static void oaktrail_lvds_get_configurat
+ mode_dev->panel_fixed_mode =
+ drm_mode_duplicate(dev,
+ dev_priv->lfp_lvds_vbt_mode);
+- /* Then guess */
++
++ /* If we still got no mode then bail */
+ if (mode_dev->panel_fixed_mode == NULL)
+- mode_dev->panel_fixed_mode
+- = drm_mode_duplicate(dev, &lvds_configuration_modes[2]);
++ return;
+
+ drm_mode_set_name(mode_dev->panel_fixed_mode);
+ drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
--- /dev/null
+From 578aa57b75f388405c91fb612df42c492a1acbe4 Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Fri, 8 Nov 2013 16:14:08 +0100
+Subject: drm/gma500/mrst: Add SDVO to output init
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit cd3fdbe853c47c5890d5362363b59504c2e5fb5f)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/oaktrail_device.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/gma500/oaktrail_device.c
++++ b/drivers/gpu/drm/gma500/oaktrail_device.c
+@@ -40,6 +40,9 @@ static int oaktrail_output_init(struct d
+ dev_err(dev->dev, "DSI is not supported\n");
+ if (dev_priv->hdmi_priv)
+ oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
++
++ psb_intel_sdvo_init(dev, SDVOB);
++
+ return 0;
+ }
+
--- /dev/null
+From 1a3369d3d2729108c26a1b3c9d340dcd580b0fbb Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Wed, 14 Aug 2013 19:14:17 +0200
+Subject: drm/gma500/cdv: Add and hook up chip op for watermarks
+
+Add a callback hook to the chip ops struct to allow chips to have their
+specific fifo watermark update function. Currently only cdv actually
+tries to set wms based on crtc configuration but if/when the other chips
+needs it we can attach a callback for them as well.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 28a8194c12f8c8bb46aecd4cb1f36bac716714c4)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_device.c | 1 +
+ drivers/gpu/drm/gma500/cdv_device.h | 1 +
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 2 +-
+ drivers/gpu/drm/gma500/gma_display.c | 2 +-
+ drivers/gpu/drm/gma500/gma_display.h | 2 --
+ drivers/gpu/drm/gma500/psb_drv.h | 1 +
+ 6 files changed, 5 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_device.c
++++ b/drivers/gpu/drm/gma500/cdv_device.c
+@@ -657,4 +657,5 @@ const struct psb_ops cdv_chip_ops = {
+ .restore_regs = cdv_restore_display_registers,
+ .power_down = cdv_power_down,
+ .power_up = cdv_power_up,
++ .update_wm = cdv_update_wm,
+ };
+--- a/drivers/gpu/drm/gma500/cdv_device.h
++++ b/drivers/gpu/drm/gma500/cdv_device.h
+@@ -26,3 +26,4 @@ extern void cdv_hdmi_init(struct drm_dev
+ int reg);
+ extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc);
++extern void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc);
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -532,7 +532,7 @@ void cdv_intel_disable_self_refresh(stru
+
+ }
+
+-void cdv_intel_update_watermark(struct drm_device *dev, struct drm_crtc *crtc)
++void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
+ {
+
+ if (cdv_intel_single_pipe_active(dev)) {
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -321,7 +321,7 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ }
+
+ if (IS_CDV(dev))
+- cdv_intel_update_watermark(dev, crtc);
++ dev_priv->ops->update_wm(dev, crtc);
+
+ /* Set FIFO watermarks */
+ REG_WRITE(DSPARB, 0x3F3E);
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -103,6 +103,4 @@ extern bool gma_find_best_pll(const stru
+
+ /* Cedarview specific functions */
+ extern void cdv_intel_disable_self_refresh(struct drm_device *dev);
+-extern void cdv_intel_update_watermark(struct drm_device *dev,
+- struct drm_crtc *crtc);
+ #endif
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -700,6 +700,7 @@ struct psb_ops {
+ int (*restore_regs)(struct drm_device *dev);
+ int (*power_up)(struct drm_device *dev);
+ int (*power_down)(struct drm_device *dev);
++ void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
+
+ void (*lvds_bl_power)(struct drm_device *dev, bool on);
+ #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
--- /dev/null
+From afe1009ec742ccf5068f9a32eafa5a54080154bd Mon Sep 17 00:00:00 2001
+From: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+Date: Thu, 15 Aug 2013 00:54:44 +0200
+Subject: drm/gma500/cdv: Add and hook up chip op for disabling sr
+
+Add a callback hook to the chip ops struct to allow chips to have their
+specific self-refresh function. Currently only used by cdv.
+
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+(cherry picked from commit 75346fe9bc4c9b366c760200a665a2c55b789389)
+Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
+---
+ drivers/gpu/drm/gma500/cdv_device.c | 1 +
+ drivers/gpu/drm/gma500/cdv_device.h | 1 +
+ drivers/gpu/drm/gma500/cdv_intel_display.c | 6 +++---
+ drivers/gpu/drm/gma500/gma_display.c | 2 +-
+ drivers/gpu/drm/gma500/gma_display.h | 3 ---
+ drivers/gpu/drm/gma500/psb_drv.h | 1 +
+ 6 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/gpu/drm/gma500/cdv_device.c
++++ b/drivers/gpu/drm/gma500/cdv_device.c
+@@ -658,4 +658,5 @@ const struct psb_ops cdv_chip_ops = {
+ .power_down = cdv_power_down,
+ .power_up = cdv_power_up,
+ .update_wm = cdv_update_wm,
++ .disable_sr = cdv_disable_sr,
+ };
+--- a/drivers/gpu/drm/gma500/cdv_device.h
++++ b/drivers/gpu/drm/gma500/cdv_device.h
+@@ -27,3 +27,4 @@ extern void cdv_hdmi_init(struct drm_dev
+ extern struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
+ struct drm_crtc *crtc);
+ extern void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc);
++extern void cdv_disable_sr(struct drm_device *dev);
+--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
++++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
+@@ -511,7 +511,7 @@ static bool is_pipeb_lvds(struct drm_dev
+ return false;
+ }
+
+-void cdv_intel_disable_self_refresh(struct drm_device *dev)
++void cdv_disable_sr(struct drm_device *dev)
+ {
+ if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
+
+@@ -534,6 +534,7 @@ void cdv_intel_disable_self_refresh(stru
+
+ void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
+ {
++ struct drm_psb_private *dev_priv = dev->dev_private;
+
+ if (cdv_intel_single_pipe_active(dev)) {
+ u32 fw;
+@@ -587,8 +588,7 @@ void cdv_update_wm(struct drm_device *de
+
+ gma_wait_for_vblank(dev);
+
+- cdv_intel_disable_self_refresh(dev);
+-
++ dev_priv->ops->disable_sr(dev);
+ }
+ }
+
+--- a/drivers/gpu/drm/gma500/gma_display.c
++++ b/drivers/gpu/drm/gma500/gma_display.c
+@@ -211,7 +211,7 @@ void gma_crtc_dpms(struct drm_crtc *crtc
+ */
+
+ if (IS_CDV(dev))
+- cdv_intel_disable_self_refresh(dev);
++ dev_priv->ops->disable_sr(dev);
+
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+--- a/drivers/gpu/drm/gma500/gma_display.h
++++ b/drivers/gpu/drm/gma500/gma_display.h
+@@ -100,7 +100,4 @@ extern bool gma_pll_is_valid(struct drm_
+ extern bool gma_find_best_pll(const struct gma_limit_t *limit,
+ struct drm_crtc *crtc, int target, int refclk,
+ struct gma_clock_t *best_clock);
+-
+-/* Cedarview specific functions */
+-extern void cdv_intel_disable_self_refresh(struct drm_device *dev);
+ #endif
+--- a/drivers/gpu/drm/gma500/psb_drv.h
++++ b/drivers/gpu/drm/gma500/psb_drv.h
+@@ -701,6 +701,7 @@ struct psb_ops {
+ int (*power_up)(struct drm_device *dev);
+ int (*power_down)(struct drm_device *dev);
+ void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
++ void (*disable_sr)(struct drm_device *dev);
+
+ void (*lvds_bl_power)(struct drm_device *dev, bool on);
+ #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
patches.baytrail/1193-PENDING-mmc-sdhci-pci-Fix-BYT-sd-card-getting-stuck-.patch
+#############################################################################
+# GMA500 patches
+#
+patches.gma500/0001-drm-gma500-Add-generic-code-for-clock-calculation.patch
+patches.gma500/0002-drm-gma500-cdv-Make-use-of-the-generic-clock-code.patch
+patches.gma500/0003-drm-gma500-Make-use-of-gma_pipe_has_type.patch
+patches.gma500/0004-drm-gma500-psb-Make-use-of-generic-clock-code.patch
+patches.gma500/0005-drm-gma500-Remove-the-unused-psb_intel_display.h.patch
+patches.gma500/0006-drm-gma500-Add-generic-pipe-crtc-functions.patch
+patches.gma500/0007-drm-gma500-cdv-Use-identical-generic-crtc-funcs.patch
+patches.gma500/0008-drm-gma500-Make-all-chips-use-gma_wait_for_vblank.patch
+patches.gma500/0009-drm-gma500-psb-Use-identical-generic-crtc-funcs.patch
+patches.gma500/0010-drm-gma500-cdv-Convert-to-gma_pipe_set_base.patch
+patches.gma500/0012-drm-gma500-cdv-Convert-to-gma_crtc_dpms.patch
+patches.gma500/0013-drm-gma500-cdv-Convert-to-generic-gamma-funcs.patch
+patches.gma500/0014-drm-gma500-psb-Convert-to-gma_pipe_set_base.patch
+patches.gma500/0015-drm-gma500-Convert-to-generic-gamma-funcs.patch
+patches.gma500/0016-drm-gma500-psb-Convert-to-gma_crtc_dpms.patch
+patches.gma500/0017-drm-gma500-oak-Use-identical-generic-crtc-funcs.patch
+patches.gma500/0018-drm-gma500-mdfld-Use-identical-generic-crtc-funcs.patch
+patches.gma500/0019-drm-gma500-psb-Convert-to-generic-crtc-destroy.patch
+patches.gma500/0020-drm-gma500-Add-generic-cursor-functions.patch
+patches.gma500/0021-drm-gma500-cdv-Convert-to-generic-cursor-funcs.patch
+patches.gma500/0022-drm-gma500-psb-Convert-to-generic-cursor-funcs.patch
+patches.gma500/0023-drm-gma500-Add-generic-encoder-functions.patch
+patches.gma500/0024-drm-gma500-Convert-to-generic-encoder-funcs.patch
+patches.gma500/0025-drm-gma500-Add-generic-crtc-save-restore-funcs.patch
+patches.gma500/0026-drm-gma500-psb-Convert-to-generic-save-restore.patch
+patches.gma500/0027-drm-gma500-cdv-Convert-to-generic-save-restore.patch
+patches.gma500/0028-drm-gma500-Add-generic-set_config-function.patch
+patches.gma500/0029-drm-gma500-psb-Convert-to-generic-set_config.patch
+patches.gma500/0030-drm-gma500-cdv-Convert-to-generic-set_config.patch
+patches.gma500/0031-drm-gma500-Rename-psb_intel_crtc-to-gma_crtc.patch
+patches.gma500/0032-drm-gma500-Rename-psb_intel_connector-to-gma_connect.patch
+patches.gma500/0033-drm-gma500-Rename-psb_intel_encoder-to-gma_encoder.patch
+patches.gma500/0034-drm-gma500-Add-Minnowboard-to-the-IS_MRST-macro.patch
+patches.gma500/0035-drm-gma500-Add-chip-specific-sdvo-masks.patch
+patches.gma500/0036-drm-gma500-Add-support-for-aux-pci-vdc-device.patch
+patches.gma500/0037-drm-gma500-Add-aux-device-support-for-gmbus.patch
+patches.gma500/0038-drm-gma500-mrst-Add-SDVO-clock-calculation.patch
+patches.gma500/0039-drm-gma500-mrst-Add-aux-register-writes-when-program.patch
+patches.gma500/0040-drm-gma500-mrst-Properly-route-oaktrail-hdmi-hooks.patch
+patches.gma500/0041-drm-gma500-mrst-Add-aux-register-writes-to-SDVO.patch
+patches.gma500/0042-drm-gma500-mrst-Replace-WMs-and-chickenbits-with-val.patch
+patches.gma500/0043-drm-gma500-mrst-Setup-GMBUS-for-oaktrail-mrst.patch
+patches.gma500/0044-drm-gma500-mrst-Don-t-blindly-guess-a-mode-for-LVDS.patch
+patches.gma500/0045-drm-gma500-mrst-Add-SDVO-to-output-init.patch
+patches.gma500/0046-drm-gma500-cdv-Add-and-hook-up-chip-op-for-watermark.patch
+patches.gma500/0047-drm-gma500-cdv-Add-and-hook-up-chip-op-for-disabling.patch
+
+
#############################################################################
# Zynq SOC patches
#
projects / platform / kernel / linux-stable.git / commitdiff