struct blorp_address {
void *buffer;
- uint32_t read_domains;
- uint32_t write_domain;
+ unsigned reloc_flags;
uint32_t offset;
};
brw, &stage_state->surf_offset[
prog_data->binding_table.shader_time_start],
brw->shader_time.bo, 0, ISL_FORMAT_RAW,
- brw->shader_time.bo->size, 1, true);
+ brw->shader_time.bo->size, 1, RELOC_WRITE);
}
uint32_t *bind =
brw_state_batch(brw, prog_data->binding_table.size_bytes,
surf->addr = (struct blorp_address) {
.buffer = mt->bo,
.offset = mt->offset,
- .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
- I915_GEM_DOMAIN_SAMPLER,
- .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
};
surf->aux_usage = aux_usage;
surf->aux_surf = aux_surf;
surf->aux_addr = (struct blorp_address) {
- .read_domains = is_render_target ? I915_GEM_DOMAIN_RENDER :
- I915_GEM_DOMAIN_SAMPLER,
- .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
+ .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
};
if (mt->mcs_buf) {
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
struct brw_bo *bo = brw->compute.num_work_groups_bo;
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 0);
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 4);
- brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 8);
+ brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
+ brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
+ brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
if (brw->gen > 7)
return;
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_x_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 0);
+ brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
/* predicate = (compute_dispatch_indirect_x_size == 0); */
BEGIN_BATCH(1);
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_y_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 4);
+ brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
BEGIN_BATCH(1);
ADVANCE_BATCH();
/* Load compute_dispatch_indirect_z_size into SRC0 */
- brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 8);
+ brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
BEGIN_BATCH(1);
*/
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
- brw_load_register_mem64(brw,
- MI_PREDICATE_SRC0,
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
- 0 /* offset */);
- brw_load_register_mem64(brw,
- MI_PREDICATE_SRC1,
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0, /* write domain */
- 8 /* offset */);
+ brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
+ brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */);
}
static void
struct drm_i915_gem_relocation_entry *relocs;
int reloc_count;
int reloc_array_size;
+ unsigned int valid_reloc_flags;
/** The validation list */
struct drm_i915_gem_exec_object2 *validation_list;
void brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset);
void brw_store_register_mem32(struct brw_context *brw,
struct brw_bo *bo, uint32_t reg, uint32_t offset);
OUT_BATCH(0);
} else {
OUT_BATCH((CMD_CONST_BUFFER << 16) | (1 << 8) | (2 - 2));
- OUT_RELOC(brw->curbe.curbe_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
+ OUT_RELOC(brw->curbe.curbe_bo, 0,
(brw->curbe.total_size - 1) + brw->curbe.curbe_offset);
}
ADVANCE_BATCH();
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT,
xfb_obj->prim_count_bo,
- I915_GEM_DOMAIN_VERTEX, 0,
stream * sizeof(uint32_t));
BEGIN_BATCH(9);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (9 - 2));
indirect_flag = GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE;
brw_load_register_mem(brw, GEN7_3DPRIM_VERTEX_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 0);
brw_load_register_mem(brw, GEN7_3DPRIM_INSTANCE_COUNT, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 4);
brw_load_register_mem(brw, GEN7_3DPRIM_START_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 8);
if (prim->indexed) {
brw_load_register_mem(brw, GEN7_3DPRIM_BASE_VERTEX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 16);
} else {
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
prim->indirect_offset + 12);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2));
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->vs.base.state_offset);
+ OUT_RELOC(brw->batch.bo, 0, brw->vs.base.state_offset);
if (brw->ff_gs.prog_active)
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->ff_gs.state_offset | 1);
+ OUT_RELOC(brw->batch.bo, 0, brw->ff_gs.state_offset | 1);
else
OUT_BATCH(0);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->clip.state_offset | 1);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->sf.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->wm.base.state_offset);
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- brw->cc.state_offset);
+ OUT_RELOC(brw->batch.bo, 0, brw->clip.state_offset | 1);
+ OUT_RELOC(brw->batch.bo, 0, brw->sf.state_offset);
+ OUT_RELOC(brw->batch.bo, 0, brw->wm.base.state_offset);
+ OUT_RELOC(brw->batch.bo, 0, brw->cc.state_offset);
ADVANCE_BATCH();
brw->ctx.NewDriverState |= BRW_NEW_PSP;
(depth_surface_type << 29));
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- depth_offset);
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, depth_offset);
} else {
OUT_BATCH(0);
}
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
/* Dynamic state base address: */
- OUT_RELOC64(brw->batch.bo,
- I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.bo, 0, mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->cache.bo, 0, mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xfffff001);
* BINDING_TABLE_STATE
* SURFACE_STATE
*/
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+ OUT_RELOC(brw->batch.bo, 0, 1);
/* Dynamic state base address:
* SAMPLER_STATE
* SAMPLER_BORDER_COLOR_STATE
* Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
* Disable is clear, which we rely on)
*/
- OUT_RELOC(brw->batch.bo, (I915_GEM_DOMAIN_RENDER |
- I915_GEM_DOMAIN_INSTRUCTION), 0, 1);
+ OUT_RELOC(brw->batch.bo, 0, 1);
OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address: shader kernels (incl. SIP) */
+
+ /* Instruction base address: shader kernels (incl. SIP) */
+ OUT_RELOC(brw->cache.bo, 0, 1);
OUT_BATCH(1); /* General state upper bound */
/* Dynamic state upper bound. Although the documentation says that
BEGIN_BATCH(8);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
- OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
- 1); /* Instruction base address */
+ OUT_RELOC(brw->cache.bo, 0, 1); /* Instruction base address */
OUT_BATCH(0xfffff001); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(1); /* Instruction access upper bound */
BEGIN_BATCH(6);
OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
OUT_BATCH(1); /* General state base address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0,
- 1); /* Surface state base address */
+ OUT_RELOC(brw->batch.bo, 0, 1); /* Surface state base address */
OUT_BATCH(1); /* Indirect object base address */
OUT_BATCH(1); /* General state upper bound */
OUT_BATCH(1); /* Indirect object upper bound */
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (6 - 2));
OUT_BATCH(flags);
if (bo) {
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION, offset);
+ OUT_RELOC64(bo, RELOC_WRITE, offset);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
if (bo) {
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- gen6_gtt | offset);
+ OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, gen6_gtt | offset);
} else {
OUT_BATCH(0);
}
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | flags | (4 - 2));
if (bo) {
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
+ OUT_RELOC(bo, RELOC_WRITE, PIPE_CONTROL_GLOBAL_GTT_WRITE | offset);
} else {
OUT_BATCH(0);
}
* 3DPRIMITIVE when needed anyway.
*/
brw_load_register_mem(brw, GEN7_3DPRIM_START_INSTANCE,
- brw->workaround_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+ brw->workaround_bo, 0);
}
} else {
/* On gen4-5, a regular pipe control seems to suffice. */
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- bool rw);
+ unsigned reloc_flags);
void brw_update_texture_surface(struct gl_context *ctx,
unsigned unit, uint32_t *surf_offset,
GLenum target, struct isl_view view,
enum isl_aux_usage aux_usage,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
- unsigned read_domains, unsigned write_domains)
+ unsigned reloc_flags)
{
uint32_t tile_x = mt->level[0].level_x;
uint32_t tile_y = mt->level[0].level_y;
isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view,
.address = brw_emit_reloc(&brw->batch,
*surf_offset + brw->isl_dev.ss.addr_offset,
- mt->bo, offset, read_domains, write_domains),
+ mt->bo, offset, reloc_flags),
.aux_surf = aux_surf, .aux_usage = aux_usage,
.aux_address = aux_offset,
.mocs = mocs, .clear_color = clear_color,
*surf_offset +
brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr,
- read_domains, write_domains);
+ reloc_flags);
}
}
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
rb_mocs[brw->gen],
&offset, surf_index,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ RELOC_WRITE);
return offset;
}
brw_emit_surface_state(brw, mt, mt->target, view, aux_usage,
tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ 0);
}
}
unsigned surface_format,
unsigned buffer_size,
unsigned pitch,
- bool rw)
+ unsigned reloc_flags)
{
uint32_t *dw = brw_state_batch(brw,
brw->isl_dev.ss.size,
brw_emit_reloc(&brw->batch,
*out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0)),
+ reloc_flags),
.size = buffer_size,
.format = surface_format,
.stride = pitch,
isl_format,
size,
texel_size,
- false /* rw */);
+ 0);
}
/**
{
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
ISL_FORMAT_R32G32B32A32_FLOAT,
- size, 1, false);
+ size, 1, 0);
}
/**
*/
brw_emit_buffer_surface_state(brw, out_offset, bo, offset,
ISL_FORMAT_RAW,
- size, 1, true);
+ size, 1, RELOC_WRITE);
}
/**
surface_format << BRW_SURFACE_FORMAT_SHIFT |
BRW_SURFACE_RC_READ_WRITE;
surf[1] = brw_emit_reloc(&brw->batch,
- *out_offset + 4, bo, offset_bytes,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ *out_offset + 4, bo, offset_bytes, RELOC_WRITE);
surf[2] = (width << BRW_SURFACE_WIDTH_SHIFT |
height << BRW_SURFACE_HEIGHT_SHIFT);
surf[3] = (depth << BRW_SURFACE_DEPTH_SHIFT |
1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT);
}
surf[1] = !bo ? 0 :
- brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0, RELOC_WRITE);
+
surf[2] = ((width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
intel_renderbuffer_get_tile_offsets(irb,
&tile_x,
&tile_y),
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
+ RELOC_WRITE);
surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
(rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);
brw_emit_surface_state(brw, irb->mt, target, view, aux_usage,
tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ 0);
} else {
brw->vtbl.emit_null_surface_state(
brw_emit_buffer_surface_state(brw, &surf_offsets[i], bo,
binding->Offset, ISL_FORMAT_RAW,
- bo->size - binding->Offset, 1, true);
+ bo->size - binding->Offset, 1,
+ RELOC_WRITE);
}
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
brw_emit_buffer_surface_state(
brw, surf_offset, intel_obj->buffer, obj->BufferOffset,
format, intel_obj->Base.Size, texel_size,
- access != GL_READ_ONLY);
+ access != GL_READ_ONLY ? RELOC_WRITE : 0);
update_buffer_image_param(brw, u, surface_idx, param);
brw_emit_buffer_surface_state(
brw, surf_offset, mt->bo, mt->offset,
format, mt->bo->size - mt->offset, 1 /* pitch */,
- access != GL_READ_ONLY);
+ access != GL_READ_ONLY ? RELOC_WRITE : 0);
} else {
const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
brw_emit_surface_state(brw, mt, mt->target, view,
ISL_AUX_USAGE_NONE, tex_mocs[brw->gen],
surf_offset, surf_index,
- I915_GEM_DOMAIN_SAMPLER,
- access == GL_READ_ONLY ? 0 :
- I915_GEM_DOMAIN_SAMPLER);
+ access == GL_READ_ONLY ? 0 : RELOC_WRITE);
}
isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view);
brw_emit_buffer_surface_state(brw, surf_offset,
bo, bo_offset,
ISL_FORMAT_RAW,
- 3 * sizeof(GLuint), 1, true);
+ 3 * sizeof(GLuint), 1,
+ RELOC_WRITE);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
}
return (struct blorp_address) {
.buffer = brw->batch.bo,
.offset = offset,
- .write_domain = 0,
- .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
};
}
return (struct blorp_address) {
.buffer = brw->cache.bo,
.offset = offset,
- .write_domain = 0,
- .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
};
}
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
} else {
OUT_BATCH(0);
}
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
OUT_BATCH(depth_mt->hiz_buf->surf.row_pitch - 1);
- OUT_RELOC(depth_mt->hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
OUT_BATCH(stencil_mt->surf.row_pitch - 1);
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- offset);
+ OUT_RELOC(stencil_mt->bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
/* 3DSTATE_DEPTH_BUFFER dw2 */
if (depth_mt) {
- OUT_RELOC(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
} else {
OUT_BATCH(0);
}
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
OUT_BATCH((mocs << 25) |
(depth_mt->hiz_buf->pitch - 1));
- OUT_RELOC(depth_mt->hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
OUT_BATCH(enabled |
mocs << 25 |
(stencil_mt->surf.row_pitch - 1));
- OUT_RELOC(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
+ OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
ADVANCE_BATCH();
}
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- i * sizeof(uint32_t));
+ OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
BEGIN_BATCH(3);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- i * sizeof(uint32_t));
+ OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
depthbuffer_format << 18 |
(depth_mt ? depth_mt->surf.row_pitch - 1 : 0));
if (depth_mt) {
- OUT_RELOC64(depth_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->bo, RELOC_WRITE, 0);
} else {
OUT_BATCH(0);
OUT_BATCH(0);
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
- OUT_RELOC64(depth_mt->hiz_buf->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
OUT_BATCH(depth_mt->hiz_buf->qpitch >> 2);
ADVANCE_BATCH();
}
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
(stencil_mt->surf.row_pitch - 1));
- OUT_RELOC64(stencil_mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_RELOC64(stencil_mt->bo, RELOC_WRITE, 0);
OUT_BATCH(stencil_mt->surf.array_pitch_el_rows >> 2);
ADVANCE_BATCH();
}
uint32_t offset = (char *)location - (char *)brw->batch.map;
return brw_emit_reloc(&brw->batch, offset,
address.buffer, address.offset + delta,
- address.read_domains,
- address.write_domain);
+ address.reloc_flags);
}
static void
uint64_t reloc_val =
brw_emit_reloc(&brw->batch, ss_offset, bo, address.offset + delta,
- address.read_domains, address.write_domain);
+ address.reloc_flags);
void *reloc_ptr = (void *)brw->batch.map + ss_offset;
#if GEN_GEN >= 8
*addr = (struct blorp_address) {
.buffer = brw->batch.bo,
- .read_domains = I915_GEM_DOMAIN_VERTEX,
- .write_domain = 0,
.offset = offset,
};
struct brw_address {
struct brw_bo *bo;
- uint32_t read_domains;
- uint32_t write_domain;
+ unsigned reloc_flags;
uint32_t offset;
};
return brw_emit_reloc(&brw->batch, offset, address.bo,
address.offset + delta,
- address.read_domains,
- address.write_domain);
+ address.reloc_flags);
}
#define __gen_address_type struct brw_address
return (struct brw_address) {
.bo = bo,
.offset = offset,
- .read_domains = I915_GEM_DOMAIN_RENDER,
- .write_domain = I915_GEM_DOMAIN_RENDER,
+ .reloc_flags = RELOC_WRITE,
};
}
return (struct brw_address) {
.bo = bo,
.offset = offset,
- .read_domains = I915_GEM_DOMAIN_RENDER,
- .write_domain = 0,
};
}
return (struct brw_address) {
.bo = bo,
.offset = offset,
- .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
- .write_domain = I915_GEM_DOMAIN_INSTRUCTION,
+ .reloc_flags = RELOC_WRITE | RELOC_NEEDS_GGTT,
};
}
return (struct brw_address) {
.bo = bo,
.offset = offset,
- .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
- .write_domain = 0,
};
}
return (struct brw_address) {
.bo = bo,
.offset = offset,
- .read_domains = I915_GEM_DOMAIN_VERTEX,
- .write_domain = 0,
};
}
brw, &stage_state->surf_offset[
prog_data->binding_table.shader_time_start],
brw->shader_time.bo, 0, ISL_FORMAT_RAW,
- brw->shader_time.bo->size, 1, true);
+ brw->shader_time.bo->size, 1,
+ RELOC_WRITE);
}
uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
if (GEN_GEN < 6) {
samp_st.BorderColorPointer =
brw_emit_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
- brw->batch.bo, border_color_offset,
- I915_GEM_DOMAIN_SAMPLER, 0);
+ brw->batch.bo, border_color_offset, 0);
} else {
samp_st.BorderColorPointer = border_color_offset;
}
{
int offset = idx * sizeof(uint64_t) * 4;
- brw_load_register_mem64(brw,
- HSW_CS_GPR(1),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ brw_load_register_mem64(brw, HSW_CS_GPR(1), query->bo, offset);
offset += sizeof(uint64_t);
- brw_load_register_mem64(brw,
- HSW_CS_GPR(2),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ brw_load_register_mem64(brw, HSW_CS_GPR(2), query->bo, offset);
offset += sizeof(uint64_t);
- brw_load_register_mem64(brw,
- HSW_CS_GPR(3),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ brw_load_register_mem64(brw, HSW_CS_GPR(3), query->bo, offset);
offset += sizeof(uint64_t);
- brw_load_register_mem64(brw,
- HSW_CS_GPR(4),
- query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ brw_load_register_mem64(brw, HSW_CS_GPR(4), query->bo, offset);
}
/*
brw_load_register_mem64(brw,
HSW_CS_GPR(0),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
2 * sizeof(uint64_t));
return;
}
brw_load_register_mem64(brw,
HSW_CS_GPR(0),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
0 * sizeof(uint64_t));
} else if (query->Base.Target == GL_TRANSFORM_FEEDBACK_STREAM_OVERFLOW_ARB
|| query->Base.Target == GL_TRANSFORM_FEEDBACK_OVERFLOW_ARB) {
brw_load_register_mem64(brw,
HSW_CS_GPR(1),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
0 * sizeof(uint64_t));
brw_load_register_mem64(brw,
HSW_CS_GPR(2),
query->bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
1 * sizeof(uint64_t));
BEGIN_BATCH(5);
/* Load query availability into SRC0 */
brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
2 * sizeof(uint64_t));
/* predicate = !(query_availability == 0); */
(cmd_size - 2));
OUT_BATCH(reg + 4 * i);
if (brw->gen >= 8) {
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+ OUT_RELOC64(bo, RELOC_WRITE, offset + 4 * i);
} else {
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION, offset + 4 * i);
+ OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset + 4 * i);
}
}
ADVANCE_BATCH();
/* GPR0 = Tally */
brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
brw_load_register_mem(brw, HSW_CS_GPR(0), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
TALLY_OFFSET + i * sizeof(uint32_t));
if (!obj->base.Paused) {
/* GPR1 = Start Snapshot */
brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- I915_GEM_DOMAIN_INSTRUCTION,
START_OFFSET + i * sizeof(uint64_t));
/* GPR2 = Ending Snapshot */
brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i), HSW_CS_GPR(2));
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- i * sizeof(uint32_t));
+ OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
}
BEGIN_BATCH(3);
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
- OUT_RELOC(brw_obj->offset_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- i * sizeof(uint32_t));
+ OUT_RELOC(brw_obj->offset_bo, RELOC_WRITE, i * sizeof(uint32_t));
ADVANCE_BATCH();
}
}
batch->use_batch_first =
brw->screen->kernel_features & KERNEL_ALLOWS_EXEC_BATCH_FIRST;
+ /* PIPE_CONTROL needs a w/a but only on gen6 */
+ batch->valid_reloc_flags = EXEC_OBJECT_WRITE;
+ if (brw->gen == 6)
+ batch->valid_reloc_flags |= EXEC_OBJECT_NEEDS_GTT;
+
intel_batchbuffer_reset(batch, bufmgr, has_llc);
}
uint64_t
brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
struct brw_bo *target, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain)
+ unsigned int reloc_flags)
{
assert(target != NULL);
/* Check args */
assert(batch_offset <= BATCH_SZ - sizeof(uint32_t));
- assert(_mesa_bitcount(write_domain) <= 1);
unsigned int index = add_exec_bo(batch, target);
struct drm_i915_gem_exec_object2 *entry = &batch->validation_list[index];
- if (write_domain) {
- entry->flags |= EXEC_OBJECT_WRITE;
-
- /* PIPECONTROL needs a w/a on gen6 */
- if (write_domain == I915_GEM_DOMAIN_INSTRUCTION) {
- struct brw_context *brw = container_of(batch, brw, batch);
- if (brw->gen == 6)
- entry->flags |= EXEC_OBJECT_NEEDS_GTT;
- }
- }
+ if (reloc_flags)
+ entry->flags |= reloc_flags & batch->valid_reloc_flags;
batch->relocs[batch->reloc_count++] =
(struct drm_i915_gem_relocation_entry) {
load_sized_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset,
int size)
{
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC64(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC64(bo, 0, offset + i * 4);
}
ADVANCE_BATCH();
} else {
for (i = 0; i < size; i++) {
OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + i * 4);
- OUT_RELOC(bo, read_domains, write_domain, offset + i * 4);
+ OUT_RELOC(bo, 0, offset + i * 4);
}
ADVANCE_BATCH();
}
brw_load_register_mem(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 1);
+ load_sized_register_mem(brw, reg, bo, offset, 1);
}
void
brw_load_register_mem64(struct brw_context *brw,
uint32_t reg,
struct brw_bo *bo,
- uint32_t read_domains, uint32_t write_domain,
uint32_t offset)
{
- load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2);
+ load_sized_register_mem(brw, reg, bo, offset, 2);
}
/*
BEGIN_BATCH(4);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, RELOC_WRITE, offset);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset);
ADVANCE_BATCH();
}
}
BEGIN_BATCH(8);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg);
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, RELOC_WRITE, offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
+ OUT_RELOC64(bo, RELOC_WRITE, offset + sizeof(uint32_t));
ADVANCE_BATCH();
} else {
BEGIN_BATCH(6);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset + sizeof(uint32_t));
+ OUT_RELOC(bo, RELOC_WRITE | RELOC_NEEDS_GGTT, offset + sizeof(uint32_t));
ADVANCE_BATCH();
}
}
BEGIN_BATCH(4);
OUT_BATCH(MI_STORE_DATA_IMM | (4 - 2));
if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, RELOC_WRITE, offset);
else {
OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, RELOC_WRITE, offset);
}
OUT_BATCH(imm);
ADVANCE_BATCH();
BEGIN_BATCH(5);
OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
if (brw->gen >= 8)
- OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC64(bo, 0, offset);
else {
OUT_BATCH(0); /* MBZ */
- OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- offset);
+ OUT_RELOC(bo, RELOC_WRITE, offset);
}
OUT_BATCH(imm & 0xffffffffu);
OUT_BATCH(imm >> 32);
bool brw_batch_references(struct intel_batchbuffer *batch, struct brw_bo *bo);
-uint64_t brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
- struct brw_bo *target, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain);
+#define RELOC_WRITE EXEC_OBJECT_WRITE
+#define RELOC_NEEDS_GGTT EXEC_OBJECT_NEEDS_GTT
+uint64_t brw_emit_reloc(struct intel_batchbuffer *batch,
+ uint32_t batch_offset,
+ struct brw_bo *target,
+ uint32_t target_offset,
+ unsigned flags);
#define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
#define OUT_BATCH(d) *__map++ = (d)
#define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
-#define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
+#define OUT_RELOC(buf, flags, delta) do { \
uint32_t __offset = (__map - brw->batch.map) * 4; \
uint32_t reloc = \
- brw_emit_reloc(&brw->batch, __offset, (buf), (delta), \
- (read_domains), (write_domain)); \
+ brw_emit_reloc(&brw->batch, __offset, (buf), (delta), (flags)); \
OUT_BATCH(reloc); \
} while (0)
/* Handle 48-bit address relocations for Gen8+ */
-#define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
+#define OUT_RELOC64(buf, flags, delta) do { \
uint32_t __offset = (__map - brw->batch.map) * 4; \
uint64_t reloc64 = \
- brw_emit_reloc(&brw->batch, __offset, (buf), (delta), \
- (read_domains), (write_domain)); \
+ brw_emit_reloc(&brw->batch, __offset, (buf), (delta), (flags)); \
OUT_BATCH(reloc64); \
OUT_BATCH(reloc64 >> 32); \
} while (0)
OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
}
OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
OUT_BATCH((uint16_t)src_pitch);
if (brw->gen >= 8) {
- OUT_RELOC64(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC64(src_buffer, 0, src_offset);
} else {
- OUT_RELOC(src_buffer,
- I915_GEM_DOMAIN_RENDER, 0,
- src_offset);
+ OUT_RELOC(src_buffer, 0, src_offset);
}
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
if (brw->gen >= 8) {
- OUT_RELOC64(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
} else {
- OUT_RELOC(dst_buffer,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- dst_offset);
+ OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
}
OUT_BATCH(0); /* bg */
OUT_BATCH(fg_color); /* fg */
OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
SET_FIELD(x + chunk_x + chunk_w, BLT_X));
if (brw->gen >= 8) {
- OUT_RELOC64(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- mt->offset + offset);
+ OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
} else {
- OUT_RELOC(mt->bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- mt->offset + offset);
+ OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
}
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
projects / platform / upstream / mesa.git / commitdiff