return 0;
}
+static int
+i915_ioctl_gem_userptr(int fd, unsigned long request, void *arg)
+{
+ struct shim_fd *shim_fd = drm_shim_fd_lookup(fd);
+ struct drm_i915_gem_userptr *userptr = arg;
+ struct i915_bo *bo = calloc(1, sizeof(*bo));
+
+ drm_shim_bo_init(&bo->base, userptr->user_size);
+
+ userptr->handle = drm_shim_bo_get_handle(shim_fd, &bo->base);
+
+ drm_shim_bo_put(&bo->base);
+
+ return 0;
+}
+
static int
i915_ioctl_gem_context_create(int fd, unsigned long request, void *arg)
{
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
*gp->value = true;
return 0;
+ case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
+ *gp->value = false;
+ return 0;
case I915_PARAM_CMD_PARSER_VERSION:
/* Most recent version in drivers/gpu/drm/i915/i915_cmd_parser.c */
*gp->value = 10;
[DRM_I915_GEM_EXECBUFFER2] = i915_ioctl_noop,
[DRM_I915_GEM_EXECBUFFER2_WR] = i915_ioctl_noop,
+ [DRM_I915_GEM_USERPTR] = i915_ioctl_gem_userptr,
+
[DRM_I915_GEM_GET_APERTURE] = i915_gem_get_aperture,
[DRM_I915_REG_READ] = i915_ioctl_noop,
[DRM_I915_GEM_SET_DOMAIN] = i915_ioctl_noop,
[DRM_I915_GEM_GET_CACHING] = i915_ioctl_noop,
[DRM_I915_GEM_SET_CACHING] = i915_ioctl_noop,
+ [DRM_I915_GEM_GET_TILING] = i915_ioctl_noop,
[DRM_I915_GEM_MADVISE] = i915_ioctl_noop,
[DRM_I915_GEM_WAIT] = i915_ioctl_noop,
[DRM_I915_GEM_BUSY] = i915_ioctl_noop,