// TODO: verify we have properly encoded deopt arguments
} break;
- case TargetOpcode::INSERT_SUBREG: {
- unsigned InsertedSize =
- TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
- unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
- if (InsertedSize != SubRegSize) {
- report("INSERT_SUBREG expected matching subreg size for operand 2", MI);
- break;
- }
- } break;
}
}
%2 = PHI %1, %bb.2, %0, %bb.1
%17 = IMPLICIT_DEF
- %16 = INSERT_SUBREG %17, %2, %subreg.sub_8bit_hi
+ %16 = INSERT_SUBREG %17, %2, 1
%18 = COPY %16
%19 = COPY %6
%21 = IMPLICIT_DEF
%18 = ADD8rr %17, %14, implicit-def dead $eflags
%8 = IMPLICIT_DEF
- %9 = INSERT_SUBREG %8, %18, %subreg.sub_8bit_hi
+ %9 = INSERT_SUBREG %8, %18, 1
%10 = COPY %9
%11 = VMOVAPDZrrk %2, killed %10, %1
VMOVAPDZmr %0, 1, $noreg, 0, $noreg, killed %11
%17 = XOR16rr %16, %12, implicit-def dead $eflags
%8 = IMPLICIT_DEF
- %9 = INSERT_SUBREG %8, %17, %subreg.sub_16bit
+ %9 = INSERT_SUBREG %8, %17, 3
%10 = COPY %9
%11 = VMOVAPSZrrk %2, killed %10, %1
VMOVAPSZmr %0, 1, $noreg, 0, $noreg, killed %11
+++ /dev/null
-#RUN: not --crash llc -march=aarch64 -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
-# REQUIRES: aarch64-registered-target
-
----
-name: test_insert_subreg
-legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-liveins:
-body: |
- bb.0:
- liveins: $s0, $h1
-
- %0:fpr32 = COPY $s0
-
- ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
- %1:fpr128 = IMPLICIT_DEF
- %2:fpr128 = INSERT_SUBREG %1:fpr128, %0:fpr32, %subreg.hsub
-
- ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
- %3:fpr128 = IMPLICIT_DEF
- %4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
-
- ; CHECK-NOT: *** Bad machine code:
- %7:fpr128 = IMPLICIT_DEF
- %8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
-
-...