[ARM GlobalISel] Support G_CONSTANT for Thumb2

All we have to do is mark it as legal.

This allows us to select a lot of new patterns handled by TableGen. This
patch adds tests for them and splits up the existing test file for
binary operators into 2 files, one for arithmetic ops and one for
logical ones.

llvm-svn: 349610

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index ec613dd..4a0c24d 100644 (file)
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -92,6 +92,10 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
   getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});
 
+  getActionDefinitionsBuilder(G_CONSTANT)
+      .legalFor({s32, p0})
+      .clampScalar(0, s32, s32);
+
   // We're keeping these builders around because we'll want to add support for
   // floating point to them.
   auto &LoadStoreBuilder =
@@ -157,10 +161,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
 
   getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
 
-  getActionDefinitionsBuilder(G_CONSTANT)
-      .legalFor({s32, p0})
-      .clampScalar(0, s32, s32);
-
   getActionDefinitionsBuilder(G_ICMP)
       .legalForCartesianProduct({s1}, {s32, p0})
       .minScalar(1, s32);

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir
new file mode 100644 (file)
index 0000000..d3248fe
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-consts.mir
@@ -0,0 +1,57 @@
+# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+  define void @test_constants() { ret void }
+...
+---
+name:            test_constants
+# CHECK-LABEL: name: test_constants
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %4(p0) = COPY $r0
+
+    %0(s32) = G_CONSTANT 42
+    ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
+
+    %1(s16) = G_CONSTANT i16 21
+    G_STORE %1(s16), %4(p0) :: (store 2)
+    ; CHECK-NOT: G_CONSTANT i16
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
+    ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32)
+    ; CHECK-NOT: G_CONSTANT i16
+
+    %2(s8) = G_CONSTANT i8 10
+    G_STORE %2(s8), %4(p0) :: (store 1)
+    ; CHECK-NOT: G_CONSTANT i8
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+    ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32)
+    ; CHECK-NOT: G_CONSTANT i8
+
+    %3(s1) = G_CONSTANT i1 1
+    G_STORE %3(s1), %4(p0) :: (store 1)
+    ; CHECK-NOT: G_CONSTANT i1
+    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
+    ; CHECK-NOT: G_CONSTANT i1
+
+    %5(p0) = G_CONSTANT 0
+    G_STORE %5(p0), %4(p0) :: (store 4)
+    ; CHECK: {{%[0-9]+}}:_(p0) = G_CONSTANT 0
+
+    $r0 = COPY %0(s32)
+    BX_RET 14, $noreg, implicit $r0
+...

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 0d65fca..bee8b7b 100644 (file)
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -9,7 +9,7 @@
 
   define void @test_gep() { ret void }
 
-  define void @test_constants() { ret void }
+  define void @test_constants_s64() { ret void }
 
   define void @test_icmp_s8() { ret void }
   define void @test_icmp_s16() { ret void }
@@ -189,8 +189,8 @@ body:             |
     BX_RET 14, $noreg, implicit $r0
 ...
 ---
-name:            test_constants
-# CHECK-LABEL: name: test_constants
+name:            test_constants_s64
+# CHECK-LABEL: name: test_constants_s64
 legalized:       false
 # CHECK: legalized: true
 regBankSelected: false
@@ -201,55 +201,21 @@ registers:
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
-  - { id: 6, class: _ }
-  - { id: 7, class: _ }
-  - { id: 8, class: _ }
 body:             |
   bb.0:
     liveins: $r0
 
-    %4(p0) = COPY $r0
-
-    %0(s32) = G_CONSTANT 42
-    ; CHECK: {{%[0-9]+}}:_(s32) = G_CONSTANT 42
-
-    %1(s16) = G_CONSTANT i16 21
-    G_STORE %1(s16), %4(p0) :: (store 2)
-    ; CHECK-NOT: G_CONSTANT i16
-    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
-    ; CHECK: {{%[0-9]+}}:_(s16) = G_TRUNC [[EXT]](s32)
-    ; CHECK-NOT: G_CONSTANT i16
-
-    %2(s8) = G_CONSTANT i8 10
-    G_STORE %2(s8), %4(p0) :: (store 1)
-    ; CHECK-NOT: G_CONSTANT i8
-    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
-    ; CHECK: {{%[0-9]+}}:_(s8) = G_TRUNC [[EXT]](s32)
-    ; CHECK-NOT: G_CONSTANT i8
-
-    %3(s1) = G_CONSTANT i1 1
-    G_STORE %3(s1), %4(p0) :: (store 1)
-    ; CHECK-NOT: G_CONSTANT i1
-    ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
-    ; CHECK: {{%[0-9]+}}:_(s1) = G_TRUNC [[EXT]](s32)
-    ; CHECK-NOT: G_CONSTANT i1
-
-    %5(p0) = G_CONSTANT 0
-    G_STORE %5(p0), %4(p0) :: (store 4)
-    ; CHECK: {{%[0-9]+}}:_(p0) = G_CONSTANT 0
-
-    %6(s64) = G_CONSTANT i64 17179869200 ; = 4 * 2 ^ 32 + 16
-    %7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
-    G_STORE %7(s32), %4(p0) :: (store 4)
-    G_STORE %8(s32), %4(p0) :: (store 4)
+    %0(p0) = COPY $r0
+
+    %1(s64) = G_CONSTANT i64 17179869200 ; = 4 * 2 ^ 32 + 16
+    %2(s32), %3(s32) = G_UNMERGE_VALUES %1(s64)
+    G_STORE %2(s32), %0(p0) :: (store 4)
+    G_STORE %3(s32), %0(p0) :: (store 4)
     ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 4
     ; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_CONSTANT i32 16
     ; CHECK-NOT: G_CONSTANT i64
 
-    $r0 = COPY %0(s32)
-    BX_RET 14, $noreg, implicit $r0
+    BX_RET 14, $noreg
 ...
 ---
 name:            test_icmp_s8

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
new file mode 100644 (file)
index 0000000..cf42a81
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir
@@ -0,0 +1,251 @@
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+  define void @test_add_regs() { ret void }
+  define void @test_add_fold_imm() { ret void }
+  define void @test_add_fold_imm12() { ret void }
+  define void @test_add_no_fold_imm() { ret void }
+
+  define void @test_sub_imm_lhs() { ret void }
+  define void @test_sub_imm_rhs() { ret void }
+
+  define void @test_mul() { ret void }
+  define void @test_mla() { ret void }
+...
+---
+name:            test_add_regs
+# CHECK-LABEL: name: test_add_regs
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+
+    %1(s32) = COPY $r1
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = G_ADD %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_add_fold_imm
+# CHECK-LABEL: name: test_add_fold_imm
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    %2(s32) = G_ADD %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_add_fold_imm12
+# CHECK-LABEL: name: test_add_fold_imm12
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 4093
+    %2(s32) = G_ADD %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDri12 [[VREGX]], 4093, 14, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_add_no_fold_imm
+# CHECK-LABEL: name: test_add_no_fold_imm
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
+
+    %2(s32) = G_ADD %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_sub_imm_lhs
+# CHECK-LABEL: name: test_sub_imm_lhs
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    %2(s32) = G_SUB %1, %0
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2RSBri [[VREGX]], 786444, 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_sub_imm_rhs
+# CHECK-LABEL: name: test_sub_imm_rhs
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    %2(s32) = G_SUB %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_mul
+# CHECK-LABEL: name: test_mul
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = COPY $r1
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = G_MUL %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MUL [[VREGX]], [[VREGY]], 14, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_mla
+# CHECK-LABEL: name: test_mla
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1, $r2
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = COPY $r1
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = COPY $r2
+    ; CHECK: [[VREGZ:%[0-9]+]]:rgpr = COPY $r2
+
+    %3(s32) = G_MUL %0, %1
+    %4(s32) = G_ADD %3, %2
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
+
+    $r0 = COPY %4(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-binops.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-binops.mir
deleted file mode 100644 (file)
index f71cc1c..0000000
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-binops.mir
+++ /dev/null
@@ -1,135 +0,0 @@
-# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
---- |
-  define void @test_add_regs() { ret void }
-
-  define void @test_mul() { ret void }
-  define void @test_mla() { ret void }
-
-  define void @test_and_regs() { ret void }
-...
----
-name:            test_add_regs
-# CHECK-LABEL: name: test_add_regs
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(s32) = COPY $r0
-    ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0
-
-    %1(s32) = COPY $r1
-    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
-
-    %2(s32) = G_ADD %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
-
-    $r0 = COPY %2(s32)
-    ; CHECK: $r0 = COPY [[VREGRES]]
-
-    BX_RET 14, $noreg, implicit $r0
-    ; CHECK: BX_RET 14, $noreg, implicit $r0
-...
----
-name:            test_mul
-# CHECK-LABEL: name: test_mul
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(s32) = COPY $r0
-    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
-
-    %1(s32) = COPY $r1
-    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
-
-    %2(s32) = G_MUL %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MUL [[VREGX]], [[VREGY]], 14, $noreg
-
-    $r0 = COPY %2(s32)
-    ; CHECK: $r0 = COPY [[VREGRES]]
-
-    BX_RET 14, $noreg, implicit $r0
-    ; CHECK: BX_RET 14, $noreg, implicit $r0
-...
----
-name:            test_mla
-# CHECK-LABEL: name: test_mla
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-  - { id: 3, class: gprb }
-  - { id: 4, class: gprb }
-body:             |
-  bb.0:
-    liveins: $r0, $r1, $r2
-
-    %0(s32) = COPY $r0
-    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
-
-    %1(s32) = COPY $r1
-    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
-
-    %2(s32) = COPY $r2
-    ; CHECK: [[VREGZ:%[0-9]+]]:rgpr = COPY $r2
-
-    %3(s32) = G_MUL %0, %1
-    %4(s32) = G_ADD %3, %2
-    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg
-
-    $r0 = COPY %4(s32)
-    ; CHECK: $r0 = COPY [[VREGRES]]
-
-    BX_RET 14, $noreg, implicit $r0
-    ; CHECK: BX_RET 14, $noreg, implicit $r0
-...
----
-name:            test_and_regs
-# CHECK-LABEL: name: test_and_regs
-legalized:       true
-regBankSelected: true
-selected:        false
-# CHECK: selected: true
-registers:
-  - { id: 0, class: gprb }
-  - { id: 1, class: gprb }
-  - { id: 2, class: gprb }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(s32) = COPY $r0
-    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
-
-    %1(s32) = COPY $r1
-    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
-
-    %2(s32) = G_AND %0, %1
-    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
-
-    $r0 = COPY %2(s32)
-    ; CHECK: $r0 = COPY [[VREGRES]]
-
-    BX_RET 14, $noreg, implicit $r0
-    ; CHECK: BX_RET 14, $noreg, implicit $r0
-...

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir
new file mode 100644 (file)
index 0000000..4979491
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir
@@ -0,0 +1,66 @@
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+  define void @test_movi() { ret void }
+  define void @test_movi16() { ret void }
+  define void @test_movi32() { ret void }
+...
+---
+name:            test_movi
+# CHECK-LABEL: name: test_movi
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0:
+    %0(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi 786444, 14, $noreg, $noreg
+
+    $r0 = COPY %0(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_movi16
+# CHECK-LABEL: name: test_movi16
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0:
+    %0(s32) = G_CONSTANT i32 65533
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi16 65533, 14, $noreg
+
+    $r0 = COPY %0(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_movi32
+# CHECK-LABEL: name: test_movi32
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+body:             |
+  bb.0:
+    %0(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
+
+    $r0 = COPY %0(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...

diff --git a/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
new file mode 100644 (file)
index 0000000..d63c599
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir
@@ -0,0 +1,219 @@
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+  define void @test_and_regs() { ret void }
+  define void @test_and_imm() { ret void }
+
+  define void @test_bfc() { ret void }
+  define void @test_no_bfc_bad_mask() { ret void }
+
+  define void @test_mvn() { ret void }
+  define void @test_bic() { ret void }
+  define void @test_orn() { ret void }
+...
+---
+name:            test_and_regs
+# CHECK-LABEL: name: test_and_regs
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = COPY $r1
+    ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = G_AND %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_and_imm
+# CHECK-LABEL: name: test_and_imm
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    %2(s32) = G_AND %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDri [[VREGX]], 786444, 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_bfc
+# CHECK-LABEL: name: test_bfc
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007
+    %2(s32) = G_AND %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BFC [[VREGX]], -65529, 14, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_no_bfc_bad_mask
+# CHECK-LABEL: name: test_no_bfc_bad_mask
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
+    %2(s32) = G_AND %0, %1
+    ; CHECK-NOT: t2BFC
+
+    $r0 = COPY %2(s32)
+
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_mvn
+# CHECK-LABEL: name: test_mvn
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0
+
+    %0(s32) = COPY $r0
+    ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+
+    %1(s32) = G_CONSTANT i32 -1
+    %2(s32) = G_XOR %0, %1
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MVNr [[VREGX]], 14, $noreg, $noreg
+
+    $r0 = COPY %2(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_bic
+# CHECK-LABEL: name: test_bic
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    ; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+    ; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = G_CONSTANT i32 -1
+    %3(s32) = G_XOR %1, %2
+
+    %4(s32) = G_AND %0, %3
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+
+    $r0 = COPY %4(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_orn
+# CHECK-LABEL: name: test_orn
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+  - { id: 4, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    ; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
+    ; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1
+
+    %2(s32) = G_CONSTANT i32 -1
+    %3(s32) = G_XOR %1, %2
+
+    %4(s32) = G_OR %0, %3
+    ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ORNrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg
+
+    $r0 = COPY %4(s32)
+    ; CHECK: $r0 = COPY [[VREGRES]]
+
+    BX_RET 14, $noreg, implicit $r0
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+...