arm64: dts: mt8195: Add dp-intf nodes

Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.

Dp-intf0 is for edptx and dp-intf1 is for dptx.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20221110063716.25677-2-rex-bc.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e078703..62a1d06 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2244,6 +2244,17 @@
                        mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
                };
 
+               dp_intf0: dp-intf@1c015000 {
+                       compatible = "mediatek,mt8195-dp-intf";
+                       reg = <0 0x1c015000 0 0x1000>;
+                       interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+                       clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
+                                <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+                                <&apmixedsys CLK_APMIXED_TVDPLL1>;
+                       clock-names = "engine", "pixel", "pll";
+                       status = "disabled";
+               };
+
                mutex: mutex@1c016000 {
                        compatible = "mediatek,mt8195-disp-mutex";
                        reg = <0 0x1c016000 0 0x1000>;
@@ -2332,5 +2343,17 @@
                        clock-names = "apb", "smi", "gals";
                        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
                };
+
+               dp_intf1: dp-intf@1c113000 {
+                       compatible = "mediatek,mt8195-dp-intf";
+                       reg = <0 0x1c113000 0 0x1000>;
+                       interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+                       clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+                                <&vdosys1 CLK_VDO1_DPINTF>,
+                                <&apmixedsys CLK_APMIXED_TVDPLL2>;
+                       clock-names = "engine", "pixel", "pll";
+                       status = "disabled";
+               };
        };
 };