.. doxygenstruct:: nir_alu_src
:members:
-.. doxygenstruct:: nir_alu_dest
- :members:
-
NIR ALU Opcode Reference:
-------------------------
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.divergent)
+ if (alu->def.divergent)
return NULL;
/* Ignore uniform floats because they regress VGPR usage too much */
if (nir_op_infos[alu->op].output_type & nir_type_float)
return NULL;
- return &alu->dest.dest.ssa;
+ return &alu->def;
}
case nir_instr_type_intrinsic: {
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
return false;
}
- unsigned num_components = instr->dest.dest.ssa.num_components;
+ unsigned num_components = instr->def.num_components;
nir_scalar components[NIR_MAX_VEC_COMPONENTS];
coord_info infos[NIR_MAX_VEC_COMPONENTS];
bool can_move_all = true;
for (unsigned i = 0; i < num_components; i++) {
- components[i] = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&instr->dest.dest.ssa, i), 0);
+ components[i] = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&instr->def, i), 0);
components[i] = nir_scalar_chase_movs(components[i]);
can_move_all &= can_move_coord(components[i], &infos[i]);
}
nir_def *def = nir_vec_scalars(&state->toplevel_b, components, num_components);
def = nir_build_alu1(&state->toplevel_b, instr->op, def);
- nir_def_rewrite_uses(&instr->dest.dest.ssa, def);
+ nir_def_rewrite_uses(&instr->def, def);
state->num_wqm_vgprs += num_components;
Temp src1 = get_alu_src_vop3p(ctx, instr->src[!swap_srcs]);
if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
src1 = as_vgpr(ctx, src1);
- assert(instr->dest.dest.ssa.num_components == 2);
+ assert(instr->def.num_components == 2);
/* swizzle to opsel: all swizzles are either 0 (x) or 1 (y) */
unsigned opsel_lo =
aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op
: instr->src[0].src.ssa->bit_size == 32 ? v32_op
: v16_op;
- bool use_valu = s_op == aco_opcode::num_opcodes || instr->dest.dest.ssa.divergent ||
+ bool use_valu = s_op == aco_opcode::num_opcodes || instr->def.divergent ||
get_ssa_temp(ctx, instr->src[0].src.ssa).type() == RegType::vgpr ||
get_ssa_temp(ctx, instr->src[1].src.ssa).type() == RegType::vgpr;
aco_opcode op = use_valu ? v_op : s_op;
return;
}
- if (instr->dest.dest.ssa.bit_size == 1) {
+ if (instr->def.bit_size == 1) {
assert(dst.regClass() == bld.lm);
assert(then.regClass() == bld.lm);
assert(els.regClass() == bld.lm);
/* divergent boolean bcsel
* this implements bcsel on bools: dst = s0 ? s1 : s2
* are going to be: dst = (s0 & s1) | (~s0 & s2) */
- assert(instr->dest.dest.ssa.bit_size == 1);
+ assert(instr->def.bit_size == 1);
if (cond.id() != then.id())
then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
{
Builder bld(ctx->program, ctx->block);
bld.is_precise = instr->exact;
- Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
+ Temp dst = get_ssa_temp(ctx, &instr->def);
switch (instr->op) {
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec8:
case nir_op_vec16: {
std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
- unsigned num = instr->dest.dest.ssa.num_components;
+ unsigned num = instr->def.num_components;
for (unsigned i = 0; i < num; ++i)
elems[i] = get_alu_src(ctx, instr->src[i]);
- if (instr->dest.dest.ssa.bit_size >= 32 || dst.type() == RegType::vgpr) {
+ if (instr->def.bit_size >= 32 || dst.type() == RegType::vgpr) {
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
- aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
- RegClass elem_rc = RegClass::get(RegType::vgpr, instr->dest.dest.ssa.bit_size / 8u);
+ aco_opcode::p_create_vector, Format::PSEUDO, instr->def.num_components, 1)};
+ RegClass elem_rc = RegClass::get(RegType::vgpr, instr->def.bit_size / 8u);
for (unsigned i = 0; i < num; ++i) {
if (elems[i].type() == RegType::sgpr && elem_rc.is_subdword())
elems[i] = emit_extract_vector(ctx, elems[i], 0, elem_rc);
ctx->allocated_vec.emplace(dst.id(), elems);
} else {
bool use_s_pack = ctx->program->gfx_level >= GFX9;
- Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->dest.dest.ssa.bit_size) - 1));
+ Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->def.bit_size) - 1));
std::array<Temp, NIR_MAX_VEC_COMPONENTS> packed;
uint32_t const_vals[NIR_MAX_VEC_COMPONENTS] = {};
for (unsigned i = 0; i < num; i++) {
unsigned packed_size = use_s_pack ? 16 : 32;
- unsigned idx = i * instr->dest.dest.ssa.bit_size / packed_size;
- unsigned offset = i * instr->dest.dest.ssa.bit_size % packed_size;
+ unsigned idx = i * instr->def.bit_size / packed_size;
+ unsigned offset = i * instr->def.bit_size % packed_size;
if (nir_src_is_const(instr->src[i].src)) {
const_vals[idx] |= nir_src_as_uint(instr->src[i].src) << offset;
continue;
if (nir_src_is_undef(instr->src[i].src))
continue;
- if (offset != packed_size - instr->dest.dest.ssa.bit_size)
+ if (offset != packed_size - instr->def.bit_size)
elems[i] =
bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), elems[i], mask);
break;
}
case nir_op_iabs: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Temp src = get_alu_src_vop3p(ctx, instr->src[0]);
unsigned opsel_lo = (instr->src[0].swizzle[0] & 1) << 1;
emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_i16_e64, dst);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_i16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_u16_e64, dst);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_u16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_i16_e64, dst);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_i16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_u16_e64, dst);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_u16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
break;
}
case nir_op_ior: {
- if (instr->dest.dest.ssa.bit_size == 1) {
+ if (instr->def.bit_size == 1) {
emit_boolean_logic(ctx, instr, Builder::s_or, dst);
} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
break;
}
case nir_op_iand: {
- if (instr->dest.dest.ssa.bit_size == 1) {
+ if (instr->def.bit_size == 1) {
emit_boolean_logic(ctx, instr, Builder::s_and, dst);
} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
break;
}
case nir_op_ixor: {
- if (instr->dest.dest.ssa.bit_size == 1) {
+ if (instr->def.bit_size == 1) {
emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
} else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshrrev_b16_e64, dst, false, 2, true);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b16, dst, false, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_lshrrev_b16, dst, true);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshlrev_b16_e64, dst, false, 2, true);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b16, dst, false, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_lshlrev_b16, dst, true);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true, false,
emit_vop3a_instruction(ctx, instr, aco_opcode::v_ashrrev_i16_e64, dst, false, 2, true);
} else if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i16, dst, false, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_ashrrev_i16, dst, true);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
} else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true);
break;
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_u16, dst);
break;
}
break;
}
case nir_op_uadd_sat: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Instruction* add_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_u16, dst);
add_instr->valu().clamp = 1;
break;
break;
}
case nir_op_iadd_sat: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Instruction* add_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_i16, dst);
add_instr->valu().clamp = 1;
break;
if (dst.regClass() == s1) {
emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
break;
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst);
break;
}
break;
}
case nir_op_usub_sat: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst);
sub_instr->valu().clamp = 1;
break;
break;
}
case nir_op_isub_sat: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_i16, dst);
sub_instr->valu().clamp = 1;
break;
emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u16_e64, dst);
} else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_lo_u16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_mul_lo_u16, dst);
} else if (dst.type() == RegType::vgpr) {
uint32_t src0_ub = get_alu_src_ub(ctx, instr, 0);
case nir_op_fmul: {
if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_mul_f16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
case nir_op_fadd: {
if (dst.regClass() == v2b) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_f16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
break;
}
case nir_op_fsub: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Instruction* add = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_f16, dst);
VALU_instruction& sub = add->valu();
sub.neg_lo[1] = true;
case nir_op_ffma: {
if (dst.regClass() == v2b) {
emit_vop3a_instruction(ctx, instr, aco_opcode::v_fma_f16, dst, false, 3);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
- assert(instr->dest.dest.ssa.num_components == 2);
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
+ assert(instr->def.num_components == 2);
Temp src0 = as_vgpr(ctx, get_alu_src_vop3p(ctx, instr->src[0]));
Temp src1 = as_vgpr(ctx, get_alu_src_vop3p(ctx, instr->src[1]));
if (dst.regClass() == v2b) {
// TODO: check fp_mode.must_flush_denorms16_64
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_f16, dst);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false,
if (dst.regClass() == v2b) {
// TODO: check fp_mode.must_flush_denorms16_64
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f16, dst, true);
- } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == v1 && instr->def.bit_size == 16) {
emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_f16, dst, true);
} else if (dst.regClass() == v1) {
emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false,
break;
}
case nir_op_fneg: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Temp src = get_alu_src_vop3p(ctx, instr->src[0]);
Instruction* vop3p =
bld.vop3p(aco_opcode::v_pk_mul_f16, Definition(dst), src, Operand::c16(0x3C00),
break;
}
case nir_op_fabs: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Temp src = get_alu_src_vop3p(ctx, instr->src[0]);
Instruction* vop3p =
bld.vop3p(aco_opcode::v_pk_max_f16, Definition(dst), src, src,
break;
}
case nir_op_fsat: {
- if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+ if (dst.regClass() == v1 && instr->def.bit_size == 16) {
Temp src = get_alu_src_vop3p(ctx, instr->src[0]);
Instruction* vop3p =
bld.vop3p(aco_opcode::v_pk_mul_f16, Definition(dst), src, Operand::c16(0x3C00),
Temp tmp = bld.tmp(v1);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f16, tmp);
tmp = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), tmp);
- tmp = convert_int(ctx, bld, tmp, 32, instr->dest.dest.ssa.bit_size, false,
+ tmp = convert_int(ctx, bld, tmp, 32, instr->def.bit_size, false,
(dst.type() == RegType::sgpr) ? Temp() : dst);
if (dst.type() == RegType::sgpr) {
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
Temp tmp = bld.tmp(v1);
emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f16, tmp);
tmp = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), tmp);
- tmp = convert_int(ctx, bld, tmp, 32, instr->dest.dest.ssa.bit_size, false,
+ tmp = convert_int(ctx, bld, tmp, 32, instr->def.bit_size, false,
(dst.type() == RegType::sgpr) ? Temp() : dst);
if (dst.type() == RegType::sgpr) {
bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
case nir_op_i2i32: {
if (dst.type() == RegType::sgpr && instr->src[0].src.ssa->bit_size < 32) {
/* no need to do the extract in get_alu_src() */
- sgpr_extract_mode mode = instr->dest.dest.ssa.bit_size > instr->src[0].src.ssa->bit_size
+ sgpr_extract_mode mode = instr->def.bit_size > instr->src[0].src.ssa->bit_size
? sgpr_extract_sext
: sgpr_extract_undef;
extract_8_16_bit_sgpr_element(ctx, dst, &instr->src[0], mode);
} else {
const unsigned input_bitsize = instr->src[0].src.ssa->bit_size;
- const unsigned output_bitsize = instr->dest.dest.ssa.bit_size;
+ const unsigned output_bitsize = instr->def.bit_size;
convert_int(ctx, bld, get_alu_src(ctx, instr->src[0]), input_bitsize, output_bitsize,
output_bitsize > input_bitsize, dst);
}
case nir_op_u2u32: {
if (dst.type() == RegType::sgpr && instr->src[0].src.ssa->bit_size < 32) {
/* no need to do the extract in get_alu_src() */
- sgpr_extract_mode mode = instr->dest.dest.ssa.bit_size > instr->src[0].src.ssa->bit_size
+ sgpr_extract_mode mode = instr->def.bit_size > instr->src[0].src.ssa->bit_size
? sgpr_extract_zext
: sgpr_extract_undef;
extract_8_16_bit_sgpr_element(ctx, dst, &instr->src[0], mode);
} else {
convert_int(ctx, bld, get_alu_src(ctx, instr->src[0]), instr->src[0].src.ssa->bit_size,
- instr->dest.dest.ssa.bit_size, false, dst);
+ instr->def.bit_size, false, dst);
}
break;
}
unsigned comp = instr->op == nir_op_extract_u8 || instr->op == nir_op_extract_i8 ? 4 : 2;
uint32_t bits = comp == 4 ? 8 : 16;
unsigned index = nir_src_as_uint(instr->src[1].src);
- if (bits >= instr->dest.dest.ssa.bit_size || index * bits >= instr->dest.dest.ssa.bit_size) {
+ if (bits >= instr->def.bit_size || index * bits >= instr->def.bit_size) {
assert(index == 0);
bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0]));
- } else if (dst.regClass() == s1 && instr->dest.dest.ssa.bit_size == 16) {
+ } else if (dst.regClass() == s1 && instr->def.bit_size == 16) {
Temp vec = get_ssa_temp(ctx, instr->src[0].src.ssa);
unsigned swizzle = instr->src[0].swizzle[0];
if (vec.size() > 1) {
vec = emit_extract_vector(ctx, vec, swizzle / 2, s1);
swizzle = swizzle & 1;
}
- index += swizzle * instr->dest.dest.ssa.bit_size / bits;
+ index += swizzle * instr->def.bit_size / bits;
bld.pseudo(aco_opcode::p_extract, Definition(dst), bld.def(s1, scc), Operand(vec),
Operand::c32(index), Operand::c32(bits), Operand::c32(is_signed));
} else {
unsigned comp = instr->op == nir_op_insert_u8 ? 4 : 2;
uint32_t bits = comp == 4 ? 8 : 16;
unsigned index = nir_src_as_uint(instr->src[1].src);
- if (bits >= instr->dest.dest.ssa.bit_size || index * bits >= instr->dest.dest.ssa.bit_size) {
+ if (bits >= instr->def.bit_size || index * bits >= instr->def.bit_size) {
assert(index == 0);
bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0]));
} else {
nir_alu_instr* alu = nir_instr_as_alu(src->parent_instr);
if (alu->op != nir_op_unpack_64_2x32_split_x && alu->op != nir_op_unpack_64_2x32_split_y)
return false;
- if (!only_used_by_cross_lane_instrs(&alu->dest.dest.ssa, follow_phis))
+ if (!only_used_by_cross_lane_instrs(&alu->def, follow_phis))
return false;
continue;
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr* alu_instr = nir_instr_as_alu(instr);
- RegType type =
- alu_instr->dest.dest.ssa.divergent ? RegType::vgpr : RegType::sgpr;
+ RegType type = alu_instr->def.divergent ? RegType::vgpr : RegType::sgpr;
switch (alu_instr->op) {
case nir_op_fmul:
case nir_op_fmulz:
case nir_op_ishr:
case nir_op_ushr:
/* packed 16bit instructions have to be VGPR */
- type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type;
+ type = alu_instr->def.num_components == 2 ? RegType::vgpr : type;
FALLTHROUGH;
default:
for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) {
break;
}
- RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components,
- alu_instr->dest.dest.ssa.bit_size);
- regclasses[alu_instr->dest.dest.ssa.index] = rc;
+ RegClass rc =
+ get_reg_class(ctx, type, alu_instr->def.num_components, alu_instr->def.bit_size);
+ regclasses[alu_instr->def.index] = rc;
break;
}
case nir_instr_type_load_const: {
static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
{
LLVMValueRef src[16], result = NULL;
- unsigned num_components = instr->dest.dest.ssa.num_components;
+ unsigned num_components = instr->def.num_components;
unsigned src_components;
- LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
+ LLVMTypeRef def_type = get_def_type(ctx, &instr->def);
assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
switch (instr->op) {
/* fneg will be optimized by backend compiler with sign
* bit removed via XOR. This is probably a LLVM bug.
*/
- result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size);
+ result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size);
}
break;
case nir_op_inot:
/* fabs will be optimized by backend compiler with sign
* bit removed via AND.
*/
- result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size);
+ result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size);
}
break;
case nir_op_fsat:
break;
case nir_op_frexp_sig:
src[0] = ac_to_float(&ctx->ac, src[0]);
- result = ac_build_frexp_mant(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
+ result = ac_build_frexp_mant(&ctx->ac, src[0], instr->def.bit_size);
break;
case nir_op_fmax:
result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum", ac_to_float_type(&ctx->ac, def_type),
src[0], src[1]);
- if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) {
+ if (ctx->ac.gfx_level < GFX9 && instr->def.bit_size == 32) {
/* Only pre-GFX9 chips do not flush denorms. */
- result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size);
+ result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size);
}
break;
case nir_op_fmin:
result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum", ac_to_float_type(&ctx->ac, def_type),
src[0], src[1]);
- if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) {
+ if (ctx->ac.gfx_level < GFX9 && instr->def.bit_size == 32) {
/* Only pre-GFX9 chips do not flush denorms. */
- result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size);
+ result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size);
}
break;
case nir_op_ffma:
/* FMA is slow on gfx6-8, so it shouldn't be used. */
- assert(instr->dest.dest.ssa.bit_size != 32 || ctx->ac.gfx_level >= GFX9);
+ assert(instr->def.bit_size != 32 || ctx->ac.gfx_level >= GFX9);
result = emit_intrin_3f_param(&ctx->ac, "llvm.fma", ac_to_float_type(&ctx->ac, def_type),
src[0], src[1], src[2]);
break;
case nir_op_b2f16:
case nir_op_b2f32:
case nir_op_b2f64:
- result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
+ result = emit_b2f(&ctx->ac, src[0], instr->def.bit_size);
break;
case nir_op_b2i8:
case nir_op_b2i16:
case nir_op_b2i32:
case nir_op_b2i64:
- result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
+ result = emit_b2i(&ctx->ac, src[0], instr->def.bit_size);
break;
case nir_op_b2b1: /* after loads */
result = emit_i2b(&ctx->ac, src[0]);
if (result) {
result = ac_to_integer_or_pointer(&ctx->ac, result);
- ctx->ssa_defs[instr->dest.dest.ssa.index] = result;
+ ctx->ssa_defs[instr->def.index] = result;
}
return true;
}
return true;
} else if (use_src->parent_instr->type == nir_instr_type_alu) {
nir_alu_instr *instr = nir_instr_as_alu(use_src->parent_instr);
- if (instr->op == nir_op_vec4 && is_def_used_in_an_export(&instr->dest.dest.ssa)) {
+ if (instr->op == nir_op_vec4 && is_def_used_in_an_export(&instr->def)) {
return true;
}
}
/* If an instruction is not scalarized by this point,
* it can be emitted as packed instruction */
- if (alu->dest.dest.ssa.num_components > 1)
+ if (alu->def.num_components > 1)
return 0;
- if (alu->dest.dest.ssa.bit_size & (8 | 16)) {
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ if (alu->def.bit_size & (8 | 16)) {
+ unsigned bit_size = alu->def.bit_size;
switch (alu->op) {
case nir_op_bitfield_select:
case nir_op_imul_high:
case nir_op_isign:
case nir_op_uadd_sat:
case nir_op_usub_sat:
- return (bit_size == 8 || !(chip >= GFX8 && alu->dest.dest.ssa.divergent)) ? 32 : 0;
+ return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
case nir_op_iadd_sat:
case nir_op_isub_sat:
- return bit_size == 8 || !alu->dest.dest.ssa.divergent ? 32 : 0;
+ return bit_size == 8 || !alu->def.divergent ? 32 : 0;
default:
return 0;
case nir_op_uge:
case nir_op_bitz:
case nir_op_bitnz:
- return (bit_size == 8 || !(chip >= GFX8 && alu->dest.dest.ssa.divergent)) ? 32 : 0;
+ return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0;
default:
return 0;
}
return 1;
const nir_alu_instr *alu = nir_instr_as_alu(instr);
- const unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ const unsigned bit_size = alu->def.bit_size;
if (bit_size != 16)
return 1;
return 0;
const nir_alu_instr *alu = nir_instr_as_alu(instr);
- const unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ const unsigned bit_size = alu->def.bit_size;
if (bit_size == 16)
return 2;
else
agx_emit_alu(agx_builder *b, nir_alu_instr *instr)
{
unsigned srcs = nir_op_infos[instr->op].num_inputs;
- unsigned sz = instr->dest.dest.ssa.bit_size;
+ unsigned sz = instr->def.bit_size;
unsigned src_sz = srcs ? nir_src_bit_size(instr->src[0].src) : 0;
- ASSERTED unsigned comps = instr->dest.dest.ssa.num_components;
+ ASSERTED unsigned comps = instr->def.num_components;
assert(comps == 1 || nir_op_is_vec(instr->op));
assert(sz == 1 ||
sz == 8) ||
sz == 16 || sz == 32 || sz == 64);
- agx_index dst = agx_def_index(&instr->dest.dest.ssa);
+ agx_index dst = agx_def_index(&instr->def);
agx_index s0 = srcs > 0 ? agx_alu_src_index(b, instr->src[0]) : agx_null();
agx_index s1 = srcs > 1 ? agx_alu_src_index(b, instr->src[1]) : agx_null();
agx_index s2 = srcs > 2 ? agx_alu_src_index(b, instr->src[2]) : agx_null();
* implemented natively.
*/
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.bit_size == 8 && !is_conversion_to_8bit(alu->op))
+ if (alu->def.bit_size == 8 && !is_conversion_to_8bit(alu->op))
return 16;
else
return 0;
srcs[i] = ntq_get_src(c, instr->src[i].src,
instr->src[i].swizzle[0]);
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
- ntq_store_def(c, &instr->dest.dest.ssa, i,
+ ntq_store_def(c, &instr->def, i,
vir_MOV(c, srcs[i]));
return;
}
abort();
}
- ntq_store_def(c, &instr->dest.dest.ssa, 0, result);
+ ntq_store_def(c, &instr->def, 0, result);
}
/* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit
switch (instr->type) {
case nir_instr_type_alu:
alu_instr = nir_instr_as_alu(instr);
- return &alu_instr->dest.dest.ssa;
+ return &alu_instr->def;
case nir_instr_type_intrinsic:
intrinsic_instr = nir_instr_as_intrinsic(instr);
{
nir_alu_instr *alu = find_op(op);
EXPECT_TRUE(alu != NULL);
- return alu->dest.dest.ssa.bit_size;
+ return alu->def.bit_size;
}
char *get_fs_ir(void) {
{
switch (instr->type) {
case nir_instr_type_alu:
- return &nir_instr_as_alu(instr)->dest.dest.ssa;
+ return &nir_instr_as_alu(instr)->def;
case nir_instr_type_deref:
return &nir_instr_as_deref(instr)->dest.ssa;
if (nir_op_infos[instr->op].input_sizes[src] > 0)
return channel < nir_op_infos[instr->op].input_sizes[src];
- return channel < instr->dest.dest.ssa.num_components;
+ return channel < instr->def.num_components;
}
nir_component_mask_t
if (nir_op_infos[instr->op].input_sizes[src] > 0)
return nir_op_infos[instr->op].input_sizes[src];
- return instr->dest.dest.ssa.num_components;
+ return instr->def.num_components;
}
#define CASE_ALL_SIZES(op) \
uint8_t swizzle[NIR_MAX_VEC_COMPONENTS];
} nir_alu_src;
-typedef struct {
- /** Base destination */
- nir_dest dest;
-} nir_alu_dest;
-
/** NIR sized and unsized types
*
* The values in this enum are carefully chosen so that the sized type is
bool no_unsigned_wrap : 1;
/** Destination */
- nir_alu_dest dest;
+ nir_def def;
/** Sources
*
}
}
- nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components,
+ nir_def_init(&instr->instr, &instr->def, num_components,
bit_size);
nir_builder_instr_insert(build, &instr->instr);
- return &instr->dest.dest.ssa;
+ return &instr->def;
}
nir_def *
/* Note: not reusing nir_builder_alu_instr_finish_and_insert() because it
* can't re-guess the num_components when num_components == 1 (nir_op_mov).
*/
- nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components,
+ nir_def_init(&instr->instr, &instr->def, num_components,
comp[0].def->bit_size);
nir_builder_instr_insert(build, &instr->instr);
- return &instr->dest.dest.ssa;
+ return &instr->def;
}
/**
}
nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
- nir_def_init(&mov->instr, &mov->dest.dest.ssa, num_components,
+ nir_def_init(&mov->instr, &mov->def, num_components,
nir_src_bit_size(src.src));
mov->exact = build->exact;
mov->src[0] = src;
nir_builder_instr_insert(build, &mov->instr);
- return &mov->dest.dest.ssa;
+ return &mov->def;
}
/**
nalu->no_signed_wrap = alu->no_signed_wrap;
nalu->no_unsigned_wrap = alu->no_unsigned_wrap;
- __clone_def(state, &nalu->instr, &nalu->dest.dest.ssa, &alu->dest.dest.ssa);
+ __clone_def(state, &nalu->instr, &nalu->def, &alu->def);
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
__clone_src(state, &nalu->instr, &nalu->src[i].src, &alu->src[i].src);
static bool
visit_alu(nir_alu_instr *instr)
{
- if (instr->dest.dest.ssa.divergent)
+ if (instr->def.divergent)
return false;
unsigned num_src = nir_op_infos[instr->op].num_inputs;
for (unsigned i = 0; i < num_src; i++) {
if (instr->src[i].src.ssa->divergent) {
- instr->dest.dest.ssa.divergent = true;
+ instr->def.divergent = true;
return true;
}
}
shader->info.bit_sizes_int |= nir_src_bit_size(instr->src[i].src);
}
if (nir_alu_type_get_base_type(info->output_type) == nir_type_float)
- shader->info.bit_sizes_float |= instr->dest.dest.ssa.bit_size;
+ shader->info.bit_sizes_float |= instr->def.bit_size;
else
- shader->info.bit_sizes_int |= instr->dest.dest.ssa.bit_size;
+ shader->info.bit_sizes_int |= instr->def.bit_size;
}
static void
case nir_op_vec8:
case nir_op_vec16:
for (unsigned i = 0; i < info->num_inputs; i++) {
- copy_types(alu->src[i].src, &alu->dest.dest.ssa,
+ copy_types(alu->src[i].src, &alu->def,
float_types, int_types, &progress);
}
break;
case nir_op_b32csel:
set_type(alu->src[0].src.ssa->index, nir_type_bool,
float_types, int_types, &progress);
- copy_types(alu->src[1].src, &alu->dest.dest.ssa,
+ copy_types(alu->src[1].src, &alu->def,
float_types, int_types, &progress);
- copy_types(alu->src[2].src, &alu->dest.dest.ssa,
+ copy_types(alu->src[2].src, &alu->def,
float_types, int_types, &progress);
break;
info->input_types[i],
float_types, int_types, &progress);
}
- set_type(alu->dest.dest.ssa.index, info->output_type,
+ set_type(alu->def.index, info->output_type,
float_types, int_types, &progress);
}
break;
{
switch (instr->type) {
case nir_instr_type_alu:
- return cb(&nir_instr_as_alu(instr)->dest.dest.ssa, state);
+ return cb(&nir_instr_as_alu(instr)->def, state);
case nir_instr_type_deref:
return cb(&nir_instr_as_deref(instr)->dest.ssa, state);
case nir_instr_type_intrinsic: {
instr->no_unsigned_wrap << 1;
hash = HASH(hash, flags);
- hash = HASH(hash, instr->dest.dest.ssa.num_components);
- hash = HASH(hash, instr->dest.dest.ssa.bit_size);
+ hash = HASH(hash, instr->def.num_components);
+ hash = HASH(hash, instr->def.bit_size);
if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
assert(nir_op_infos[instr->op].num_inputs >= 2);
/* TODO: We can probably acutally do something more inteligent such
* as allowing different numbers and taking a maximum or something
* here */
- if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components)
+ if (alu1->def.num_components != alu2->def.num_components)
return false;
- if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size)
+ if (alu1->def.bit_size != alu2->def.bit_size)
return false;
if (nir_op_infos[alu1->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) {
{
switch (instr->type) {
case nir_instr_type_alu:
- return &nir_instr_as_alu(instr)->dest.dest.ssa;
+ return &nir_instr_as_alu(instr)->def;
case nir_instr_type_deref:
return &nir_instr_as_deref(instr)->dest.ssa;
case nir_instr_type_load_const:
assert(mod->op == nir_op_fabs || mod->op == nir_op_fneg);
/* No legacy user supports fp64 modifiers */
- if (mod->dest.dest.ssa.bit_size == 64)
+ if (mod->def.bit_size == 64)
return false;
- nir_foreach_use_including_if(src, &mod->dest.dest.ssa) {
+ nir_foreach_use_including_if(src, &mod->def) {
if (src->is_if)
return false;
return false;
/* We can't do expansions without a move in the middle */
- unsigned nr_components = generate_alu->dest.dest.ssa.num_components;
- if (fsat->dest.dest.ssa.num_components != nr_components)
+ unsigned nr_components = generate_alu->def.num_components;
+ if (fsat->def.num_components != nr_components)
return false;
/* We don't handle swizzles here, so check for the identity */
/* Otherwise, we're good */
nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr);
- *def = &alu->dest.dest.ssa;
+ *def = &alu->def;
return true;
}
* already know that they're all float ALU instructions because
* nir_legacy_float_mod_folds() returned true.
*/
- nir_foreach_use_including_if_safe(use, &alu->dest.dest.ssa) {
+ nir_foreach_use_including_if_safe(use, &alu->def) {
assert(!use->is_if);
assert(use->parent_instr->type == nir_instr_type_alu);
nir_alu_src *alu_use = list_entry(use, nir_alu_src, src);
}
}
- nir_legacy_alu_dest dest = nir_legacy_chase_alu_dest(&alu->dest.dest.ssa);
+ nir_legacy_alu_dest dest = nir_legacy_chase_alu_dest(&alu->def);
if (dest.fsat) {
nir_intrinsic_instr *store = nir_store_reg_for_def(dest.dest.ssa);
if (store) {
nir_intrinsic_set_legacy_fsat(store, true);
- nir_src_rewrite(&store->src[0], &alu->dest.dest.ssa);
+ nir_src_rewrite(&store->src[0], &alu->def);
return true;
}
}
/* Also if the selects condition is only used by the select then
* remove that alu instructons cost from the cost total also.
*/
- if (!list_is_singular(&sel_alu->dest.dest.ssa.uses) ||
- nir_def_used_by_if(&sel_alu->dest.dest.ssa))
+ if (!list_is_singular(&sel_alu->def.uses) ||
+ nir_def_used_by_if(&sel_alu->def))
return 0;
else
return -1;
}
if (alu->op == nir_op_flrp) {
- if ((options->lower_flrp16 && alu->dest.dest.ssa.bit_size == 16) ||
- (options->lower_flrp32 && alu->dest.dest.ssa.bit_size == 32) ||
- (options->lower_flrp64 && alu->dest.dest.ssa.bit_size == 64))
+ if ((options->lower_flrp16 && alu->def.bit_size == 16) ||
+ (options->lower_flrp32 && alu->def.bit_size == 32) ||
+ (options->lower_flrp64 && alu->def.bit_size == 64))
cost *= 3;
}
* There are no 64-bit ops that don't have a 64-bit thing as their
* destination or first source.
*/
- if (alu->dest.dest.ssa.bit_size < 64 &&
+ if (alu->def.bit_size < 64 &&
nir_src_bit_size(alu->src[0].src) < 64)
return cost;
- bool is_fp64 = alu->dest.dest.ssa.bit_size == 64 &&
+ bool is_fp64 = alu->def.bit_size == 64 &&
nir_alu_type_get_base_type(info->output_type) == nir_type_float;
for (unsigned i = 0; i < info->num_inputs; i++) {
if (nir_src_bit_size(alu->src[i].src) == 64 &&
alu_src_has_identity_swizzle(nir_alu_instr *alu, unsigned src_idx)
{
assert(nir_op_infos[alu->op].input_sizes[src_idx] == 0);
- for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) {
+ for (unsigned i = 0; i < alu->def.num_components; i++) {
if (alu->src[src_idx].swizzle[i] != i)
return false;
}
nir_instr_as_phi(src_var->def->parent_instr);
nir_alu_instr *src_phi_alu = phi_instr_as_alu(src_phi);
if (src_phi_alu) {
- src_var = get_loop_var(&src_phi_alu->dest.dest.ssa, state);
+ src_var = get_loop_var(&src_phi_alu->def, state);
if (!src_var->in_if_branch)
break;
}
*/
unsigned bit_size = 0;
if (!nir_alu_type_get_type_size(nir_op_infos[alu->op].output_type))
- bit_size = alu->dest.dest.ssa.bit_size;
+ bit_size = alu->def.bit_size;
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
if (bit_size == 0 &&
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; ++i)
srcs[i] = src[i];
- nir_eval_const_opcode(alu->op, dest, alu->dest.dest.ssa.num_components,
+ nir_eval_const_opcode(alu->op, dest, alu->def.num_components,
bit_size, srcs, execution_mode);
return true;
*/
unsigned trip_offset = 0;
nir_alu_instr *cond_alu = nir_instr_as_alu(cond.def->parent_instr);
- if (cond_alu->src[0].src.ssa == &alu->dest.dest.ssa ||
- cond_alu->src[1].src.ssa == &alu->dest.dest.ssa) {
+ if (cond_alu->src[0].src.ssa == &alu->def ||
+ cond_alu->src[1].src.ssa == &alu->def) {
trip_offset = 1;
}
}
if (lowered) {
- nir_def_rewrite_uses(&instr->dest.dest.ssa, lowered);
+ nir_def_rewrite_uses(&instr->def, lowered);
nir_instr_remove(&instr->instr);
return true;
} else {
/* There is no ALU instruction which has a scalar destination, scalar
* src[0], and some other vector source.
*/
- return alu->dest.dest.ssa.num_components > 1 ||
+ return alu->def.num_components > 1 ||
nir_op_infos[alu->op].input_sizes[0] > 1;
}
continue;
unsigned mask = ~(width - 1);
- for (unsigned j = 1; j < alu->dest.dest.ssa.num_components; j++) {
+ for (unsigned j = 1; j < alu->def.num_components; j++) {
if ((alu->src[i].swizzle[0] & mask) != (alu->src[i].swizzle[j] & mask))
return false;
}
nir_alu_ssa_dest_init(nir_alu_instr *alu, unsigned num_components,
unsigned bit_size)
{
- nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components, bit_size);
+ nir_def_init(&alu->instr, &alu->def, num_components, bit_size);
}
static nir_def *
for (int i = 0; i < num_components; i++) {
int channel = reverse_order ? num_components - 1 - i : i;
nir_alu_instr *chan = nir_alu_instr_create(builder->shader, chan_op);
- nir_alu_ssa_dest_init(chan, 1, alu->dest.dest.ssa.bit_size);
+ nir_alu_ssa_dest_init(chan, 1, alu->def.bit_size);
nir_alu_src_copy(&chan->src[0], &alu->src[0], chan);
chan->src[0].swizzle[0] = chan->src[0].swizzle[channel];
if (nir_op_infos[chan_op].num_inputs > 1) {
nir_builder_instr_insert(builder, &chan->instr);
if (i == 0) {
- last = &chan->dest.dest.ssa;
+ last = &chan->def;
} else {
last = nir_build_alu(builder, merge_op,
- last, &chan->dest.dest.ssa, NULL, NULL);
+ last, &chan->def, NULL, NULL);
}
}
/* If we don't want to lower ffma, create several ffma instead of fmul+fadd
* and fusing later because fusing is not possible for exact fdot instructions.
*/
- if (will_lower_ffma(builder->shader, alu->dest.dest.ssa.bit_size))
+ if (will_lower_ffma(builder->shader, alu->def.bit_size))
return lower_reduction(alu, nir_op_fmul, nir_op_fadd, builder, reverse_order);
unsigned num_components = nir_op_infos[alu->op].input_sizes[0];
int channel = reverse_order ? num_components - 1 - i : i;
nir_alu_instr *instr = nir_alu_instr_create(
builder->shader, prev ? nir_op_ffma : nir_op_fmul);
- nir_alu_ssa_dest_init(instr, 1, alu->dest.dest.ssa.bit_size);
+ nir_alu_ssa_dest_init(instr, 1, alu->def.bit_size);
for (unsigned j = 0; j < 2; j++) {
nir_alu_src_copy(&instr->src[j], &alu->src[j], instr);
instr->src[j].swizzle[0] = alu->src[j].swizzle[channel];
nir_builder_instr_insert(builder, &instr->instr);
- prev = &instr->dest.dest.ssa;
+ prev = &instr->def;
}
return prev;
b->exact = alu->exact;
- unsigned num_components = alu->dest.dest.ssa.num_components;
+ unsigned num_components = alu->def.num_components;
unsigned target_width = 1;
if (data->cb) {
/* Only use reverse order for imprecise fdph, see explanation in lower_fdot. */
bool reverse_order = !b->exact;
- if (will_lower_ffma(b->shader, alu->dest.dest.ssa.bit_size)) {
+ if (will_lower_ffma(b->shader, alu->def.bit_size)) {
nir_def *sum[4];
for (unsigned i = 0; i < 3; i++) {
int dest = reverse_order ? 3 - i : i;
}
}
- nir_alu_ssa_dest_init(lower, components, alu->dest.dest.ssa.bit_size);
+ nir_alu_ssa_dest_init(lower, components, alu->def.bit_size);
lower->exact = alu->exact;
for (i = 0; i < components; i++) {
- vec->src[chan + i].src = nir_src_for_ssa(&lower->dest.dest.ssa);
+ vec->src[chan + i].src = nir_src_for_ssa(&lower->def);
vec->src[chan + i].swizzle[0] = i;
}
if (alu->op != nir_op_amul)
continue;
- if (alu->dest.dest.ssa.bit_size <= 32)
+ if (alu->def.bit_size <= 32)
alu->op = nir_op_imul24;
else
alu->op = nir_op_imul;
lower_alu_instr(nir_builder *bld, nir_alu_instr *alu, unsigned bit_size)
{
const nir_op op = alu->op;
- unsigned dst_bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bit_size = alu->def.bit_size;
bld->cursor = nir_before_instr(&alu->instr);
dst_bit_size != bit_size) {
nir_alu_type type = nir_op_infos[op].output_type;
nir_def *dst = nir_convert_to_bit_size(bld, lowered_dst, type, dst_bit_size);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, dst);
+ nir_def_rewrite_uses(&alu->def, dst);
} else {
- nir_def_rewrite_uses(&alu->dest.dest.ssa, lowered_dst);
+ nir_def_rewrite_uses(&alu->def, lowered_dst);
}
}
*/
nir_alu_instr *conv_instr =
nir_instr_as_alu(nir_builder_last_instr(b));
- conv_instr->dest.dest.ssa.num_components =
- alu->dest.dest.ssa.num_components;
+ conv_instr->def.num_components =
+ alu->def.num_components;
memcpy(conv_instr->src[0].swizzle,
alu->src[i].swizzle,
sizeof(conv_instr->src[0].swizzle));
case nir_op_iand:
case nir_op_ior:
case nir_op_ixor:
- if (alu->dest.dest.ssa.bit_size > 1)
+ if (alu->def.bit_size > 1)
return false; /* Not a boolean instruction */
FALLTHROUGH;
case nir_op_bcsel:
/* bcsel may be choosing between boolean sources too */
- if (alu->dest.dest.ssa.bit_size == 1)
+ if (alu->def.bit_size == 1)
make_sources_canonical(b, alu, 1);
break;
break;
default:
- assert(alu->dest.dest.ssa.bit_size > 1);
+ assert(alu->def.bit_size > 1);
for (unsigned i = 0; i < op_info->num_inputs; i++)
assert(alu->src[i].src.ssa->bit_size > 1);
return false;
alu->op = opcode;
- if (alu->dest.dest.ssa.bit_size == 1)
- alu->dest.dest.ssa.bit_size = bit_size;
+ if (alu->def.bit_size == 1)
+ alu->def.bit_size = bit_size;
return true;
}
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
- if (alu->dest.dest.ssa.bit_size != 1)
+ if (alu->def.bit_size != 1)
return false;
/* These we expect to have booleans but the opcode doesn't change */
break;
break;
default:
- assert(alu->dest.dest.ssa.bit_size > 1);
+ assert(alu->def.bit_size > 1);
for (unsigned i = 0; i < op_info->num_inputs; i++)
assert(alu->src[i].src.ssa->bit_size > 1);
return false;
if (rep) {
/* We've emitted a replacement instruction */
- nir_def_rewrite_uses(&alu->dest.dest.ssa, rep);
+ nir_def_rewrite_uses(&alu->def, rep);
nir_instr_remove(&alu->instr);
} else {
- if (alu->dest.dest.ssa.bit_size == 1)
- alu->dest.dest.ssa.bit_size = 32;
+ if (alu->def.bit_size == 1)
+ alu->def.bit_size = 32;
}
return true;
case nir_op_iand:
case nir_op_ior:
case nir_op_ixor:
- if (alu->dest.dest.ssa.bit_size != 1)
+ if (alu->def.bit_size != 1)
return false;
/* These we expect to have booleans but the opcode doesn't change */
break;
break;
default:
- assert(alu->dest.dest.ssa.bit_size > 1);
+ assert(alu->def.bit_size > 1);
for (unsigned i = 0; i < op_info->num_inputs; i++)
assert(alu->src[i].src.ssa->bit_size > 1);
return false;
}
- if (alu->dest.dest.ssa.bit_size == 1)
- alu->dest.dest.ssa.bit_size = 32;
+ if (alu->def.bit_size == 1)
+ alu->def.bit_size = 32;
return true;
}
nir_def *src = nir_ssa_for_alu_src(b, alu, 0);
nir_alu_type src_type = nir_op_infos[alu->op].input_types[0] | src->bit_size;
nir_alu_type dst_type = nir_op_infos[alu->op].output_type;
- return nir_convert_alu_types(b, alu->dest.dest.ssa.bit_size, src,
+ return nir_convert_alu_types(b, alu->def.bit_size, src,
.src_type = src_type, .dest_type = dst_type,
.rounding_mode = nir_rounding_mode_undef,
.saturate = false);
const nir_alu_instr *alu = nir_instr_as_alu(instr);
- bool is_64 = alu->dest.dest.ssa.bit_size == 64;
+ bool is_64 = alu->def.bit_size == 64;
unsigned num_srcs = nir_op_infos[alu->op].num_inputs;
for (unsigned i = 0; i < num_srcs; i++) {
return NULL;
nir_def *src = nir_mov_alu(b, alu->src[0],
- alu->dest.dest.ssa.num_components);
+ alu->def.num_components);
switch (alu->op) {
case nir_op_frcp:
case nir_op_fsub:
case nir_op_fmod: {
nir_def *src1 = nir_mov_alu(b, alu->src[1],
- alu->dest.dest.ssa.num_components);
+ alu->def.num_components);
switch (alu->op) {
case nir_op_fdiv:
return nir_fmul(b, src, nir_frcp(b, src1));
nir_def *const outer_ffma = nir_ffma(bld, b, c, inner_ffma);
nir_instr_as_alu(outer_ffma->parent_instr)->exact = alu->exact;
- nir_def_rewrite_uses(&alu->dest.dest.ssa, outer_ffma);
+ nir_def_rewrite_uses(&alu->def, outer_ffma);
/* DO NOT REMOVE the original flrp yet. Many of the lowering choices are
* based on other uses of the sources. Removing the flrp may cause the
nir_def *const final_ffma = nir_ffma(bld, a, one_minus_c, b_times_c);
nir_instr_as_alu(final_ffma->parent_instr)->exact = alu->exact;
- nir_def_rewrite_uses(&alu->dest.dest.ssa, final_ffma);
+ nir_def_rewrite_uses(&alu->def, final_ffma);
/* DO NOT REMOVE the original flrp yet. Many of the lowering choices are
* based on other uses of the sources. Removing the flrp may cause the
nir_def *const sum = nir_fadd(bld, first_product, second_product);
nir_instr_as_alu(sum->parent_instr)->exact = alu->exact;
- nir_def_rewrite_uses(&alu->dest.dest.ssa, sum);
+ nir_def_rewrite_uses(&alu->def, sum);
/* DO NOT REMOVE the original flrp yet. Many of the lowering choices are
* based on other uses of the sources. Removing the flrp may cause the
nir_def *const sum = nir_fadd(bld, a, product);
nir_instr_as_alu(sum->parent_instr)->exact = alu->exact;
- nir_def_rewrite_uses(&alu->dest.dest.ssa, sum);
+ nir_def_rewrite_uses(&alu->def, sum);
/* DO NOT REMOVE the original flrp yet. Many of the lowering choices are
* based on other uses of the sources. Removing the flrp may cause the
nir_def *const outer_sum = nir_fadd(bld, inner_sum, b_times_c);
nir_instr_as_alu(outer_sum->parent_instr)->exact = alu->exact;
- nir_def_rewrite_uses(&alu->dest.dest.ssa, outer_sum);
+ nir_def_rewrite_uses(&alu->def, outer_sum);
/* DO NOT REMOVE the original flrp yet. Many of the lowering choices are
* based on other uses of the sources. Removing the flrp may cause the
return false;
const uint8_t *const swizzle = instr->src[src].swizzle;
- const unsigned num_components = instr->dest.dest.ssa.num_components;
+ const unsigned num_components = instr->def.num_components;
- if (instr->dest.dest.ssa.bit_size == 32) {
+ if (instr->def.bit_size == 32) {
const float first = val[swizzle[0]].f32;
for (unsigned i = 1; i < num_components; i++) {
const uint8_t *const swizzle0 = instr->src[0].swizzle;
const uint8_t *const swizzle1 = instr->src[1].swizzle;
- const unsigned num_components = instr->dest.dest.ssa.num_components;
+ const unsigned num_components = instr->def.num_components;
- if (instr->dest.dest.ssa.bit_size == 32) {
+ if (instr->def.bit_size == 32) {
for (unsigned i = 0; i < num_components; i++) {
int exp0;
int exp1;
bool always_precise)
{
bool have_ffma = false;
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned bit_size = alu->def.bit_size;
if (bit_size == 16)
have_ffma = !bld->shader->options->lower_ffma16;
nir_alu_instr *const alu = nir_instr_as_alu(instr);
if (alu->op == nir_op_flrp &&
- (alu->dest.dest.ssa.bit_size & lowering_mask)) {
+ (alu->def.bit_size & lowering_mask)) {
convert_flrp_instruction(&b, dead_flrp, alu, always_precise);
}
}
nir_alu_instr *alu = nir_instr_as_alu(instr);
src = alu->src[0].src.ssa;
swizzle = alu->src[0].swizzle;
- dst = &alu->dest.dest.ssa;
+ dst = &alu->def;
switch (alu->op) {
case nir_op_f2f16:
if (b->shader->info.float_controls_execution_mode & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16)
return false;
}
- nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, lower);
+ nir_def_rewrite_uses(&alu_instr->def, lower);
nir_instr_remove(instr);
return true;
}
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.bit_size > 32)
+ if (alu->def.bit_size > 32)
return false;
switch (alu->op) {
case nir_op_i2f64:
case nir_op_i2f32:
case nir_op_i2f16:
- return lower_2f(b, src[0], alu->dest.dest.ssa.bit_size, true);
+ return lower_2f(b, src[0], alu->def.bit_size, true);
case nir_op_u2f64:
case nir_op_u2f32:
case nir_op_u2f16:
- return lower_2f(b, src[0], alu->dest.dest.ssa.bit_size, false);
+ return lower_2f(b, src[0], alu->def.bit_size, false);
case nir_op_f2i64:
case nir_op_f2u64:
return lower_f2(b, src[0], alu->op == nir_op_f2i64);
case nir_op_amul:
if (options->has_imul24)
return false;
- if (alu->dest.dest.ssa.bit_size != 64)
+ if (alu->def.bit_size != 64)
return false;
break;
case nir_op_i2f64:
case nir_op_f2i64:
FALLTHROUGH;
default:
- if (alu->dest.dest.ssa.bit_size != 64)
+ if (alu->def.bit_size != 64)
return false;
break;
}
const nir_op_info *info = &nir_op_infos[alu->op];
for (unsigned i = 0; i < info->num_inputs; i++) {
- for (unsigned chan = 0; chan < alu->dest.dest.ssa.num_components; chan++) {
+ for (unsigned chan = 0; chan < alu->def.num_components; chan++) {
if (alu->src[i].swizzle[chan] != chan)
return false;
}
{
const nir_op_info *info = &nir_op_infos[alu->op];
- bool is_bool_only = alu->dest.dest.ssa.bit_size == 1;
+ bool is_bool_only = alu->def.bit_size == 1;
for (unsigned i = 0; i < info->num_inputs; i++) {
if (alu->src[i].src.ssa->bit_size != 1)
is_bool_only = false;
if (rep) {
/* We've emitted a replacement instruction */
- nir_def_rewrite_uses(&alu->dest.dest.ssa, rep);
+ nir_def_rewrite_uses(&alu->def, rep);
nir_instr_remove(&alu->instr);
}
default:
unreachable("Impossible opcode");
}
- nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, dest);
+ nir_def_rewrite_uses(&alu_instr->def, dest);
nir_instr_remove(&alu_instr->instr);
return true;
nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components);
nir_alu_instr *vec = nir_alu_instr_create(state->shader, vec_op);
- nir_def_init(&vec->instr, &vec->dest.dest.ssa,
+ nir_def_init(&vec->instr, &vec->def,
phi->dest.ssa.num_components, bit_size);
for (unsigned i = 0; i < phi->dest.ssa.num_components; i++) {
/* We need to insert a mov to grab the i'th component of src */
nir_alu_instr *mov = nir_alu_instr_create(state->shader,
nir_op_mov);
- nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, bit_size);
+ nir_def_init(&mov->instr, &mov->def, 1, bit_size);
nir_src_copy(&mov->src[0].src, &src->src, &mov->instr);
mov->src[0].swizzle[0] = i;
else
nir_instr_insert_after_block(src->pred, &mov->instr);
- nir_phi_instr_add_src(new_phi, src->pred, nir_src_for_ssa(&mov->dest.dest.ssa));
+ nir_phi_instr_add_src(new_phi, src->pred, nir_src_for_ssa(&mov->def));
}
nir_instr_insert_before(&phi->instr, &new_phi->instr);
nir_instr_insert_after(&last_phi->instr, &vec->instr);
nir_def_rewrite_uses(&phi->dest.ssa,
- &vec->dest.dest.ssa);
+ &vec->def);
nir_instr_remove(&phi->instr);
exec_list_push_tail(&state->dead_instrs, &phi->instr.node);
nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr);
nir_alu_src *alu_src = exec_node_data(nir_alu_src, use_src, src);
- unsigned count = alu->dest.dest.ssa.num_components;
+ unsigned count = alu->def.num_components;
for (unsigned idx = 0; idx < count; ++idx)
alu_src->swizzle[idx] = swiz_map[alu_src->swizzle[idx]];
} else if (use_src->parent_instr->type == nir_instr_type_intrinsic) {
for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++)
mov->src[0].swizzle[i] = 0;
- nir_def_init(&mov->instr, &mov->dest.dest.ssa,
+ nir_def_init(&mov->instr, &mov->def,
intrin->num_components, intrin->dest.ssa.bit_size);
nir_instr_insert_before(&intrin->instr, &mov->instr);
nir_instr_remove(&intrin->instr);
nir_def_rewrite_uses(&intrin->dest.ssa,
- &mov->dest.dest.ssa);
+ &mov->def);
break;
}
assert(start_idx < nir_op_infos[vec->op].num_inputs);
nir_def *src = vec->src[start_idx].src.ssa;
- unsigned num_components = vec->dest.dest.ssa.num_components;
+ unsigned num_components = vec->def.num_components;
assert(num_components == nir_op_infos[vec->op].num_inputs);
unsigned write_mask = 0;
unsigned swiz[NIR_MAX_VEC_COMPONENTS] = { 0 };
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
swizzles[j][i] = src_alu->src[j].swizzle[i];
- unsigned dest_components = vec->dest.dest.ssa.num_components;
+ unsigned dest_components = vec->def.num_components;
assert(dest_components == nir_op_infos[vec->op].num_inputs);
/* Generate the final write mask */
nir_component_mask_t write_mask = 0;
for (unsigned i = start_idx; i < dest_components; i++) {
- if (vec->src[i].src.ssa != &src_alu->dest.dest.ssa)
+ if (vec->src[i].src.ssa != &src_alu->def)
continue;
write_mask |= BITFIELD_BIT(i);
}
/* We've cleared the only use of the destination */
- assert(list_is_empty(&src_alu->dest.dest.ssa.uses));
+ assert(list_is_empty(&src_alu->def.uses));
/* ... so we can replace it with the bigger destination accommodating the
* whole vector that will be masked for the store.
*/
- unsigned bit_size = vec->dest.dest.ssa.bit_size;
- assert(bit_size == src_alu->dest.dest.ssa.bit_size);
- nir_def_init(&src_alu->instr, &src_alu->dest.dest.ssa, dest_components,
+ unsigned bit_size = vec->def.bit_size;
+ assert(bit_size == src_alu->def.bit_size);
+ nir_def_init(&src_alu->instr, &src_alu->def, dest_components,
bit_size);
/* Then we can store that ALU result directly into the register */
b->cursor = nir_after_instr(&src_alu->instr);
- nir_build_store_reg(b, &src_alu->dest.dest.ssa,
+ nir_build_store_reg(b, &src_alu->def,
reg, .write_mask = write_mask);
return write_mask;
if (vec->op == nir_op_mov || !nir_op_is_vec(vec->op))
return false;
- unsigned num_components = vec->dest.dest.ssa.num_components;
+ unsigned num_components = vec->def.num_components;
/* Special case: if all sources are the same, just swizzle instead to avoid
* the extra copies from a register.
if (need_reg) {
/* We'll replace with a register. Declare one for the purpose. */
nir_def *reg = nir_decl_reg(b, num_components,
- vec->dest.dest.ssa.bit_size, 0);
+ vec->def.bit_size, 0);
unsigned finished_write_mask = 0;
for (unsigned i = 0; i < num_components; i++) {
finished_write_mask |= insert_store(b, reg, vec, i);
}
- nir_rewrite_uses_to_load_reg(b, &vec->dest.dest.ssa, reg);
+ nir_rewrite_uses_to_load_reg(b, &vec->def, reg);
} else {
/* Otherwise, we replace with a swizzle */
unsigned swiz[NIR_MAX_VEC_COMPONENTS] = { 0 };
b->cursor = nir_before_instr(instr);
nir_def *swizzled = nir_swizzle(b, vec->src[0].src.ssa, swiz,
num_components);
- nir_def_rewrite_uses(&vec->dest.dest.ssa, swizzled);
+ nir_def_rewrite_uses(&vec->def, swizzled);
}
nir_instr_remove(&vec->instr);
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(val.def->parent_instr);
- if (alu->dest.dest.ssa.num_components != 1)
+ if (alu->def.num_components != 1)
return false;
switch (alu->op) {
continue;
/* We need to dominate the use if we are going to rewrite it */
- if (!ssa_def_dominates_instr(&vec->dest.dest.ssa, use->parent_instr))
+ if (!ssa_def_dominates_instr(&vec->def, use->parent_instr))
continue;
/* For now, we'll just rewrite ALU instructions */
* Go ahead and rewrite it as needed.
*/
nir_instr_rewrite_src(use->parent_instr, use,
- nir_src_for_ssa(&vec->dest.dest.ssa));
+ nir_src_for_ssa(&vec->def));
for (unsigned j = 0; j < 4; j++) {
if (!nir_alu_instr_channel_used(use_alu, src_idx, j))
continue;
if (is_used_by_if(instr))
return true;
- nir_foreach_use(src, &instr->dest.dest.ssa) {
+ nir_foreach_use(src, &instr->def) {
const nir_instr *const user_instr = src->parent_instr;
if (user_instr->type != nir_instr_type_alu)
: nir_fadd(bld, a, nir_fneg(bld, b));
nir_def *const zero =
- nir_imm_floatN_t(bld, 0.0, orig_add->dest.dest.ssa.bit_size);
+ nir_imm_floatN_t(bld, 0.0, orig_add->def.bit_size);
nir_def *const cmp = zero_on_left
? nir_build_alu(bld, orig_cmp->op, zero, fadd, NULL, NULL)
* nir_search.c).
*/
nir_alu_instr *mov_add = nir_alu_instr_create(bld->shader, nir_op_mov);
- nir_def_init(&mov_add->instr, &mov_add->dest.dest.ssa,
- orig_add->dest.dest.ssa.num_components,
- orig_add->dest.dest.ssa.bit_size);
+ nir_def_init(&mov_add->instr, &mov_add->def,
+ orig_add->def.num_components,
+ orig_add->def.bit_size);
mov_add->src[0].src = nir_src_for_ssa(fadd);
nir_builder_instr_insert(bld, &mov_add->instr);
nir_alu_instr *mov_cmp = nir_alu_instr_create(bld->shader, nir_op_mov);
- nir_def_init(&mov_cmp->instr, &mov_cmp->dest.dest.ssa,
- orig_cmp->dest.dest.ssa.num_components,
- orig_cmp->dest.dest.ssa.bit_size);
+ nir_def_init(&mov_cmp->instr, &mov_cmp->def,
+ orig_cmp->def.num_components,
+ orig_cmp->def.bit_size);
mov_cmp->src[0].src = nir_src_for_ssa(cmp);
nir_builder_instr_insert(bld, &mov_cmp->instr);
- nir_def_rewrite_uses(&orig_cmp->dest.dest.ssa,
- &mov_cmp->dest.dest.ssa);
- nir_def_rewrite_uses(&orig_add->dest.dest.ssa,
- &mov_add->dest.dest.ssa);
+ nir_def_rewrite_uses(&orig_cmp->def,
+ &mov_cmp->def);
+ nir_def_rewrite_uses(&orig_add->def,
+ &mov_add->def);
/* We know these have no more uses because we just rewrote them all, so we
* can remove them.
nir_alu_instr *const alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.num_components != 1)
+ if (alu->def.num_components != 1)
continue;
static const uint8_t swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 };
*/
unsigned bit_size = 0;
if (!nir_alu_type_get_type_size(nir_op_infos[alu->op].output_type))
- bit_size = alu->dest.dest.ssa.bit_size;
+ bit_size = alu->def.bit_size;
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
if (bit_size == 0 &&
memset(dest, 0, sizeof(dest));
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; ++i)
srcs[i] = src[i];
- nir_eval_const_opcode(alu->op, dest, alu->dest.dest.ssa.num_components,
+ nir_eval_const_opcode(alu->op, dest, alu->def.num_components,
bit_size, srcs,
b->shader->info.float_controls_execution_mode);
b->cursor = nir_before_instr(&alu->instr);
- nir_def *imm = nir_build_imm(b, alu->dest.dest.ssa.num_components,
- alu->dest.dest.ssa.bit_size,
+ nir_def *imm = nir_build_imm(b, alu->def.num_components,
+ alu->def.bit_size,
dest);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, imm);
+ nir_def_rewrite_uses(&alu->def, imm);
nir_instr_remove(&alu->instr);
nir_instr_free(&alu->instr);
static bool
is_swizzleless_move(nir_alu_instr *instr)
{
- unsigned num_comp = instr->dest.dest.ssa.num_components;
+ unsigned num_comp = instr->def.num_components;
if (instr->src[0].src.ssa->num_components != num_comp)
return false;
nir_builder b = nir_builder_at(nir_after_instr(&mov->instr));
- unsigned num_comp = mov->dest.dest.ssa.num_components;
+ unsigned num_comp = mov->def.num_components;
nir_alu_instr *new_vec = nir_alu_instr_create(b.shader, nir_op_vec(num_comp));
for (unsigned i = 0; i < num_comp; i++)
new_vec->src[i] = vec->src[mov->src[0].swizzle[i]];
nir_def *new = nir_builder_alu_instr_finish_and_insert(&b, new_vec);
- nir_def_rewrite_uses(&mov->dest.dest.ssa, new);
+ nir_def_rewrite_uses(&mov->def, new);
/* If we remove "mov" and it's the next instruction in the
* nir_foreach_instr_safe() loop, then we would end copy-propagation early. */
bool progress = false;
- nir_foreach_use_including_if_safe(src, &mov->dest.dest.ssa) {
+ nir_foreach_use_including_if_safe(src, &mov->def) {
if (!src->is_if && src->parent_instr->type == nir_instr_type_alu)
progress |= copy_propagate_alu(container_of(src, nir_alu_src, src), mov);
else
progress |= copy_propagate(src, mov);
}
- if (progress && nir_def_is_unused(&mov->dest.dest.ssa))
+ if (progress && nir_def_is_unused(&mov->def))
nir_instr_remove(&mov->instr);
return progress;
return true;
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(instr);
- return is_def_live(&alu->dest.dest.ssa, defs_live);
+ return is_def_live(&alu->def, defs_live);
}
case nir_instr_type_deref: {
nir_deref_instr *deref = nir_instr_as_deref(instr);
alu->op != nir_op_irem)
return false;
- if (alu->dest.dest.ssa.bit_size < *min_bit_size)
+ if (alu->def.bit_size < *min_bit_size)
return false;
if (!nir_src_is_const(alu->src[1].src))
b->cursor = nir_before_instr(&alu->instr);
nir_def *q[NIR_MAX_VEC_COMPONENTS];
- for (unsigned comp = 0; comp < alu->dest.dest.ssa.num_components; comp++) {
+ for (unsigned comp = 0; comp < alu->def.num_components; comp++) {
/* Get the numerator for the channel */
nir_def *n = nir_channel(b, alu->src[0].src.ssa,
alu->src[0].swizzle[comp]);
}
}
- nir_def *qvec = nir_vec(b, q, alu->dest.dest.ssa.num_components);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, qvec);
+ nir_def *qvec = nir_vec(b, q, alu->def.num_components);
+ nir_def_rewrite_uses(&alu->def, qvec);
nir_instr_remove(&alu->instr);
return true;
if (!is_prev_result_undef && !is_prev_result_const) {
/* check if the only user is a trivial bcsel */
- if (!list_is_singular(&alu->dest.dest.ssa.uses))
+ if (!list_is_singular(&alu->def.uses))
continue;
- nir_src *use = list_first_entry(&alu->dest.dest.ssa.uses, nir_src, use_link);
+ nir_src *use = list_first_entry(&alu->def.uses, nir_src, use_link);
if (use->is_if || !is_trivial_bcsel(use->parent_instr, true))
continue;
}
/* Modify all readers of the original ALU instruction to read the
* result of the phi.
*/
- nir_def_rewrite_uses(&alu->dest.dest.ssa,
+ nir_def_rewrite_uses(&alu->def,
&phi->dest.ssa);
/* Since the original ALU instruction no longer has any readers, just
->src);
nir_def_init(&phi->instr, &phi->dest.ssa,
- bcsel->dest.dest.ssa.num_components,
- bcsel->dest.dest.ssa.bit_size);
+ bcsel->def.num_components,
+ bcsel->def.bit_size);
b->cursor = nir_after_phis(header_block);
nir_builder_instr_insert(b, &phi->instr);
/* Modify all readers of the bcsel instruction to read the result of
* the phi.
*/
- nir_def_rewrite_uses(&bcsel->dest.dest.ssa,
+ nir_def_rewrite_uses(&bcsel->def,
&phi->dest.ssa);
/* Since the original bcsel instruction no longer has any readers,
b->cursor = nir_after_instr(&alu_instr->instr);
nir_def *new_condition =
- nir_inot(b, &alu_instr->dest.dest.ssa);
+ nir_inot(b, &alu_instr->def);
nir_if_rewrite_condition(nif, nir_src_for_ssa(new_condition));
nir_alu_instr *nalu = nir_alu_instr_create(b->shader, alu->op);
nalu->exact = alu->exact;
- nir_def_init(&nalu->instr, &nalu->dest.dest.ssa,
- alu->dest.dest.ssa.num_components,
- alu->dest.dest.ssa.bit_size);
+ nir_def_init(&nalu->instr, &nalu->def,
+ alu->def.num_components,
+ alu->def.bit_size);
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
nalu->src[i].src = nir_src_for_ssa(src_defs[i]);
nir_builder_instr_insert(b, &nalu->instr);
- return &nalu->dest.dest.ssa;
+ return &nalu->def;
;
}
if (!use_src->is_if && can_propagate_through_alu(use_src)) {
nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr);
- nir_foreach_use_including_if_safe(alu_use, &alu->dest.dest.ssa)
+ nir_foreach_use_including_if_safe(alu_use, &alu->def)
progress |= propagate_condition_eval(b, nif, use_src, alu_use, alu);
}
break;
case nir_op_iand:
case nir_op_ior:
- if (alu->dest.dest.ssa.bit_size == 1 && options->optimize_quad_vote_to_reduce)
+ if (alu->def.bit_size == 1 && options->optimize_quad_vote_to_reduce)
replacement = try_opt_quad_vote(b, alu, block_has_discard);
break;
default:
}
if (replacement) {
- nir_def_rewrite_uses(&alu->dest.dest.ssa,
+ nir_def_rewrite_uses(&alu->def,
replacement);
nir_instr_remove(&alu->instr);
return true;
alu->op != nir_op_fmax && alu->op != nir_op_fmin && alu->exact)
return false;
- if (alu->dest.dest.ssa.num_components != 1)
+ if (alu->def.num_components != 1)
return false;
nir_alu_src *alu_src = list_entry(src, nir_alu_src, src);
nir_foreach_use_including_if_safe(src, &intrin->dest.ssa) {
/* Remove alu. */
nir_alu_instr *alu = nir_instr_as_alu(src->parent_instr);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, &intrin->dest.ssa);
+ nir_def_rewrite_uses(&alu->def, &intrin->dest.ssa);
nir_instr_remove(&alu->instr);
}
if (alu->op == nir_op_ine)
new_expr = nir_inot(b, new_expr);
- nir_def_rewrite_uses(&alu->dest.dest.ssa,
+ nir_def_rewrite_uses(&alu->def,
new_expr);
nir_instr_remove(&alu->instr);
progress = true;
(*count)++;
} else {
/* The only uses of this definition must be phis in the successor */
- nir_foreach_use_including_if(use, &mov->dest.dest.ssa) {
+ nir_foreach_use_including_if(use, &mov->def) {
if (use->is_if ||
use->parent_instr->type != nir_instr_type_phi ||
use->parent_instr->block != block->successors[0])
nir_src_copy(&sel->src[idx].src, &src->src, &sel->instr);
}
- nir_def_init(&sel->instr, &sel->dest.dest.ssa,
+ nir_def_init(&sel->instr, &sel->def,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_def_rewrite_uses(&phi->dest.ssa,
- &sel->dest.dest.ssa);
+ &sel->def);
nir_instr_insert_before(&phi->instr, &sel->instr);
nir_instr_remove(&phi->instr);
/* We also need to check that the conversion's dest was actually
* wider:
*/
- if (alu->dest.dest.ssa.bit_size <= *bit_size)
+ if (alu->def.bit_size <= *bit_size)
return INVALID_OP;
return alu->op;
/* The conversion we are stripping off could have had a swizzle,
* so replace it with a mov if necessary:
*/
- unsigned num_comp = alu->dest.dest.ssa.num_components;
+ unsigned num_comp = alu->def.num_components;
new_src = nir_mov_alu(b, alu->src[0], num_comp);
}
return false;
nir_alu_instr *bfiCD0 = nir_instr_as_alu(instr);
- if (bfiCD0->op != nir_op_bfi || bfiCD0->dest.dest.ssa.num_components != 1)
+ if (bfiCD0->op != nir_op_bfi || bfiCD0->def.num_components != 1)
return false;
/* Enforce the bfi('#c', d, 0) part of the pattern. */
if (!is_used_once(bfiCD0))
return false;
- nir_src *use = list_first_entry(&bfiCD0->dest.dest.ssa.uses,
+ nir_src *use = list_first_entry(&bfiCD0->def.uses,
nir_src, use_link);
if (use->parent_instr->type != nir_instr_type_alu)
return false;
nir_alu_instr *bfiABx = nir_instr_as_alu(use->parent_instr);
- if (bfiABx->op != nir_op_bfi || bfiABx->dest.dest.ssa.num_components != 1)
+ if (bfiABx->op != nir_op_bfi || bfiABx->def.num_components != 1)
return false;
/* Enforce the bfi('#a', b, ...) part of the pattern. */
if (!nir_src_is_const(bfiABx->src[0].src) ||
- bfiABx->src[2].src.ssa != &bfiCD0->dest.dest.ssa) {
+ bfiABx->src[2].src.ssa != &bfiCD0->def) {
return false;
}
nir_mov_alu(b, bfiABx->src[0], 1),
nir_mov_alu(b, bfiABx->src[1], 1)));
- nir_def_rewrite_uses(&bfiABx->dest.dest.ssa, new_bfi);
+ nir_def_rewrite_uses(&bfiABx->def, new_bfi);
return true;
}
static bool
all_uses_are_bcsel(const nir_alu_instr *instr)
{
- nir_foreach_use(use, &instr->dest.dest.ssa) {
+ nir_foreach_use(use, &instr->def) {
if (use->parent_instr->type != nir_instr_type_alu)
return false;
/* Not only must the result be used by a bcsel, but it must be used as
* the first source (the condition).
*/
- if (alu->src[0].src.ssa != &instr->dest.dest.ssa)
+ if (alu->src[0].src.ssa != &instr->def)
return false;
}
* instruction must be duplicated only once in each block because CSE
* cannot be run after this pass.
*/
- nir_foreach_use_including_if_safe(use, &alu->dest.dest.ssa) {
+ nir_foreach_use_including_if_safe(use, &alu->def) {
if (use->is_if) {
nir_if *const if_stmt = use->parent_if;
nir_instr_insert_after_block(prev_block, &clone->instr);
nir_if_rewrite_condition(if_stmt,
- nir_src_for_ssa(&clone->dest.dest.ssa));
+ nir_src_for_ssa(&clone->def));
progress = true;
} else {
nir_instr *const use_instr = use->parent_instr;
nir_alu_instr *const use_alu = nir_instr_as_alu(use_instr);
for (unsigned i = 0; i < nir_op_infos[use_alu->op].num_inputs; i++) {
- if (use_alu->src[i].src.ssa == &alu->dest.dest.ssa) {
+ if (use_alu->src[i].src.ssa == &alu->def) {
nir_instr_rewrite_src(&use_alu->instr,
&use_alu->src[i].src,
- nir_src_for_ssa(&clone->dest.dest.ssa));
+ nir_src_for_ssa(&clone->def));
progress = true;
}
}
static bool
opt_shrink_vector(nir_builder *b, nir_alu_instr *instr)
{
- nir_def *def = &instr->dest.dest.ssa;
+ nir_def *def = &instr->def;
unsigned mask = nir_def_components_read(def);
/* If nothing was read, leave it up to DCE. */
static bool
opt_shrink_vectors_alu(nir_builder *b, nir_alu_instr *instr)
{
- nir_def *def = &instr->dest.dest.ssa;
+ nir_def *def = &instr->def;
/* Nothing to shrink */
if (def->num_components == 1)
int src_idx = alu_src - &alu->src[0];
nir_component_mask_t src_read_mask = nir_alu_instr_src_read_mask(alu, src_idx);
- nir_def *alu_def = &alu->dest.dest.ssa;
+ nir_def *alu_def = &alu->def;
/* We don't mark the channels used if the only reader is the original phi.
* This can happen in the case of loops.
}
b->cursor = nir_before_instr(&alu->instr);
- nir_def *undef = nir_undef(b, alu->dest.dest.ssa.num_components,
- alu->dest.dest.ssa.bit_size);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, undef);
+ nir_def *undef = nir_undef(b, alu->def.num_components,
+ alu->def.bit_size);
+ nir_def_rewrite_uses(&alu->def, undef);
return true;
}
default:
return false;
}
- unsigned num_components = alu->dest.dest.ssa.num_components;
+ unsigned num_components = alu->def.num_components;
b->cursor = nir_before_instr(&alu->instr);
nir_def *def = nir_undef(b, num_components, 32);
- nir_def_rewrite_uses_after(&alu->dest.dest.ssa, def, &alu->instr);
+ nir_def_rewrite_uses_after(&alu->def, def, &alu->instr);
nir_instr_remove(&alu->instr);
return true;
}
nir_alu_instr *alu = nir_instr_as_alu(instr);
uint32_t hash = HASH(0, alu->op);
- hash = HASH(hash, alu->dest.dest.ssa.bit_size);
+ hash = HASH(hash, alu->def.bit_size);
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++)
hash = hash_alu_src(hash, &alu->src[i],
- alu->dest.dest.ssa.num_components,
+ alu->def.num_components,
instr->pass_flags);
return hash;
if (alu1->op != alu2->op)
return false;
- if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size)
+ if (alu1->def.bit_size != alu2->def.bit_size)
return false;
for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) {
return false;
/* no need to hash instructions which are already vectorized */
- if (alu->dest.dest.ssa.num_components >= instr->pass_flags)
+ if (alu->def.num_components >= instr->pass_flags)
return false;
if (nir_op_infos[alu->op].output_size != 0)
/* don't hash instructions which are already swizzled
* outside of max_components: these should better be scalarized */
uint32_t mask = ~(instr->pass_flags - 1);
- for (unsigned j = 1; j < alu->dest.dest.ssa.num_components; j++) {
+ for (unsigned j = 1; j < alu->def.num_components; j++) {
if ((alu->src[i].swizzle[0] & mask) != (alu->src[i].swizzle[j] & mask))
return false;
}
nir_alu_instr *alu1 = nir_instr_as_alu(instr1);
nir_alu_instr *alu2 = nir_instr_as_alu(instr2);
- assert(alu1->dest.dest.ssa.bit_size == alu2->dest.dest.ssa.bit_size);
- unsigned alu1_components = alu1->dest.dest.ssa.num_components;
- unsigned alu2_components = alu2->dest.dest.ssa.num_components;
+ assert(alu1->def.bit_size == alu2->def.bit_size);
+ unsigned alu1_components = alu1->def.num_components;
+ unsigned alu2_components = alu2->def.num_components;
unsigned total_components = alu1_components + alu2_components;
assert(instr1->pass_flags == instr2->pass_flags);
nir_builder b = nir_builder_at(nir_after_instr(instr1));
nir_alu_instr *new_alu = nir_alu_instr_create(b.shader, alu1->op);
- nir_def_init(&new_alu->instr, &new_alu->dest.dest.ssa, total_components,
- alu1->dest.dest.ssa.bit_size);
+ nir_def_init(&new_alu->instr, &new_alu->def, total_components,
+ alu1->def.bit_size);
new_alu->instr.pass_flags = alu1->instr.pass_flags;
/* If either channel is exact, we have to preserve it even if it's
nir_builder_instr_insert(&b, &new_alu->instr);
/* update all ALU uses */
- nir_foreach_use_safe(src, &alu1->dest.dest.ssa) {
+ nir_foreach_use_safe(src, &alu1->def) {
nir_instr *user_instr = src->parent_instr;
if (user_instr->type == nir_instr_type_alu) {
/* Check if user is found in the hashset */
* round-trip through copy propagation.
*/
nir_instr_rewrite_src(user_instr, src,
- nir_src_for_ssa(&new_alu->dest.dest.ssa));
+ nir_src_for_ssa(&new_alu->def));
/* Rehash user if it was found in the hashset */
if (entry && entry->key == user_instr) {
}
}
- nir_foreach_use_safe(src, &alu2->dest.dest.ssa) {
+ nir_foreach_use_safe(src, &alu2->def) {
if (src->parent_instr->type == nir_instr_type_alu) {
/* For ALU instructions, rewrite the source directly to avoid a
* round-trip through copy propagation.
*/
nir_instr_rewrite_src(src->parent_instr, src,
- nir_src_for_ssa(&new_alu->dest.dest.ssa));
+ nir_src_for_ssa(&new_alu->def));
nir_alu_src *alu_src = container_of(src, nir_alu_src, src);
nir_alu_instr *use = nir_instr_as_alu(src->parent_instr);
/* update all other uses if there are any */
unsigned swiz[NIR_MAX_VEC_COMPONENTS];
- if (!nir_def_is_unused(&alu1->dest.dest.ssa)) {
+ if (!nir_def_is_unused(&alu1->def)) {
for (unsigned i = 0; i < alu1_components; i++)
swiz[i] = i;
- nir_def *new_alu1 = nir_swizzle(&b, &new_alu->dest.dest.ssa, swiz,
+ nir_def *new_alu1 = nir_swizzle(&b, &new_alu->def, swiz,
alu1_components);
- nir_def_rewrite_uses(&alu1->dest.dest.ssa, new_alu1);
+ nir_def_rewrite_uses(&alu1->def, new_alu1);
}
- if (!nir_def_is_unused(&alu2->dest.dest.ssa)) {
+ if (!nir_def_is_unused(&alu2->def)) {
for (unsigned i = 0; i < alu2_components; i++)
swiz[i] = i + alu1_components;
- nir_def *new_alu2 = nir_swizzle(&b, &new_alu->dest.dest.ssa, swiz,
+ nir_def *new_alu2 = nir_swizzle(&b, &new_alu->def, swiz,
alu2_components);
- nir_def_rewrite_uses(&alu2->dest.dest.ssa, new_alu2);
+ nir_def_rewrite_uses(&alu2->def, new_alu2);
}
nir_instr_remove(instr1);
{
FILE *fp = state->fp;
- print_def(&instr->dest.dest.ssa, state);
+ print_def(&instr->def, state);
fprintf(fp, " = %s", nir_op_infos[instr->op].name);
if (instr->exact)
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (!def_is_invariant(&alu->dest.dest.ssa, invariants))
+ if (!def_is_invariant(&alu->def, invariants))
break;
alu->exact = true;
* question can eventually answered after the shader has been
* scalarized.
*/
- if (use_alu->dest.dest.ssa.num_components > 1)
+ if (use_alu->def.num_components > 1)
return all_bits;
switch (use_alu->op) {
(nir_bcsel(b, small, scaled_up_b, orig_b)));
nir_def *new_div = nir_fdiv(b, final_a, final_b);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, new_div);
+ nir_def_rewrite_uses(&alu->def, new_div);
return true;
}
return false;
if (expr->value.bit_size > 0 &&
- instr->dest.dest.ssa.bit_size != expr->value.bit_size)
+ instr->def.bit_size != expr->value.bit_size)
return false;
state->inexact_match = expr->inexact || state->inexact_match;
num_components = nir_op_infos[op].output_size;
nir_alu_instr *alu = nir_alu_instr_create(build->shader, op);
- nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components,
+ nir_def_init(&alu->instr, &alu->def, num_components,
dst_bit_size);
/* We have no way of knowing what values in a given search expression
nir_builder_instr_insert(build, &alu->instr);
- assert(alu->dest.dest.ssa.index ==
+ assert(alu->def.index ==
util_dynarray_num_elements(state->states, uint16_t));
util_dynarray_append(state->states, uint16_t, 0);
nir_algebraic_automaton(&alu->instr, state->states, state->pass_op_table);
nir_alu_src val;
- val.src = nir_src_for_ssa(&alu->dest.dest.ssa);
+ val.src = nir_src_for_ssa(&alu->def);
memcpy(val.swizzle, identity_swizzle, sizeof val.swizzle);
return val;
{
uint8_t swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 };
- for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i)
+ for (unsigned i = 0; i < instr->def.num_components; ++i)
swizzle[i] = i;
struct match_state state;
state.variables_seen = 0;
if (match_expression(table, search, instr,
- instr->dest.dest.ssa.num_components,
+ instr->def.num_components,
swizzle, &state)) {
found = true;
break;
dump_value(&search->value);
fprintf(stderr, " -> ");
dump_value(replace);
- fprintf(stderr, " ssa_%d\n", instr->dest.dest.ssa.index);
+ fprintf(stderr, " ssa_%d\n", instr->def.index);
#endif
/* If the instruction at the root of the expression tree being replaced is
state.states = states;
nir_alu_src val = construct_value(build, replace,
- instr->dest.dest.ssa.num_components,
- instr->dest.dest.ssa.bit_size,
+ instr->def.num_components,
+ instr->def.bit_size,
&state, &instr->instr);
/* Note that NIR builder will elide the MOV if it's a no-op, which may
* allow more work to be done in a single pass through algebraic.
*/
nir_def *ssa_val =
- nir_mov_alu(build, val, instr->dest.dest.ssa.num_components);
+ nir_mov_alu(build, val, instr->def.num_components);
if (ssa_val->index == util_dynarray_num_elements(states, uint16_t)) {
util_dynarray_append(states, uint16_t, 0);
nir_algebraic_automaton(ssa_val->parent_instr, states, table->pass_op_table);
/* Rewrite the uses of the old SSA value to the new one, and recurse
* through the uses updating the automaton's state.
*/
- nir_def_rewrite_uses(&instr->dest.dest.ssa, ssa_val);
+ nir_def_rewrite_uses(&instr->def, ssa_val);
nir_algebraic_update_automaton(ssa_val->parent_instr, algebraic_worklist,
states, table->pass_op_table);
}
uint16_t *state = util_dynarray_element(states, uint16_t,
- alu->dest.dest.ssa.index);
+ alu->def.index);
if (*state != tbl->table[index]) {
*state = tbl->table[index];
return true;
nir_alu_instr *alu = nir_instr_as_alu(instr);
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned bit_size = alu->def.bit_size;
const unsigned execution_mode =
build->shader->info.float_controls_execution_mode;
const bool ignore_inexact =
nir_is_denorm_flush_to_zero(execution_mode, bit_size);
int xform_idx = *util_dynarray_element(states, uint16_t,
- alu->dest.dest.ssa.index);
+ alu->def.index);
for (const struct transform *xform = &table->transforms[table->transform_offsets[xform_idx]];
xform->condition_offset != ~0;
xform++) {
static inline bool
is_used_once(const nir_alu_instr *instr)
{
- return list_is_singular(&instr->dest.dest.ssa.uses);
+ return list_is_singular(&instr->def.uses);
}
static inline bool
is_used_by_if(const nir_alu_instr *instr)
{
- return nir_def_used_by_if(&instr->dest.dest.ssa);
+ return nir_def_used_by_if(&instr->def);
}
static inline bool
static inline bool
is_used_by_non_fsat(const nir_alu_instr *instr)
{
- nir_foreach_use(src, &instr->dest.dest.ssa) {
+ nir_foreach_use(src, &instr->def) {
const nir_instr *const user_instr = src->parent_instr;
if (user_instr->type != nir_instr_type_alu)
static inline bool
is_only_used_as_float(const nir_alu_instr *instr)
{
- nir_foreach_use(src, &instr->dest.dest.ssa) {
+ nir_foreach_use(src, &instr->def) {
const nir_instr *const user_instr = src->parent_instr;
if (user_instr->type != nir_instr_type_alu)
return false;
static inline bool
is_only_used_by_fadd(const nir_alu_instr *instr)
{
- nir_foreach_use(src, &instr->dest.dest.ssa) {
+ nir_foreach_use(src, &instr->def) {
const nir_instr *const user_instr = src->parent_instr;
if (user_instr->type != nir_instr_type_alu)
return false;
static inline bool
only_lower_8_bits_used(const nir_alu_instr *instr)
{
- return (nir_def_bits_used(&instr->dest.dest.ssa) & ~0xffull) == 0;
+ return (nir_def_bits_used(&instr->def) & ~0xffull) == 0;
}
static inline bool
only_lower_16_bits_used(const nir_alu_instr *instr)
{
- return (nir_def_bits_used(&instr->dest.dest.ssa) & ~0xffffull) == 0;
+ return (nir_def_bits_used(&instr->def) & ~0xffffull) == 0;
}
/**
header.alu.writemask_or_two_swizzles |= alu->src[1].swizzle[0] << 2;
}
- write_def(ctx, &alu->dest.dest.ssa, header, alu->instr.type);
+ write_def(ctx, &alu->def, header, alu->instr.type);
if (header.alu.packed_src_ssa_16bit) {
for (unsigned i = 0; i < num_srcs; i++) {
alu->no_signed_wrap = header.alu.no_signed_wrap;
alu->no_unsigned_wrap = header.alu.no_unsigned_wrap;
- read_def(ctx, &alu->dest.dest.ssa, &alu->instr, header);
+ read_def(ctx, &alu->def, &alu->instr, header);
if (header.alu.packed_src_ssa_16bit) {
for (unsigned i = 0; i < num_srcs; i++) {
nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components);
nir_alu_instr *vec = nir_alu_instr_create(b->shader, vec_op);
- nir_def_init(&vec->instr, &vec->dest.dest.ssa,
+ nir_def_init(&vec->instr, &vec->def,
phi->dest.ssa.num_components, 64);
int num_comp[2] = { 2, phi->dest.ssa.num_components - 2 };
}
nir_alu_type dest_type = nir_op_infos[instr->op].output_type;
- unsigned dest_bit_size = instr->dest.dest.ssa.bit_size;
+ unsigned dest_bit_size = instr->def.bit_size;
if (nir_alu_type_get_type_size(dest_type)) {
validate_assert(state, dest_bit_size == nir_alu_type_get_type_size(dest_type));
} else if (instr_bit_size) {
dest_bit_size == 64);
}
- validate_def(&instr->dest.dest.ssa, state, 0, 0);
+ validate_def(&instr->def, state, 0, 0);
}
static void
nir_builder_alu_instr_finish_and_insert(&bld, flt);
- flt->dest.dest.ssa.num_components = 1;
+ flt->def.num_components = 1;
- nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
+ nir_if *nif = nir_push_if(&bld, &flt->def);
nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd);
nir_builder_alu_instr_finish_and_insert(&bld, fadd);
- fadd->dest.dest.ssa.num_components = 1;
+ fadd->def.num_components = 1;
nir_pop_if(&bld, nif);
nir_builder_alu_instr_finish_and_insert(&bld, flt);
- flt->dest.dest.ssa.num_components = 1;
+ flt->def.num_components = 1;
- nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa);
+ nir_if *nif = nir_push_if(&bld, &flt->def);
nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd);
nir_builder_alu_instr_finish_and_insert(&bld, fadd);
- fadd->dest.dest.ssa.num_components = 2;
+ fadd->def.num_components = 2;
nir_pop_if(&bld, nif);
instr->src[1].src = nir_src_for_ssa(src1);
instr->src[1].swizzle[0] = 1;
- nir_def_init(&instr->instr, &instr->dest.dest.ssa, 1, 32);
+ nir_def_init(&instr->instr, &instr->def, 1, 32);
nir_builder_instr_insert(b, &instr->instr);
- return &instr->dest.dest.ssa;
+ return &instr->def;
}
TEST_F(nir_mod_analysis_test, const_val)
if (alu == NULL)
return NULL;
- alu->dest.dest.ssa.num_components = 1;
+ alu->def.num_components = 1;
return alu;
}
{
nir_op op = nir_op_vec(num_components);
nir_alu_instr *vec = nir_alu_instr_create(b->shader, op);
- nir_def_init(&vec->instr, &vec->dest.dest.ssa, num_components, bit_size);
+ nir_def_init(&vec->instr, &vec->def, num_components, bit_size);
return vec;
}
nir_builder_instr_insert(&b->nb, &vec->instr);
- return &vec->dest.dest.ssa;
+ return &vec->def;
}
/*
nir_builder_instr_insert(&b->nb, &vec->instr);
- return &vec->dest.dest.ssa;
+ return &vec->def;
}
static struct vtn_ssa_value *
unsigned bs[info->num_inputs]; /* bit size */
struct ir3_block *b = ctx->block;
unsigned dst_sz, wrmask;
- type_t dst_type = type_uint_size(alu->dest.dest.ssa.bit_size);
+ type_t dst_type = type_uint_size(alu->def.bit_size);
- dst_sz = alu->dest.dest.ssa.num_components;
+ dst_sz = alu->def.num_components;
wrmask = (1 << dst_sz) - 1;
- dst = ir3_get_def(ctx, &alu->dest.dest.ssa, dst_sz);
+ dst = ir3_get_def(ctx, &alu->def, dst_sz);
/* Vectors are special in that they have non-scalarized writemasks,
* and just take the first swizzle channel for each argument in
dst[i] = ir3_MOV(b, src[i], dst_type);
}
- ir3_put_def(ctx, &alu->dest.dest.ssa);
+ ir3_put_def(ctx, &alu->def);
return;
}
}
}
- ir3_put_def(ctx, &alu->dest.dest.ssa);
+ ir3_put_def(ctx, &alu->def);
return;
}
/* General case: We can just grab the one used channel per src. */
- assert(alu->dest.dest.ssa.num_components == 1);
+ assert(alu->def.num_components == 1);
for (int i = 0; i < info->num_inputs; i++) {
nir_alu_src *asrc = &alu->src[i];
dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
break;
case nir_op_imul:
- compile_assert(ctx, alu->dest.dest.ssa.bit_size == 16);
+ compile_assert(ctx, alu->def.bit_size == 16);
dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
break;
case nir_op_imul24:
}
if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
- assert(alu->dest.dest.ssa.bit_size == 1 || alu->op == nir_op_b2b32);
+ assert(alu->def.bit_size == 1 || alu->op == nir_op_b2b32);
assert(dst_sz == 1);
} else {
/* 1-bit values stored in 32-bit registers are only valid for certain
case nir_op_bcsel:
break;
default:
- compile_assert(ctx, alu->dest.dest.ssa.bit_size != 1);
+ compile_assert(ctx, alu->def.bit_size != 1);
}
}
- ir3_put_def(ctx, &alu->dest.dest.ssa);
+ ir3_put_def(ctx, &alu->def);
}
static void
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu = nir_instr_as_alu(instr);
- unsigned components = alu->dest.dest.ssa.num_components;
+ unsigned components = alu->def.num_components;
switch (alu->op) {
/* cat4 */
case nir_op_frcp:
case nir_op_f2f16:
case nir_op_f2fmp:
case nir_op_fneg:
- return all_uses_float(&alu->dest.dest.ssa, true) ? 0 : 1 * components;
+ return all_uses_float(&alu->def, true) ? 0 : 1 * components;
case nir_op_fabs:
- return all_uses_float(&alu->dest.dest.ssa, false) ? 0 : 1 * components;
+ return all_uses_float(&alu->def, false) ? 0 : 1 * components;
case nir_op_inot:
- return all_uses_bit(&alu->dest.dest.ssa) ? 0 : 1 * components;
+ return all_uses_bit(&alu->def) ? 0 : 1 * components;
/* Instructions that become vector split/collect */
case nir_op_vec2:
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMValueRef src[NIR_MAX_VEC_COMPONENTS];
unsigned src_bit_size[NIR_MAX_VEC_COMPONENTS];
- const unsigned num_components = instr->dest.dest.ssa.num_components;
+ const unsigned num_components = instr->def.num_components;
unsigned src_components;
switch (instr->op) {
result[c] = do_alu_action(bld_base, instr, src_bit_size, src_chan);
result[c] = cast_type(bld_base, result[c],
nir_op_infos[instr->op].output_type,
- instr->dest.dest.ssa.bit_size);
+ instr->def.bit_size);
}
}
- assign_ssa_dest(bld_base, &instr->dest.dest.ssa, result);
+ assign_ssa_dest(bld_base, &instr->def, result);
}
!(src.src.is_ssa && src.src.ssa->parent_instr->type == nir_instr_type_ssa_undef)) {
int chan1 = 1;
if (nir_op_infos[instr->op].input_sizes[i] == 0) {
- chan1 = instr->dest.dest.ssa.num_components > 1 ? 1 : 0;
+ chan1 = instr->def.num_components > 1 ? 1 : 0;
}
usrc = ureg_swizzle(usrc,
src.swizzle[0] * 2,
struct ureg_src src[4];
struct ureg_dst dst;
unsigned i;
- int dst_64 = instr->dest.dest.ssa.bit_size == 64;
+ int dst_64 = instr->def.bit_size == 64;
int src_64 = nir_src_bit_size(instr->src[0].src) == 64;
int num_srcs = nir_op_infos[instr->op].num_inputs;
for (; i < ARRAY_SIZE(src); i++)
src[i] = ureg_src_undef();
- dst = ntt_get_alu_dest(c, &instr->dest.dest.ssa);
+ dst = ntt_get_alu_dest(c, &instr->def);
static enum tgsi_opcode op_map[][2] = {
[nir_op_mov] = { TGSI_OPCODE_MOV, TGSI_OPCODE_MOV },
}
int src_bit_size = nir_src_bit_size(alu->src[0].src);
- int dst_bit_size = alu->dest.dest.ssa.bit_size;
+ int dst_bit_size = alu->def.bit_size;
if (src_bit_size == 64 || dst_bit_size == 64) {
/* Avoid vectorizing 64-bit instructions at all. Despite tgsi.rst
{
const nir_alu_instr *alu = nir_instr_as_alu(instr);
- return (alu->dest.dest.ssa.bit_size == 64 ||
+ return (alu->def.bit_size == 64 ||
nir_src_bit_size(alu->src[0].src) == 64);
}
return false;
nir_alu_instr *alu = nir_instr_as_alu(instr);
- int dst_32 = alu->dest.dest.ssa.bit_size == 32;
+ int dst_32 = alu->def.bit_size == 32;
int src_64 = nir_src_bit_size(alu->src[0].src) == 64;
if (src_64 && dst_32) {
static bool
vec_dest_has_swizzle(nir_alu_instr *vec, nir_def *ssa)
{
- for (unsigned i = 0; i < vec->dest.dest.ssa.num_components; i++) {
+ for (unsigned i = 0; i < vec->def.num_components; i++) {
if (vec->src[i].src.ssa != ssa)
continue;
assert(!(alu->op >= nir_op_vec2 && alu->op <= nir_op_vec4));
unsigned dst_swiz;
- hw_dst dst = ra_def(c, &alu->dest.dest.ssa, &dst_swiz);
+ hw_dst dst = ra_def(c, &alu->def, &dst_swiz);
switch (alu->op) {
case nir_op_fdot2:
unsigned num_components = 1;
- for (unsigned i = start_idx + 1; i < vec->dest.dest.ssa.num_components; i++) {
+ for (unsigned i = start_idx + 1; i < vec->def.num_components; i++) {
if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src) &&
is_src_mod_neg(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx) &&
is_src_mod_abs(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx)) {
}
}
- nir_def_init(&mov->instr, &mov->dest.dest.ssa, num_components, 32);
+ nir_def_init(&mov->instr, &mov->def, num_components, 32);
/* replace vec srcs with inserted mov */
for (unsigned i = 0, j = 0; i < 4; i++) {
if (!(write_mask & (1 << i)))
continue;
- nir_instr_rewrite_src(&vec->instr, &vec->src[i].src, nir_src_for_ssa(&mov->dest.dest.ssa));
+ nir_instr_rewrite_src(&vec->instr, &vec->src[i].src, nir_src_for_ssa(&mov->def));
vec->src[i].swizzle[0] = j++;
}
if (cv) {
/* Validate that we are only using ETNA_UNIFORM_CONSTANT const_values. */
- for (unsigned i = 0; i < parent->dest.dest.ssa.num_components; i++) {
+ for (unsigned i = 0; i < parent->def.num_components; i++) {
if (cv[i].u64 >> 32 != ETNA_UNIFORM_CONSTANT) {
cv = NULL;
break;
if (!cv)
continue;
- unsigned num_components = info->input_sizes[i] ?: alu->dest.dest.ssa.num_components;
+ unsigned num_components = info->input_sizes[i] ?: alu->def.num_components;
for (unsigned j = 0; j < num_components; j++) {
int idx = const_add(&value[0].u64, cv[alu->src[i].swizzle[j]].u64);
swizzle[i][j] = idx;
nir_def *def = nir_build_imm(&b, num_components, 32, value);
if (num_components == info->num_inputs) {
- nir_def_rewrite_uses(&alu->dest.dest.ssa, def);
+ nir_def_rewrite_uses(&alu->def, def);
nir_instr_remove(&alu->instr);
return;
}
}
unsigned finished_write_mask = 0;
- for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) {
+ for (unsigned i = 0; i < alu->def.num_components; i++) {
nir_def *ssa = alu->src[i].src.ssa;
/* check that vecN instruction is only user of this */
assert(!(instr->pass_flags & BYPASS_SRC));
instr->pass_flags |= BYPASS_DST;
- return real_def(&alu->dest.dest.ssa, swiz, mask);
+ return real_def(&alu->def, swiz, mask);
}
if (can_bypass_src && !(p_instr->pass_flags & BYPASS_DST)) {
switch (instr->type) {
case nir_instr_type_alu:
- def = &nir_instr_as_alu(instr)->dest.dest.ssa;
+ def = &nir_instr_as_alu(instr)->def;
break;
case nir_instr_type_tex:
def = &nir_instr_as_tex(instr)->dest.ssa;
for (unsigned i = tex->coord_components; i < 4; i++)
vec->src[i].src = nir_src_for_ssa(src1->ssa);
- nir_def_init(&vec->instr, &vec->dest.dest.ssa, 4, 32);
+ nir_def_init(&vec->instr, &vec->def, 4, 32);
nir_tex_instr_remove_src(tex, src1_idx);
- nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->dest.dest.ssa));
+ nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->def));
tex->coord_components = 4;
nir_instr_insert_before(&tex->instr, &vec->instr);
if (has_new_transcendentals && (
alu->op == nir_op_fdiv || alu->op == nir_op_flog2 ||
alu->op == nir_op_fsin || alu->op == nir_op_fcos)) {
- nir_def *ssa = &alu->dest.dest.ssa;
+ nir_def *ssa = &alu->def;
assert(ssa->num_components == 1);
mul->src[0].src = mul->src[1].src = nir_src_for_ssa(ssa);
mul->src[1].swizzle[0] = 1;
- nir_def_init(&mul->instr, &mul->dest.dest.ssa, 1, 32);
+ nir_def_init(&mul->instr, &mul->def, 1, 32);
alu->src[0].swizzle[1] = 0;
ssa->num_components = 2;
nir_instr_insert_after(instr, &mul->instr);
- nir_def_rewrite_uses_after(ssa, &mul->dest.dest.ssa,
+ nir_def_rewrite_uses_after(ssa, &mul->def,
&mul->instr);
}
}
alu->src[i].swizzle[j] = parent->src[0].swizzle[alu->src[i].swizzle[j]];
}
- if (nir_def_is_unused(&parent->dest.dest.ssa))
+ if (nir_def_is_unused(&parent->def))
nir_instr_remove(&parent->instr);
progress = true;
emit_alu(struct ir2_context *ctx, nir_alu_instr *alu)
{
const nir_op_info *info = &nir_op_infos[alu->op];
- nir_def *def = &alu->dest.dest.ssa;
+ nir_def *def = &alu->def;
struct ir2_instr *instr;
struct ir2_src tmp;
unsigned ncomp;
instr = instr_create_alu(ctx, alu->op, ncomp);
nir_legacy_alu_dest legacy_dest =
- nir_legacy_chase_alu_dest(&alu->dest.dest.ssa);
+ nir_legacy_chase_alu_dest(&alu->def);
set_legacy_index(ctx, legacy_dest.dest, instr);
instr->alu.saturate = legacy_dest.fsat;
instr->alu.write_mask = legacy_dest.write_mask;
if (instr->op == nir_op_mov) {
gpir_node *child = gpir_node_find(block, &instr->src[0].src,
instr->src[0].swizzle[0]);
- register_node_ssa(block, child, &instr->dest.dest.ssa);
+ register_node_ssa(block, child, &instr->def);
return true;
}
}
list_addtail(&node->node.list, &block->node_list);
- register_node_ssa(block, &node->node, &instr->dest.dest.ssa);
+ register_node_ssa(block, &node->node, &instr->def);
return true;
}
uint8_t swizzle = alu->src[0].swizzle[0];
int i;
- for (i = 1; i < alu->dest.dest.ssa.num_components; i++)
+ for (i = 1; i < alu->def.num_components; i++)
if (alu->src[0].swizzle[i] != (swizzle + i))
break;
- if (i != alu->dest.dest.ssa.num_components)
+ if (i != alu->def.num_components)
return false;
/* mali4xx can't access unaligned vec3, don't split load input */
- if (alu->dest.dest.ssa.num_components == 3 && swizzle > 0)
+ if (alu->def.num_components == 3 && swizzle > 0)
return false;
/* mali4xx can't access unaligned vec2, don't split load input */
- if (alu->dest.dest.ssa.num_components == 2 &&
+ if (alu->def.num_components == 2 &&
swizzle != 0 && swizzle != 2)
return false;
b->shader,
intrin->intrinsic);
nir_def_init(&new_intrin->instr, &new_intrin->dest.ssa,
- alu->dest.dest.ssa.num_components, ssa->bit_size);
- new_intrin->num_components = alu->dest.dest.ssa.num_components;
+ alu->def.num_components, ssa->bit_size);
+ new_intrin->num_components = alu->def.num_components;
nir_intrinsic_set_base(new_intrin, nir_intrinsic_base(intrin));
nir_intrinsic_set_component(new_intrin, nir_intrinsic_component(intrin) + swizzle);
nir_intrinsic_set_dest_type(new_intrin, nir_intrinsic_dest_type(intrin));
nir_src_copy(&new_intrin->src[0], &intrin->src[0], &new_intrin->instr);
nir_builder_instr_insert(b, &new_intrin->instr);
- nir_def_rewrite_uses(&alu->dest.dest.ssa,
+ nir_def_rewrite_uses(&alu->def,
&new_intrin->dest.ssa);
nir_instr_remove(&alu->instr);
return true;
static bool ppir_emit_alu(ppir_block *block, nir_instr *ni)
{
nir_alu_instr *instr = nir_instr_as_alu(ni);
- nir_def *def = &instr->dest.dest.ssa;
+ nir_def *def = &instr->def;
int op = nir_to_ppir_opcodes[instr->op];
if (op == ppir_op_unsupported) {
return false;
}
- int num_components = alu->dest.dest.ssa.num_components;
+ int num_components = alu->def.num_components;
uint8_t swizzle = alu->src[0].swizzle[0];
static Pin
pin_for_components(const nir_alu_instr& alu)
{
- return alu.dest.dest.ssa.num_components == 1 ? pin_free : pin_none;
+ return alu.def.num_components == 1 ? pin_free : pin_none;
}
static bool
swz[1] = 0;
}
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_chan),
+ value_factory.dest(alu.def, 2 * i, pin_chan),
value_factory.src64(alu.src[0], i, swz[0]),
{alu_write});
group->add_instruction(ir);
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_chan),
+ value_factory.dest(alu.def, 2 * i + 1, pin_chan),
value_factory.src64(alu.src[0], i, swz[1]),
{alu_write});
group->add_instruction(ir);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_free),
+ value_factory.dest(alu.def, 2 * i + c, pin_free),
value_factory.src64(alu.src[0], i, c),
{alu_write});
shader.emit_instruction(ir);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_chan),
+ value_factory.dest(alu.def, 2 * i + c, pin_chan),
value_factory.src64(alu.src[0], i, c),
{alu_write});
shader.emit_instruction(ir);
{
auto& value_factory = shader.value_factory();
- assert(alu.dest.dest.ssa.num_components == 1);
+ assert(alu.def.num_components == 1);
shader.emit_instruction(new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
AluInstr::write));
auto ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
+ value_factory.dest(alu.def, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
AluInstr::last_write);
ir->set_source_mod(0, AluInstr::mod_abs);
{
auto& value_factory = shader.value_factory();
- assert(alu.dest.dest.ssa.num_components == 1);
+ assert(alu.def.num_components == 1);
if (try_propagat_fsat64(alu, shader)) {
auto ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
AluInstr::write);
shader.emit_instruction(ir);
shader.emit_instruction(new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
+ value_factory.dest(alu.def, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
AluInstr::last_write));
} else {
auto group = new AluGroup();
auto ir = new AluInstr(op2_add_64,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
value_factory.literal(0),
AluInstr::write);
group->add_instruction(ir);
group->add_instruction(new AluInstr(op2_add_64,
- value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
+ value_factory.dest(alu.def, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
value_factory.literal(0),
AluInstr::last_write));
int num_emit0 = opcode == op2_mul_64 ? 3 : 1;
- assert(num_emit0 == 1 || alu.dest.dest.ssa.num_components == 1);
+ assert(num_emit0 == 1 || alu.def.num_components == 1);
- for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
+ for (unsigned k = 0; k < alu.def.num_components; ++k) {
int i = 0;
for (; i < num_emit0; ++i) {
- auto dest = i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan)
+ auto dest = i < 2 ? value_factory.dest(alu.def, i, pin_chan)
: value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
}
auto dest =
- i == 1 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i);
+ i == 1 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
dest,
AluInstr::SrcValues src(4);
- for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
- auto dest = value_factory.dest(alu.dest.dest.ssa, 2 * k, pin_chan);
+ for (unsigned k = 0; k < alu.def.num_components; ++k) {
+ auto dest = value_factory.dest(alu.def, 2 * k, pin_chan);
src[0] = value_factory.src64(alu.src[order[0]], k, 1);
src[1] = value_factory.src64(alu.src[order[1]], k, 1);
src[2] = value_factory.src64(alu.src[order[0]], k, 0);
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 3; ++i) {
ir = new AluInstr(opcode,
- i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan)
+ i < 2 ? value_factory.dest(alu.def, i, pin_chan)
: value_factory.dummy_dest(i),
value_factory.src64(alu.src[0], 0, 1),
value_factory.src64(alu.src[0], 0, 0),
int chan = i < 3 ? 1 : 0;
auto dest =
- i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i);
+ i < 2 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
dest,
auto group = new AluGroup();
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(op2_and_int,
- value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_group),
+ value_factory.dest(alu.def, 2 * i, pin_group),
value_factory.src(alu.src[0], i),
value_factory.zero(),
{alu_write});
group->add_instruction(ir);
ir = new AluInstr(op2_and_int,
- value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_group),
+ value_factory.dest(alu.def, 2 * i + 1, pin_group),
value_factory.src(alu.src[0], i),
value_factory.literal(0x3ff00000),
{alu_write});
auto group = new AluGroup();
AluInstr *ir = nullptr;
- assert(alu.dest.dest.ssa.num_components == 1);
+ assert(alu.def.num_components == 1);
auto tmpx = value_factory.temp_register();
shader.emit_instruction(new AluInstr(op2_and_int,
group = new AluGroup();
ir = new AluInstr(op2_add_64,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
tmpy3,
tmpw3,
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op2_add_64,
- value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
+ value_factory.dest(alu.def, 1, pin_chan),
tmpx3,
tmpz3,
AluInstr::write);
auto group = new AluGroup();
AluInstr *ir = nullptr;
- assert(alu.dest.dest.ssa.num_components == 1);
+ assert(alu.def.num_components == 1);
ir = new AluInstr(op1_flt32_to_flt64,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
value_factory.src(alu.src[0], 0),
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op1_flt32_to_flt64,
- value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
+ value_factory.dest(alu.def, 1, pin_chan),
value_factory.zero(),
AluInstr::last_write);
group->add_instruction(ir);
AluInstr *ir = nullptr;
ir = new AluInstr(op1v_flt64_to_flt32,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
+ value_factory.dest(alu.def, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
{alu_write});
group->add_instruction(ir);
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
auto src = value_factory.src(alu.src[0], i);
ir = new AluInstr(op2_and_int,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
src,
value_factory.inline_const(mask, 0),
{alu_write});
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.src(alu.src[0], i),
{alu_write});
switch (mod) {
auto pin = pin_for_components(alu);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.src(*src0, i),
value_factory.src(*src1, i),
{alu_write});
auto pin = pin_for_components(alu);
AluInstr *ir = nullptr;
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.src(*src[0], i),
value_factory.src(*src[1], i),
value_factory.src(*src[2], i),
opcode = (opcode == op2_setne_dx10) ? op2_or_int : op2_and_int;
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
tmp[0],
tmp[1],
AluInstr::last_write);
op = (op == op2_sete) ? op2_setne_dx10 : op2_sete_dx10;
ir = new AluInstr(op,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
max_val,
value_factory.inline_const(ALU_SRC_1, 0),
AluInstr::last_write);
AluInstr *ir = nullptr;
PRegister v[6];
- auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
+ auto dest = value_factory.dest(alu.def, 0, pin_free);
for (int i = 0; i < nc + nc / 2; ++i)
v[i] = value_factory.temp_register();
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
- auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_chan);
+ auto dest = value_factory.dest(alu.def, 0, pin_chan);
AluInstr::SrcValues srcs(2 * n);
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
- auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
+ auto dest = value_factory.dest(alu.def, 0, pin_free);
AluInstr::SrcValues srcs(8);
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
- auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
+ auto dest = value_factory.dest(alu.def, 0, pin_free);
AluInstr::SrcValues srcs(8);
for (unsigned i = 0; i < nc; ++i) {
auto src = value_factory.src(instr.src[i].src, instr.src[i].swizzle[0]);
- auto dst = value_factory.dest(instr.dest.dest.ssa, i, pin_none);
+ auto dst = value_factory.dest(instr.def, i, pin_none);
shader.emit_instruction(new AluInstr(op1_mov, dst, src, {alu_write}));
}
auto& value_factory = shader.value_factory();
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.zero(),
value_factory.src(alu.src[0], i),
AluInstr::write);
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, i, pin_none),
+ value_factory.dest(alu.def, i, pin_none),
value_factory.src(alu.src[i], 0),
AluInstr::write);
shader.emit_instruction(ir);
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, i, pin_none),
+ value_factory.dest(alu.def, i, pin_none),
value_factory.src(alu.src[0], i),
AluInstr::write);
shader.emit_instruction(ir);
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, i, pin_none),
+ value_factory.dest(alu.def, i, pin_none),
value_factory.src64(alu.src[0], 0, i),
AluInstr::write);
shader.emit_instruction(ir);
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, i, pin_chan),
+ value_factory.dest(alu.def, i, pin_chan),
value_factory.src64(alu.src[0], 0, i),
AluInstr::write);
shader.emit_instruction(ir);
}
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, i + 2, pin_chan),
+ value_factory.dest(alu.def, i + 2, pin_chan),
value_factory.src64(alu.src[1], 1, i),
AluInstr::write);
shader.emit_instruction(ir);
new AluInstr(op2_lshl_int, yy, y, value_factory.literal(16), AluInstr::last_write));
shader.emit_instruction(new AluInstr(op2_or_int,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
x,
yy,
AluInstr::last_write));
{
auto& value_factory = shader.value_factory();
shader.emit_instruction(new AluInstr(op1_mov,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
value_factory.src64(alu.src[0], 0, comp),
AluInstr::last_write));
return true;
{
auto& value_factory = shader.value_factory();
shader.emit_instruction(new AluInstr(op1_flt16_to_flt32,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
value_factory.src(alu.src[0], 0),
AluInstr::last_write));
return true;
AluInstr::last_write));
shader.emit_instruction(new AluInstr(op1_flt16_to_flt32,
- value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
+ value_factory.dest(alu.def, 0, pin_free),
tmp,
AluInstr::last_write));
return true;
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.src(src0, i),
AluInstr::last_write);
ir->set_alu_flag(alu_is_trans);
PRegister reg[4];
- int num_comp = alu.dest.dest.ssa.num_components;
+ int num_comp = alu.def.num_components;
for (int i = 0; i < num_comp; ++i) {
reg[i] = value_factory.temp_register();
auto pin = pin_for_components(alu);
for (int i = 0; i < num_comp; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
reg[i],
AluInstr::write);
if (opcode == op1_flt_to_uint) {
const std::set<AluModifiers> flags({alu_write, alu_last_instr, alu_is_cayman_trans});
- for (unsigned j = 0; j < alu.dest.dest.ssa.num_components; ++j) {
+ for (unsigned j = 0; j < alu.def.num_components; ++j) {
unsigned ncomp = j == 3 ? 4 : 3;
AluInstr::SrcValues srcs(ncomp);
- PRegister dest = value_factory.dest(alu.dest.dest.ssa, j, pin, (1 << ncomp) - 1);
+ PRegister dest = value_factory.dest(alu.def, j, pin, (1 << ncomp) - 1);
for (unsigned i = 0; i < ncomp; ++i)
srcs[i] = value_factory.src(src0, j);
AluInstr *ir = nullptr;
auto pin = pin_for_components(alu);
- for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu.def.num_components; ++i) {
ir = new AluInstr(opcode,
- value_factory.dest(alu.dest.dest.ssa, i, pin),
+ value_factory.dest(alu.def, i, pin),
value_factory.src(src0, i),
value_factory.src(src1, i),
AluInstr::last_write);
const std::set<AluModifiers> flags({alu_write, alu_last_instr, alu_is_cayman_trans});
- for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) {
+ for (unsigned k = 0; k < alu.def.num_components; ++k) {
AluInstr::SrcValues srcs(2 * last_slot);
- PRegister dest = value_factory.dest(alu.dest.dest.ssa, k, pin_free);
+ PRegister dest = value_factory.dest(alu.def, k, pin_free);
for (unsigned i = 0; i < last_slot; ++i) {
srcs[2 * i] = value_factory.src(src0, k);
{
auto& value_factory = shader.value_factory();
- int ncomp = alu.dest.dest.ssa.num_components;
+ int ncomp = alu.def.num_components;
RegisterVec4::Swizzle src_swz = {7, 7, 7, 7};
RegisterVec4::Swizzle tmp_swz = {7, 7, 7, 7};
for (auto i = 0; i < ncomp; ++i) {
if (mv)
mv->set_alu_flag(alu_last_instr);
- auto dst = value_factory.dest_vec4(alu.dest.dest.ssa, pin_group);
+ auto dst = value_factory.dest_vec4(alu.def, pin_group);
RegisterVec4::Swizzle dst_swz = {7, 7, 7, 7};
for (auto i = 0; i < ncomp; ++i) {
dst_swz[i] = i;
for (int i = 0; i < 4; ++i) {
ir = new AluInstr(op2_cube,
- value_factory.dest(alu.dest.dest.ssa, i, pin_chan),
+ value_factory.dest(alu.def, i, pin_chan),
value_factory.src(alu.src[0], src0_chan[i]),
value_factory.src(alu.src[0], src1_chan[i]),
AluInstr::write);
auto alu = nir_instr_as_alu(instr);
switch (alu->op) {
case nir_op_bcsel:
- return alu->dest.dest.ssa.bit_size == 64;
+ return alu->def.bit_size == 64;
case nir_op_f2i32:
case nir_op_f2u32:
case nir_op_f2i64:
auto alu = nir_instr_as_alu(instr);
switch (alu->op) {
case nir_op_bcsel:
- if (alu->dest.dest.ssa.num_components < 3)
+ if (alu->def.num_components < 3)
return false;
- return alu->dest.dest.ssa.bit_size == 64;
+ return alu->def.bit_size == 64;
case nir_op_bany_fnequal3:
case nir_op_bany_fnequal4:
case nir_op_ball_fequal3:
LowerSplit64BitVar::split_bcsel(nir_alu_instr *alu)
{
static nir_def *dest[4];
- for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; ++i) {
+ for (unsigned i = 0; i < alu->def.num_components; ++i) {
dest[i] = nir_bcsel(b,
nir_channel(b, alu->src[0].src.ssa, i),
nir_channel(b, alu->src[1].src.ssa, i),
nir_channel(b, alu->src[2].src.ssa, i));
}
- return nir_vec(b, dest, alu->dest.dest.ssa.num_components);
+ return nir_vec(b, dest, alu->def.num_components);
}
nir_def *
}
case nir_instr_type_alu: {
auto alu = nir_instr_as_alu(instr);
- return alu->dest.dest.ssa.bit_size == 64;
+ return alu->def.bit_size == 64;
}
case nir_instr_type_phi: {
auto phi = nir_instr_as_phi(instr);
}
case nir_instr_type_alu: {
auto alu = nir_instr_as_alu(instr);
- alu->dest.dest.ssa.bit_size = 32;
- alu->dest.dest.ssa.num_components *= 2;
+ alu->def.bit_size = 32;
+ alu->def.num_components *= 2;
switch (alu->op) {
case nir_op_pack_64_2x32_split:
alu->op = nir_op_vec2;
k += s->num_components;
}
- nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_comp, 32);
+ nir_def_init(&instr->instr, &instr->def, num_comp, 32);
nir_builder_instr_insert(b, &instr->instr);
- return &instr->dest.dest.ssa;
+ return &instr->def;
}
} // namespace r600
auto sum = nir_fadd(&b, c1, c2);
auto alu = nir_instr_as_alu(sum->parent_instr);
- sfn_log << SfnLog::reg << "Search (test) " << &alu->dest << "\n";
- auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_none);
+ sfn_log << SfnLog::reg << "Search (test) " << &alu->def << "\n";
+ auto dest_value = factory->dest(alu->def, 0, pin_none);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 0);
EXPECT_EQ(dest_value->pin(), pin_none);
auto sum = nir_fadd(&b, c1, c2);
auto alu = nir_instr_as_alu(sum->parent_instr);
- auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_chan);
+ auto dest_value = factory->dest(alu->def, 0, pin_chan);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 0);
EXPECT_EQ(dest_value->pin(), pin_chan);
auto sum = nir_fadd(&b, c1, c2);
auto alu = nir_instr_as_alu(sum->parent_instr);
- auto dest_value = factory->dest(alu->dest.dest.ssa, 1, pin_chan);
+ auto dest_value = factory->dest(alu->def, 1, pin_chan);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 1);
EXPECT_EQ(dest_value->pin(), pin_chan);
if (instr->type == nir_instr_type_alu) {
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.bit_size == 16 &&
- alu->dest.dest.ssa.num_components == 2)
+ if (alu->def.bit_size == 16 &&
+ alu->def.num_components == 2)
return false;
}
return 0;
nir_alu_instr *alu = nir_instr_as_alu(instr);
- if (alu->dest.dest.ssa.bit_size == 16) {
+ if (alu->def.bit_size == 16) {
switch (alu->op) {
case nir_op_unpack_32_2x16_split_x:
case nir_op_unpack_32_2x16_split_y:
switch (alu->op) {
case nir_op_imul_high:
case nir_op_umul_high:
- if (alu->dest.dest.ssa.bit_size < 32)
+ if (alu->def.bit_size < 32)
return 32;
break;
default:
struct qreg rep = ntq_get_src(c,
instr->src[0].src,
instr->src[0].swizzle[0]);
- ntq_store_def(c, &instr->dest.dest.ssa, 0, qir_PACK_8888_F(c, rep));
+ ntq_store_def(c, &instr->def, 0, qir_PACK_8888_F(c, rep));
return;
}
qir_PACK_8_F(c, result, src, i);
}
- ntq_store_def(c, &instr->dest.dest.ssa, 0, qir_MOV(c, result));
+ ntq_store_def(c, &instr->def, 0, qir_MOV(c, result));
}
/** Handles sign-extended bitfield extracts for 16 bits. */
srcs[i] = ntq_get_src(c, instr->src[i].src,
instr->src[i].swizzle[0]);
for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
- ntq_store_def(c, &instr->dest.dest.ssa, i,
+ ntq_store_def(c, &instr->def, i,
qir_MOV(c, srcs[i]));
return;
}
if (instr->op == nir_op_unpack_unorm_4x8) {
struct qreg src = ntq_get_src(c, instr->src[0].src,
instr->src[0].swizzle[0]);
- unsigned count = instr->dest.dest.ssa.num_components;
+ unsigned count = instr->def.num_components;
for (int i = 0; i < count; i++) {
- ntq_store_def(c, &instr->dest.dest.ssa, i,
+ ntq_store_def(c, &instr->def, i,
qir_UNPACK_8_F(c, src, i));
}
return;
abort();
}
- ntq_store_def(c, &instr->dest.dest.ssa, 0, result);
+ ntq_store_def(c, &instr->def, 0, result);
}
static void
}
/* ignore typeless ops */
if (alu_op_is_typeless(alu->op)) {
- atype = infer_nir_alu_type_from_uses_ssa(&alu->dest.dest.ssa);
+ atype = infer_nir_alu_type_from_uses_ssa(&alu->def);
break;
}
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
if (nir_op_infos[instr->op].input_sizes[src] > 0)
return nir_op_infos[instr->op].input_sizes[src];
- return instr->dest.dest.ssa.num_components;
+ return instr->def.num_components;
}
static SpvId
static void
store_alu_result(struct ntv_context *ctx, nir_alu_instr *alu, SpvId result, nir_alu_type atype)
{
- store_def(ctx, &alu->dest.dest.ssa, result, atype);
+ store_def(ctx, &alu->def, result, atype);
}
static SpvId
}
}
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
- unsigned num_components = alu->dest.dest.ssa.num_components;
+ unsigned bit_size = alu->def.bit_size;
+ unsigned num_components = alu->def.num_components;
nir_alu_type atype = bit_size == 1 ?
nir_type_bool :
(alu_op_is_typeless(alu->op) ? typeless_type : nir_op_infos[alu->op].output_type);
- SpvId dest_type = get_def_type(ctx, &alu->dest.dest.ssa, atype);
+ SpvId dest_type = get_def_type(ctx, &alu->def, atype);
if (needs_derivative_control(alu))
spirv_builder_emit_cap(&ctx->builder, SpvCapabilityDerivativeControl);
#define BUILTIN_UNOPF(nir_op, spirv_op) \
case nir_op: \
assert(nir_op_infos[alu->op].num_inputs == 1); \
- result = emit_builtin_unop(ctx, spirv_op, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_float), src[0]); \
+ result = emit_builtin_unop(ctx, spirv_op, get_def_type(ctx, &alu->def, nir_type_float), src[0]); \
atype = nir_type_float; \
break;
case nir_op_pack_half_2x16:
assert(nir_op_infos[alu->op].num_inputs == 1);
- result = emit_builtin_unop(ctx, GLSLstd450PackHalf2x16, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_uint), src[0]);
+ result = emit_builtin_unop(ctx, GLSLstd450PackHalf2x16, get_def_type(ctx, &alu->def, nir_type_uint), src[0]);
break;
case nir_op_unpack_64_2x32:
assert(nir_op_infos[alu->op].num_inputs == 1);
- result = emit_builtin_unop(ctx, GLSLstd450UnpackDouble2x32, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_uint), src[0]);
+ result = emit_builtin_unop(ctx, GLSLstd450UnpackDouble2x32, get_def_type(ctx, &alu->def, nir_type_uint), src[0]);
break;
BUILTIN_UNOPF(nir_op_unpack_half_2x16, GLSLstd450UnpackHalf2x16)
default:
unreachable("Impossible opcode");
}
- nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, dest);
+ nir_def_rewrite_uses(&alu_instr->def, dest);
nir_instr_remove(&alu_instr->instr);
return true;
}
default:
return false;
}
- unsigned num_components = alu->dest.dest.ssa.num_components;
+ unsigned num_components = alu->def.num_components;
if (num_components == 1)
return false;
b->cursor = nir_before_instr(in);
nir_channel(b, alu->src[2].src.ssa, alu->src[2].swizzle[i]));
}
nir_def *dest = nir_vec(b, dests, num_components);
- nir_def_rewrite_uses_after(&alu->dest.dest.ssa, dest, in);
+ nir_def_rewrite_uses_after(&alu->def, dest, in);
nir_instr_remove(in);
return true;
}
static rogue_ref
nir_ssa_reg_alu_dst(rogue_shader *shader, const nir_alu_instr *alu, bool vec)
{
- unsigned num_components = alu->dest.dest.ssa.num_components;
- unsigned index = alu->dest.dest.ssa.index;
+ unsigned num_components = alu->def.num_components;
+ unsigned index = alu->def.index;
assert(num_components == 1);
static void trans_nir_alu_vecN(rogue_builder *b, nir_alu_instr *alu, unsigned n)
{
- unsigned dst_index = alu->dest.dest.ssa.index;
+ unsigned dst_index = alu->def.index;
rogue_regarray *dst;
rogue_reg *src;
static void trans_nir_alu_iadd64(rogue_builder *b, nir_alu_instr *alu)
{
- unsigned dst_index = alu->dest.dest.ssa.index;
+ unsigned dst_index = alu->def.index;
rogue_regarray *dst[2] = {
rogue_ssa_vec_regarray(b->shader, 1, dst_index, 0),
rogue_ssa_vec_regarray(b->shader, 1, dst_index, 1),
static void trans_nir_alu_iadd(rogue_builder *b, nir_alu_instr *alu)
{
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned bit_size = alu->def.bit_size;
switch (bit_size) {
/* TODO: case 32: */
bool need_dest)
{
fs_reg result =
- need_dest ? get_nir_def(instr->dest.dest.ssa) : bld.null_reg_ud();
+ need_dest ? get_nir_def(instr->def) : bld.null_reg_ud();
result.type = brw_type_for_nir_type(devinfo,
(nir_alu_type)(nir_op_infos[instr->op].output_type |
- instr->dest.dest.ssa.bit_size));
+ instr->def.bit_size));
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
op[i] = get_nir_src(instr->src[i].src);
/* Since NIR is doing the scalarizing for us, we should only ever see
* vectorized operations with a single channel.
*/
- nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa);
+ nir_component_mask_t write_mask = get_nir_write_mask(instr->def);
assert(util_bitcount(write_mask) == 1);
channel = ffs(write_mask) - 1;
* The source restriction is just because I was lazy about generating the
* constant below.
*/
- if (instr->dest.dest.ssa.bit_size != 32 ||
+ if (instr->def.bit_size != 32 ||
nir_src_bit_size(inot_instr->src[0].src) != 32)
return false;
/* Since NIR is doing the scalarizing for us, we should only ever see
* vectorized operations with a single channel.
*/
- nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa);
+ nir_component_mask_t write_mask = get_nir_write_mask(instr->def);
assert(util_bitcount(write_mask) == 1);
channel = ffs(write_mask) - 1;
}
bool need_extra_copy = false;
nir_intrinsic_instr *store_reg =
- nir_store_reg_for_def(&instr->dest.dest.ssa);
+ nir_store_reg_for_def(&instr->def);
if (store_reg != NULL) {
nir_def *dest_reg = store_reg->src[1].ssa;
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
}
}
- nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa);
+ nir_component_mask_t write_mask = get_nir_write_mask(instr->def);
unsigned last_bit = util_last_bit(write_mask);
for (unsigned i = 0; i < last_bit; i++) {
case nir_op_irhadd:
case nir_op_urhadd:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
inst = bld.AVG(result, op[0], op[1]);
break;
case nir_op_ihadd:
case nir_op_uhadd: {
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
fs_reg tmp = bld.vgrf(result.type);
if (devinfo->ver >= 8) {
const enum brw_reg_type dword_type =
ud ? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D;
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
/* Before copy propagation there are no immediate values. */
assert(op[0].file != IMM && op[1].file != IMM);
}
case nir_op_imul:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
bld.MUL(result, op[0], op[1]);
break;
case nir_op_imul_high:
case nir_op_umul_high:
- assert(instr->dest.dest.ssa.bit_size < 64);
- if (instr->dest.dest.ssa.bit_size == 32) {
+ assert(instr->def.bit_size < 64);
+ if (instr->def.bit_size == 32) {
bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]);
} else {
fs_reg tmp = bld.vgrf(brw_reg_type_from_bit_size(32, op[0].type));
case nir_op_idiv:
case nir_op_udiv:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
* appears that our hardware just does the right thing for signed
* remainder.
*/
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
break;
result.type =
brw_type_for_nir_type(devinfo,
(nir_alu_type)(nir_type_int |
- instr->dest.dest.ssa.bit_size));
+ instr->def.bit_size));
op[0].type =
brw_type_for_nir_type(devinfo,
(nir_alu_type)(nir_type_int |
break;
case nir_op_bitfield_reverse:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
bld.BFREV(result, op[0]);
break;
case nir_op_bit_count:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) < 64);
bld.CBIT(result, op[0]);
break;
case nir_op_uclz:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
bld.LZD(retype(result, BRW_REGISTER_TYPE_UD), op[0]);
break;
case nir_op_ifind_msb: {
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
assert(devinfo->ver >= 7);
}
case nir_op_find_lsb:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
assert(devinfo->ver >= 7);
bld.FBL(result, op[0]);
unreachable("should have been lowered");
case nir_op_ubfe:
case nir_op_ibfe:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
bld.BFE(result, op[2], op[1], op[0]);
break;
case nir_op_bfm:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
bld.BFI1(result, op[0], op[1]);
break;
case nir_op_bfi:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
/* bfi is ((...) | (~src0 & src2)). The second part is zero when src2 is
* either 0 or src0. Replacing the 0 with another value can eliminate a
* There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
* Use two instructions and a word or DWord intermediate integer type.
*/
- if (instr->dest.dest.ssa.bit_size == 64) {
+ if (instr->def.bit_size == 64) {
const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8);
if (instr->op == nir_op_extract_i8) {
break;
}
- if (alu->dest.dest.ssa.bit_size >= 32)
+ if (alu->def.bit_size >= 32)
return 0;
/* Note: nir_op_iabs and nir_op_ineg are not lowered here because the
return 0;
default:
if (nir_op_infos[alu->op].num_inputs >= 2 &&
- alu->dest.dest.ssa.bit_size == 8)
+ alu->def.bit_size == 8)
return 16;
if (nir_alu_instr_is_comparison(alu) &&
nir_def *src = nir_ssa_for_alu_src(b, alu, 0);
nir_def *tmp = nir_type_convert(b, src, src_type, tmp_type, nir_rounding_mode_undef);
nir_def *res = nir_type_convert(b, tmp, tmp_type, dst_type, rnd);
- nir_def_rewrite_uses(&alu->dest.dest.ssa, res);
+ nir_def_rewrite_uses(&alu->def, res);
nir_instr_remove(&alu->instr);
}
nir_alu_type src_type = nir_op_infos[alu->op].input_types[0];
nir_alu_type src_full_type = (nir_alu_type) (src_type | src_bit_size);
- unsigned dst_bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bit_size = alu->def.bit_size;
nir_alu_type dst_full_type = nir_op_infos[alu->op].output_type;
nir_alu_type dst_type = nir_alu_type_get_base_type(dst_full_type);
case nir_op_mov:
case nir_op_fneg:
case nir_op_fabs:
- if (!are_all_uses_fadd(&use_alu->dest.dest.ssa))
+ if (!are_all_uses_fadd(&use_alu->def))
return false;
break;
switch (alu->op) {
case nir_op_mov:
- alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components,
+ alu = get_mul_for_src(&alu->src[0], alu->def.num_components,
swizzle, negate, abs);
break;
case nir_op_fneg:
- alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components,
+ alu = get_mul_for_src(&alu->src[0], alu->def.num_components,
swizzle, negate, abs);
*negate = !*negate;
break;
case nir_op_fabs:
- alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components,
+ alu = get_mul_for_src(&alu->src[0], alu->def.num_components,
swizzle, negate, abs);
*negate = false;
*abs = true;
* operations. This prevents us from being too aggressive with our
* fusing which can actually lead to more instructions.
*/
- if (!are_all_uses_fadd(&alu->dest.dest.ssa))
+ if (!are_all_uses_fadd(&alu->def))
return NULL;
break;
abs = false;
mul = get_mul_for_src(&add->src[add_mul_src],
- add->dest.dest.ssa.num_components,
+ add->def.num_components,
swizzle, &negate, &abs);
if (mul != NULL)
if (mul == NULL)
return false;
- unsigned bit_size = add->dest.dest.ssa.bit_size;
+ unsigned bit_size = add->def.bit_size;
nir_def *mul_src[2];
mul_src[0] = mul->src[0].src.ssa;
for (unsigned i = 0; i < 2; i++) {
ffma->src[i].src = nir_src_for_ssa(mul_src[i]);
- for (unsigned j = 0; j < add->dest.dest.ssa.num_components; j++)
+ for (unsigned j = 0; j < add->def.num_components; j++)
ffma->src[i].swizzle[j] = mul->src[i].swizzle[swizzle[j]];
}
nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src], ffma);
- nir_def_init(&ffma->instr, &ffma->dest.dest.ssa,
- add->dest.dest.ssa.num_components, bit_size);
- nir_def_rewrite_uses(&add->dest.dest.ssa, &ffma->dest.dest.ssa);
+ nir_def_init(&ffma->instr, &ffma->def,
+ add->def.num_components, bit_size);
+ nir_def_rewrite_uses(&add->def, &ffma->def);
nir_builder_instr_insert(b, &ffma->instr);
- assert(list_is_empty(&add->dest.dest.ssa.uses));
+ assert(list_is_empty(&add->def.uses));
nir_instr_remove(&add->instr);
return true;
nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16);
nir_alu_src_copy(&imul_32x16->src[1], &imul->src[small_val], imul_32x16);
- nir_def_init(&imul_32x16->instr, &imul_32x16->dest.dest.ssa,
- imul->dest.dest.ssa.num_components, 32);
+ nir_def_init(&imul_32x16->instr, &imul_32x16->def,
+ imul->def.num_components, 32);
- nir_def_rewrite_uses(&imul->dest.dest.ssa,
- &imul_32x16->dest.dest.ssa);
+ nir_def_rewrite_uses(&imul->def,
+ &imul_32x16->def);
nir_builder_instr_insert(b, &imul_32x16->instr);
if (imul->op != nir_op_imul)
return false;
- if (imul->dest.dest.ssa.bit_size != 32)
+ if (imul->def.bit_size != 32)
return false;
nir_op new_opcode = nir_num_opcodes;
int64_t lo = INT64_MAX;
int64_t hi = INT64_MIN;
- for (unsigned comp = 0; comp < imul->dest.dest.ssa.num_components; comp++) {
+ for (unsigned comp = 0; comp < imul->def.num_components; comp++) {
int64_t v = nir_src_comp_as_int(imul->src[i].src, comp);
if (v < lo)
return true;
}
- if (imul->dest.dest.ssa.num_components > 1)
+ if (imul->def.num_components > 1)
return false;
- const nir_scalar imul_scalar = { &imul->dest.dest.ssa, 0 };
+ const nir_scalar imul_scalar = { &imul->def, 0 };
int idx = -1;
enum root_operation prev_root = invalid_root;
vec4_instruction *inst;
nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type |
- instr->dest.dest.ssa.bit_size);
- dst_reg dst = get_nir_def(instr->dest.dest.ssa, dst_type);
- dst.writemask &= nir_component_mask(instr->dest.dest.ssa.num_components);
+ instr->def.bit_size);
+ dst_reg dst = get_nir_def(instr->def, dst_type);
+ dst.writemask &= nir_component_mask(instr->def.num_components);
src_reg op[4];
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
break;
case nir_op_iadd:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_fadd:
try_immediate_source(instr, op, true);
break;
case nir_op_uadd_sat:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
inst = emit(ADD(dst, op[0], op[1]));
inst->saturate = true;
break;
break;
case nir_op_imul: {
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
/* For integer multiplication, the MUL uses the low 16 bits of one of
* the operands (src0 through SNB, src1 on IVB and later). The MACH
case nir_op_imul_high:
case nir_op_umul_high: {
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
emit(MUL(acc, op[0], op[1]));
case nir_op_idiv:
case nir_op_udiv:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]);
break;
* appears that our hardware just does the right thing for signed
* remainder.
*/
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]);
break;
break;
case nir_op_uadd_carry: {
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
emit(ADDC(dst_null_ud(), op[0], op[1]));
}
case nir_op_usub_borrow: {
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
emit(SUBB(dst_null_ud(), op[0], op[1]));
case nir_op_imin:
case nir_op_umin:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_fmin:
try_immediate_source(instr, op, true);
case nir_op_imax:
case nir_op_umax:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_fmax:
try_immediate_source(instr, op, true);
case nir_op_uge32:
case nir_op_ieq32:
case nir_op_ine32:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_flt32:
case nir_op_fge32:
case nir_op_b32all_iequal2:
case nir_op_b32all_iequal3:
case nir_op_b32all_iequal4:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_b32all_fequal2:
case nir_op_b32all_fequal3:
case nir_op_b32any_inequal2:
case nir_op_b32any_inequal3:
case nir_op_b32any_inequal4:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
FALLTHROUGH;
case nir_op_b32any_fnequal2:
case nir_op_b32any_fnequal3:
}
case nir_op_inot:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit(NOT(dst, op[0]));
break;
case nir_op_ixor:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, true);
emit(XOR(dst, op[0], op[1]));
break;
case nir_op_ior:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, true);
emit(OR(dst, op[0], op[1]));
break;
case nir_op_iand:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, true);
emit(AND(dst, op[0], op[1]));
break;
case nir_op_b2i32:
case nir_op_b2f32:
case nir_op_b2f64:
- if (instr->dest.dest.ssa.bit_size > 32) {
+ if (instr->def.bit_size > 32) {
assert(dst.type == BRW_REGISTER_TYPE_DF);
emit_conversion_to_double(dst, negate(op[0]));
} else {
break;
case nir_op_unpack_unorm_4x8:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_unpack_unorm_4x8(dst, op[0]);
break;
case nir_op_pack_unorm_4x8:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_pack_unorm_4x8(dst, op[0]);
break;
case nir_op_unpack_snorm_4x8:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_unpack_snorm_4x8(dst, op[0]);
break;
case nir_op_pack_snorm_4x8:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit_pack_snorm_4x8(dst, op[0]);
break;
case nir_op_bitfield_reverse:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
emit(BFREV(dst, op[0]));
break;
case nir_op_bit_count:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) < 64);
emit(CBIT(dst, op[0]));
break;
case nir_op_ifind_msb: {
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
assert(devinfo->ver >= 7);
}
case nir_op_uclz:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
emit(LZD(dst, op[0]));
break;
case nir_op_find_lsb:
- assert(instr->dest.dest.ssa.bit_size == 32);
+ assert(instr->def.bit_size == 32);
assert(nir_src_bit_size(instr->src[0].src) == 32);
assert(devinfo->ver >= 7);
emit(FBL(dst, op[0]));
unreachable("should have been lowered");
case nir_op_ubfe:
case nir_op_ibfe:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
break;
case nir_op_bfm:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
emit(BFI1(dst, op[0], op[1]));
break;
case nir_op_bfi:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
break;
case nir_op_ishl:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, false);
emit(SHL(dst, op[0], op[1]));
break;
case nir_op_ishr:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, false);
emit(ASR(dst, op[0], op[1]));
break;
case nir_op_ushr:
- assert(instr->dest.dest.ssa.bit_size < 64);
+ assert(instr->def.bit_size < 64);
try_immediate_source(instr, op, false);
emit(SHR(dst, op[0], op[1]));
break;
} else {
assert(swizzle != SWIZZLE_NIL);
nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
- nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, 32);
+ nir_def_init(&mov->instr, &mov->def, 1, 32);
mov->src[0] = src;
mov->src[0].swizzle[0] = swizzle;
nir_builder_instr_insert(b, &mov->instr);
- chans[i] = &mov->dest.dest.ssa;
+ chans[i] = &mov->def;
}
if (prog_src->Negate & (1 << i))
const nir_op_info *info = &nir_op_infos[alu->op];
if (info->output_type & nir_type_float &&
- alu->dest.dest.ssa.bit_size == 64)
+ alu->def.bit_size == 64)
return true;
}
}
alu->src[i].src.ssa->bit_size == 64) {
unsigned num_components = nir_op_infos[alu->op].input_sizes[i];
if (!num_components)
- num_components = alu->dest.dest.ssa.num_components;
+ num_components = alu->def.num_components;
nir_def *components[NIR_MAX_VEC_COMPONENTS];
for (unsigned c = 0; c < num_components; ++c) {
nir_def *packed_double = nir_channel(b, alu->src[i].src.ssa, alu->src[i].swizzle[c]);
}
if (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) == nir_type_float &&
- alu->dest.dest.ssa.bit_size == 64) {
+ alu->def.bit_size == 64) {
b->cursor = nir_after_instr(&alu->instr);
nir_def *components[NIR_MAX_VEC_COMPONENTS];
- for (unsigned c = 0; c < alu->dest.dest.ssa.num_components; ++c) {
- nir_def *packed_double = nir_channel(b, &alu->dest.dest.ssa, c);
+ for (unsigned c = 0; c < alu->def.num_components; ++c) {
+ nir_def *packed_double = nir_channel(b, &alu->def, c);
nir_def *unpacked_double = nir_unpack_double_2x32_dxil(b, packed_double);
components[c] = nir_pack_64_2x32(b, unpacked_double);
}
- nir_def *repacked_dvec = nir_vec(b, components, alu->dest.dest.ssa.num_components);
- nir_def_rewrite_uses_after(&alu->dest.dest.ssa, repacked_dvec, repacked_dvec->parent_instr);
+ nir_def *repacked_dvec = nir_vec(b, components, alu->def.num_components);
+ nir_def_rewrite_uses_after(&alu->def, repacked_dvec, repacked_dvec->parent_instr);
progress = true;
}
store_alu_dest(struct ntd_context *ctx, nir_alu_instr *alu, unsigned chan,
const struct dxil_value *value)
{
- store_def(ctx, &alu->dest.dest.ssa, chan, value);
+ store_def(ctx, &alu->def, chan, value);
}
static const struct dxil_value *
0);
} else {
uint64_t val = nir_scalar_as_uint(
- nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->dest.dest.ssa, 0), 1));
+ nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->def, 0), 1));
op1 = dxil_module_get_int_const(&ctx->mod, val & shift_mask, op0_bit_size);
}
static enum dxil_cast_opcode
get_cast_op(nir_alu_instr *alu)
{
- unsigned dst_bits = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bits = alu->def.bit_size;
unsigned src_bits = nir_src_bit_size(alu->src[0].src);
switch (alu->op) {
static const struct dxil_type *
get_cast_dest_type(struct ntd_context *ctx, nir_alu_instr *alu)
{
- unsigned dst_bits = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bits = alu->def.bit_size;
switch (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type)) {
case nir_type_bool:
assert(dst_bits == 1);
switch (opcode) {
case DXIL_CAST_UITOFP:
case DXIL_CAST_SITOFP:
- if (is_double(info->output_type, alu->dest.dest.ssa.bit_size))
+ if (is_double(info->output_type, alu->def.bit_size))
ctx->mod.feats.dx11_1_double_extensions = true;
break;
case DXIL_CAST_FPTOUI:
break;
}
- if (alu->dest.dest.ssa.bit_size == 16) {
+ if (alu->def.bit_size == 16) {
switch (alu->op) {
case nir_op_f2fmp:
case nir_op_i2imp:
const nir_op_info *info = &nir_op_infos[alu->op];
assert(info->output_type == info->input_types[0]);
assert(info->output_type == info->input_types[1]);
- unsigned dst_bits = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bits = alu->def.bit_size;
assert(nir_src_bit_size(alu->src[0].src) == dst_bits);
assert(nir_src_bit_size(alu->src[1].src) == dst_bits);
enum overload_type overload = get_overload(info->output_type, dst_bits);
const struct dxil_value *op2)
{
const nir_op_info *info = &nir_op_infos[alu->op];
- unsigned dst_bits = alu->dest.dest.ssa.bit_size;
+ unsigned dst_bits = alu->def.bit_size;
assert(nir_src_bit_size(alu->src[0].src) == dst_bits);
assert(nir_src_bit_size(alu->src[1].src) == dst_bits);
assert(nir_src_bit_size(alu->src[2].src) == dst_bits);
const struct dxil_value *v = dxil_emit_call(&ctx->mod, func, args, ARRAY_SIZE(args));
if (!v)
return false;
- store_def(ctx, &alu->dest.dest.ssa, 0, v);
+ store_def(ctx, &alu->def, 0, v);
return true;
}
if (!hi || !lo)
return false;
- store_def(ctx, &alu->dest.dest.ssa, 0, hi);
- store_def(ctx, &alu->dest.dest.ssa, 1, lo);
+ store_def(ctx, &alu->def, 0, hi);
+ store_def(ctx, &alu->def, 1, lo);
return true;
}
case nir_op_vec16:
return emit_vec(ctx, alu, nir_op_infos[alu->op].num_inputs);
case nir_op_mov: {
- assert(alu->dest.dest.ssa.num_components == 1);
- store_ssa_def(ctx, &alu->dest.dest.ssa, 0, get_src_ssa(ctx,
+ assert(alu->def.num_components == 1);
+ store_ssa_def(ctx, &alu->def, 0, get_src_ssa(ctx,
alu->src->src.ssa, alu->src->swizzle[0]));
return true;
}
case nir_op_fmul: return emit_binop(ctx, alu, DXIL_BINOP_MUL, src[0], src[1]);
case nir_op_fdiv:
- if (alu->dest.dest.ssa.bit_size == 64)
+ if (alu->def.bit_size == 64)
ctx->mod.feats.dx11_1_double_extensions = 1;
return emit_binop(ctx, alu, DXIL_BINOP_SDIV, src[0], src[1]);
case nir_op_udiv:
if (nir_src_is_const(alu->src[1].src)) {
/* It's illegal to emit a literal divide by 0 in DXIL */
- nir_scalar divisor = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->dest.dest.ssa, 0), 1);
+ nir_scalar divisor = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->def, 0), 1);
if (nir_scalar_as_int(divisor) == 0) {
store_alu_dest(ctx, alu, 0,
- dxil_module_get_int_const(&ctx->mod, 0, alu->dest.dest.ssa.bit_size));
+ dxil_module_get_int_const(&ctx->mod, 0, alu->def.bit_size));
return true;
}
}
case nir_op_ior: return emit_binop(ctx, alu, DXIL_BINOP_OR, src[0], src[1]);
case nir_op_ixor: return emit_binop(ctx, alu, DXIL_BINOP_XOR, src[0], src[1]);
case nir_op_inot: {
- unsigned bit_size = alu->dest.dest.ssa.bit_size;
+ unsigned bit_size = alu->def.bit_size;
intmax_t val = bit_size == 1 ? 1 : -1;
const struct dxil_value *negative_one = dxil_module_get_int_const(&ctx->mod, val, bit_size);
return emit_binop(ctx, alu, DXIL_BINOP_XOR, src[0], negative_one);
case nir_op_fround_even: return emit_unary_intin(ctx, alu, DXIL_INTR_ROUND_NE, src[0]);
case nir_op_frcp: {
const struct dxil_value *one;
- switch (alu->dest.dest.ssa.bit_size) {
+ switch (alu->def.bit_size) {
case 16:
one = dxil_module_get_float16_const(&ctx->mod, 0x3C00);
break;
case nir_op_fmax: return emit_binary_intin(ctx, alu, DXIL_INTR_FMAX, src[0], src[1]);
case nir_op_fmin: return emit_binary_intin(ctx, alu, DXIL_INTR_FMIN, src[0], src[1]);
case nir_op_ffma:
- if (alu->dest.dest.ssa.bit_size == 64)
+ if (alu->def.bit_size == 64)
ctx->mod.feats.dx11_1_double_extensions = 1;
return emit_tertiary_intin(ctx, alu, DXIL_INTR_FMA, src[0], src[1], src[2]);
DataType
Converter::getDType(nir_alu_instr *insn)
{
- return getDType(insn->op, insn->dest.dest.ssa.bit_size);
+ return getDType(insn->op, insn->def.bit_size);
}
DataType
}
#define DEFAULT_CHECKS \
- if (insn->dest.dest.ssa.num_components > 1) { \
+ if (insn->def.num_components > 1) { \
ERROR("nir_alu_instr only supported with 1 component!\n"); \
return false; \
}
case nir_op_ishl:
case nir_op_ixor: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
operation preOp = preOperationNeeded(op);
if (preOp != OP_NOP) {
assert(info.num_inputs < 2);
case nir_op_ifind_msb:
case nir_op_ufind_msb: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
dType = sTypes[0];
mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
break;
}
case nir_op_fround_even: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkCvt(OP_CVT, dType, newDefs[0], dType, getSrc(&insn->src[0]))->rnd = ROUND_NI;
break;
}
case nir_op_u2f64:
case nir_op_u2u64: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
DataType stype = sTypes[0];
Instruction *i = mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0]));
if (::isFloatType(stype) && isIntType(dType))
case nir_op_fneu32:
case nir_op_ine32: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Instruction *i = mkCmp(getOperation(op),
getCondCode(op),
dType,
break;
}
case nir_op_mov: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
mkMov(newDefs[c], getSrc(&insn->src[0], c), dType);
}
case nir_op_vec4:
case nir_op_vec8:
case nir_op_vec16: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
for (LValues::size_type c = 0u; c < newDefs.size(); ++c) {
mkMov(newDefs[c], getSrc(&insn->src[c]), dType);
}
}
// (un)pack
case nir_op_pack_64_2x32: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]);
merge->setSrc(0, getSrc(&insn->src[0], 0));
merge->setSrc(1, getSrc(&insn->src[0], 1));
break;
}
case nir_op_pack_half_2x16_split: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *tmpH = getSSA();
Value *tmpL = getSSA();
}
case nir_op_unpack_half_2x16_split_x:
case nir_op_unpack_half_2x16_split_y: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Instruction *cvt = mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, getSrc(&insn->src[0]));
if (op == nir_op_unpack_half_2x16_split_y)
cvt->subOp = 1;
break;
}
case nir_op_unpack_64_2x32: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, newDefs[1]);
break;
}
case nir_op_unpack_64_2x32_split_x: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, getSSA());
break;
}
case nir_op_unpack_64_2x32_split_y: {
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp1(OP_SPLIT, dType, getSSA(), getSrc(&insn->src[0]))->setDef(1, newDefs[0]);
break;
}
else
iType = TYPE_S32;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
LValue *val0 = getScratch();
LValue *val1 = getScratch();
mkCmp(OP_SET, CC_GT, iType, val0, dType, getSrc(&insn->src[0]), zero);
case nir_op_fcsel:
case nir_op_b32csel: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkCmp(OP_SLCT, CC_NE, dType, newDefs[0], sTypes[0], getSrc(&insn->src[1]), getSrc(&insn->src[2]), getSrc(&insn->src[0]));
break;
}
case nir_op_ubitfield_extract: {
DEFAULT_CHECKS;
Value *tmp = getSSA();
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
mkOp2(OP_EXTBF, dType, newDefs[0], getSrc(&insn->src[0]), tmp);
break;
}
case nir_op_bfm: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp2(OP_BMSK, dType, newDefs[0], getSrc(&insn->src[1]), getSrc(&insn->src[0]))->subOp = NV50_IR_SUBOP_BMSK_W;
break;
}
case nir_op_bitfield_insert: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
LValue *temp = getSSA();
mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
}
case nir_op_bit_count: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp2(OP_POPCNT, dType, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[0]));
break;
}
case nir_op_bitfield_reverse: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp1(OP_BREV, TYPE_U32, newDefs[0], getSrc(&insn->src[0]));
break;
}
case nir_op_find_lsb: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *tmp = getSSA();
mkOp1(OP_BREV, TYPE_U32, tmp, getSrc(&insn->src[0]));
mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT;
}
case nir_op_extract_u8: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *prmt = getSSA();
mkOp2(OP_OR, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x4440));
mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
}
case nir_op_extract_i8: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *prmt = getSSA();
mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x1111), loadImm(NULL, 0x8880));
mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
}
case nir_op_extract_u16: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *prmt = getSSA();
mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x22), loadImm(NULL, 0x4410));
mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
}
case nir_op_extract_i16: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *prmt = getSSA();
mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x2222), loadImm(NULL, 0x9910));
mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
}
case nir_op_fquantize2f16: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *tmp = getSSA();
mkCvt(OP_CVT, TYPE_F16, tmp, TYPE_F32, getSrc(&insn->src[0]))->ftz = 1;
mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, tmp);
}
case nir_op_urol: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]),
getSrc(&insn->src[1]), getSrc(&insn->src[0]))
->subOp = NV50_IR_SUBOP_SHF_L |
}
case nir_op_uror: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]),
getSrc(&insn->src[1]), getSrc(&insn->src[0]))
->subOp = NV50_IR_SUBOP_SHF_R |
// boolean conversions
case nir_op_b2f32: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1.0f));
break;
}
case nir_op_b2f64: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
Value *tmp = getSSA(4);
mkOp2(OP_AND, TYPE_U32, tmp, getSrc(&insn->src[0]), loadImm(NULL, 0x3ff00000));
mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp);
case nir_op_b2i16:
case nir_op_b2i32: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1));
break;
}
case nir_op_b2i64: {
DEFAULT_CHECKS;
- LValues &newDefs = convert(&insn->dest.dest.ssa);
+ LValues &newDefs = convert(&insn->def);
LValue *def = getScratch();
mkOp2(OP_AND, TYPE_U32, def, getSrc(&insn->src[0]), loadImm(NULL, 1));
mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0));
static void
bi_emit_alu(bi_builder *b, nir_alu_instr *instr)
{
- bi_index dst = bi_def_index(&instr->dest.dest.ssa);
+ bi_index dst = bi_def_index(&instr->def);
unsigned srcs = nir_op_infos[instr->op].num_inputs;
- unsigned sz = instr->dest.dest.ssa.bit_size;
- unsigned comps = instr->dest.dest.ssa.num_components;
+ unsigned sz = instr->def.bit_size;
+ unsigned comps = instr->def.num_components;
unsigned src_sz = srcs > 0 ? nir_src_bit_size(instr->src[0].src) : 0;
/* Indicate scalarness */
}
/* Vectorized instructions cannot write more than 32-bit */
- int dst_bit_size = alu->dest.dest.ssa.bit_size;
+ int dst_bit_size = alu->def.bit_size;
if (dst_bit_size == 16)
return 2;
else
if (nir_src_bit_size(alu->src[0].src) == 64)
return true;
- if (alu->dest.dest.ssa.bit_size == 64)
+ if (alu->def.bit_size == 64)
return true;
switch (alu->op) {
const nir_alu_instr *alu = nir_instr_as_alu(instr);
int src_bit_size = nir_src_bit_size(alu->src[0].src);
- int dst_bit_size = alu->dest.dest.ssa.bit_size;
+ int dst_bit_size = alu->def.bit_size;
if (src_bit_size == 64 || dst_bit_size == 64)
return 2;
return;
}
- unsigned nr_components = instr->dest.dest.ssa.num_components;
+ unsigned nr_components = instr->def.num_components;
unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
unsigned op = 0;
bool flip_src12 = false;
ASSERTED unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
- unsigned dst_bitsize = instr->dest.dest.ssa.bit_size;
+ unsigned dst_bitsize = instr->def.bit_size;
enum midgard_roundmode roundmode = MIDGARD_RTE;
.roundmode = roundmode,
};
- ins.dest = nir_def_index_with_mask(&instr->dest.dest.ssa, &ins.mask);
+ ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask);
for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
ins.src[i] = ~0;
},
};
- ins.dest = nir_def_index_with_mask(&instr->dest.dest.ssa, &ins.mask);
+ ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask);
emit_mir_instruction(ctx, ins);
}
return false;
BITSET_WORD *float_types = data;
- if (BITSET_TEST(float_types, alu->dest.dest.ssa.index)) {
+ if (BITSET_TEST(float_types, alu->def.index)) {
alu->op = nir_op_b32fcsel_mdg;
return true;
} else {
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