amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
- start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL);
- max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
+ if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) {
+ start = dev->dev_info.high_va_offset;
+ max = dev->dev_info.high_va_max;
+ } else {
+ start = MAX2(dev->dev_info.virtual_address_offset, 0x100000000ULL);
+ max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
+ }
amdgpu_vamgr_init(&dev->vamgr, start, max,
dev->dev_info.virtual_address_alignment);
__u32 _pad1;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
+ /** Starting high virtual address for UMDs. */
+ __u64 high_va_offset;
+ /** The maximum high virtual address */
+ __u64 high_va_max;
};
struct drm_amdgpu_info_hw_ip {