hdmitx: optimise the mode setting sequence [2/2]

PD#SWPL-10600

Problem:
When hdmitx output deep color modes (30 or 36 bits), the Hactive
may set wrong values, offset +1.

Solution:
Optimise the mode setting sequence: disable VENC, PHY configure,
core configure / reset, enable VENC

Verify:
G12B/W400

Change-Id: Id19b4441ccee3a7d3d81c3d55dbd9102762fe992
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
index 9df42c2..176db3e 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/enc_cfg_hw.c
@@ -61,8 +61,8 @@ static const struct reg_s tvregs_720p[] = {
        {P_ENCP_VIDEO_VSPULS_ELINE, 8},
        {P_ENCP_VIDEO_HAVON_BEGIN, 260},
        {P_ENCP_VIDEO_HAVON_END, 1539},
-       {P_ENCP_VIDEO_VAVON_BLINE, 15},
-       {P_ENCP_VIDEO_VAVON_ELINE, 744},
+       {P_ENCP_VIDEO_VAVON_BLINE, 29},
+       {P_ENCP_VIDEO_VAVON_ELINE, 749},
        {P_ENCP_VIDEO_HSO_BEGIN, 0},
        {P_ENCP_VIDEO_HSO_END, 168},
        {P_ENCP_VIDEO_VSO_BEGIN, 168},
@@ -70,7 +70,6 @@ static const struct reg_s tvregs_720p[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0},
        {P_ENCP_VIDEO_VSO_ELINE, 5},
        {P_ENCP_VIDEO_MAX_LNCNT, 749},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -105,7 +104,6 @@ static const struct reg_s tvregs_720p_50hz[] = {
        {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x407},
        {P_ENCP_VIDEO_YC_DLY, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -136,7 +134,6 @@ static const struct reg_s tvregs_480i[] = {
        {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
        {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
        {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
-       {P_ENCP_VIDEO_EN, 0},
        {P_ENCI_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
@@ -176,7 +173,6 @@ static const struct reg_s tvregs_480p[] = {
        {P_ENCP_DACSEL_0, 0x3102},
        {P_ENCP_DACSEL_1, 0x0054},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -211,7 +207,6 @@ static const struct reg_s tvregs_576i[] = {
        {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
        {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
        {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
-       {P_ENCP_VIDEO_EN, 0},
        {P_ENCI_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
@@ -249,7 +244,6 @@ static const struct reg_s tvregs_576p[] = {
        {P_ENCP_VIDEO_SY_VAL, 8},
        {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -288,7 +282,6 @@ static const struct reg_s tvregs_1080i[] = {
        {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x207},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -323,7 +316,6 @@ static const struct reg_s tvregs_1080i_50hz[] = {
        {P_ENCP_VIDEO_MODE_ADV, 0x0018},
        {P_ENCP_VIDEO_SYNC_MODE, 0x7},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -346,42 +338,8 @@ static const struct reg_s tvregs_1080p[] = {
        {P_ENCP_VIDEO_VSPULS_ELINE, 4},
        {P_ENCP_VIDEO_HAVON_BEGIN, 148},
        {P_ENCP_VIDEO_HAVON_END, 2067},
-       {P_ENCP_VIDEO_VAVON_BLINE, 41},
-       {P_ENCP_VIDEO_VAVON_ELINE, 1120},
-       {P_ENCP_VIDEO_HSO_BEGIN, 44},
-       {P_ENCP_VIDEO_HSO_END, 2156},
-       {P_ENCP_VIDEO_VSO_BEGIN, 2100},
-       {P_ENCP_VIDEO_VSO_END, 2164},
-       {P_ENCP_VIDEO_VSO_BLINE, 0},
-       {P_ENCP_VIDEO_VSO_ELINE, 5},
-       {P_ENCP_VIDEO_MAX_LNCNT, 1124},
-       {P_VENC_VIDEO_PROG_MODE, 0x100},
-       {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
-       {MREG_END_MARKER, 0},
-};
-
-static const struct reg_s tvregs_1080p_30hz[] = {
-       {P_ENCP_VIDEO_EN, 0},
-       {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_FILT_CTRL, 0x1052},
-       {P_VENC_DVI_SETTING, 0x0001},
-       {P_ENCP_VIDEO_MODE, 0x4040},
-       {P_ENCP_VIDEO_MODE_ADV, 0x0018},
-       {P_ENCP_VIDEO_YFP1_HTIME, 140},
-       {P_ENCP_VIDEO_YFP2_HTIME, 2060},
-       {P_ENCP_VIDEO_MAX_PXCNT, 2199},
-       {P_ENCP_VIDEO_HSPULS_BEGIN, 2156},
-       {P_ENCP_VIDEO_HSPULS_END, 44},
-       {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
-       {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
-       {P_ENCP_VIDEO_VSPULS_END, 2059},
-       {P_ENCP_VIDEO_VSPULS_BLINE, 0},
-       {P_ENCP_VIDEO_VSPULS_ELINE, 4},
-       {P_ENCP_VIDEO_HAVON_BEGIN, 148},
-       {P_ENCP_VIDEO_HAVON_END, 2067},
-       {P_ENCP_VIDEO_VAVON_BLINE, 41},
-       {P_ENCP_VIDEO_VAVON_ELINE, 1120},
+       {P_ENCP_VIDEO_VAVON_BLINE, 42},
+       {P_ENCP_VIDEO_VAVON_ELINE, 1121},
        {P_ENCP_VIDEO_HSO_BEGIN, 44},
        {P_ENCP_VIDEO_HSO_END, 2156},
        {P_ENCP_VIDEO_VSO_BEGIN, 2100},
@@ -391,7 +349,6 @@ static const struct reg_s tvregs_1080p_30hz[] = {
        {P_ENCP_VIDEO_MAX_LNCNT, 1124},
        {P_VENC_VIDEO_PROG_MODE, 0x100},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -429,7 +386,6 @@ static const struct reg_s tvregs_1080p_50hz[] = {
        {P_ENCP_VIDEO_YC_DLY, 0},
        {P_ENCP_VIDEO_RGB_CTRL, 2},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -468,7 +424,6 @@ static const struct reg_s tvregs_1080p_24hz[] = {
        {P_ENCP_VIDEO_YC_DLY, 0},
        {P_ENCP_VIDEO_RGB_CTRL, 2},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -499,7 +454,6 @@ static const struct reg_s tvregs_4k2k_30hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -531,7 +485,6 @@ static const struct reg_s tvregs_4k2k_25hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -563,7 +516,6 @@ static const struct reg_s tvregs_4k2k_24hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -595,7 +547,6 @@ static const struct reg_s tvregs_4k2k_smpte[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 53},
        {P_ENCP_VIDEO_MAX_LNCNT, 2249},
        {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -617,7 +568,6 @@ static const struct reg_s tvregs_4k2k_smpte_25hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -639,7 +589,6 @@ static const struct reg_s tvregs_4k2k_smpte_30hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -661,7 +610,6 @@ static const struct reg_s tvregs_4k2k_smpte_50hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -683,7 +631,6 @@ static const struct reg_s tvregs_4k2k_smpte_60hz[] = {
        {P_ENCP_VIDEO_VSO_END, 0x32,},
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -723,7 +670,6 @@ static const struct reg_s tvregs_2560x1080p50hz[] = {
        {P_ENCP_VIDEO_RGB_CTRL, 2},
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -762,7 +708,6 @@ static const struct reg_s tvregs_2560x1080p60hz[] = {
        {P_ENCP_VIDEO_RGB_CTRL, 2},
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -785,7 +730,6 @@ static const struct reg_s tvregs_vesa_640x480p60hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0x2,},
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -809,7 +753,6 @@ static const struct reg_s tvregs_vesa_800x600p60hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -833,7 +776,6 @@ static const struct reg_s tvregs_vesa_800x480p60hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0x0},
        {P_ENCP_VIDEO_VSO_ELINE, 0x7},
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -857,7 +799,6 @@ static const struct reg_s tvregs_vesa_852x480p60hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -881,7 +822,6 @@ static const struct reg_s tvregs_vesa_854x480p60hz[] = {
        {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
        {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -907,7 +847,6 @@ static const struct reg_s tvregs_vesa_1024x600p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -933,7 +872,6 @@ static const struct reg_s tvregs_vesa_1024x768p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -959,7 +897,6 @@ static const struct reg_s tvregs_vesa_1152x864p75hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -987,7 +924,6 @@ static const struct reg_s tvregs_vesa_1280x600p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 #endif
 };
@@ -1014,7 +950,6 @@ static const struct reg_s tvregs_vesa_1280x768p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1040,7 +975,6 @@ static const struct reg_s tvregs_vesa_1280x800p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1066,7 +1000,6 @@ static const struct reg_s tvregs_vesa_1280x960p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1092,7 +1025,6 @@ static const struct reg_s tvregs_vesa_1280x1024p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1118,7 +1050,6 @@ static const struct reg_s tvregs_vesa_1360x768p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1145,7 +1076,6 @@ static const struct reg_s tvregs_vesa_1366x768p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1172,7 +1102,6 @@ static const struct reg_s tvregs_vesa_1400x1050p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1199,7 +1128,6 @@ static const struct reg_s tvregs_vesa_1440x900p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1226,7 +1154,6 @@ static const struct reg_s tvregs_vesa_1440x2560p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1253,7 +1180,6 @@ static const struct reg_s tvregs_vesa_1600x900p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1280,7 +1206,6 @@ static const struct reg_s tvregs_vesa_1600x1200p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1306,7 +1231,6 @@ static const struct reg_s tvregs_vesa_1680x1050p60hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1,},
        {P_ENCI_VIDEO_EN, 0,},
        {MREG_END_MARKER, 0}
 };
@@ -1333,7 +1257,6 @@ static const struct reg_s tvregs_vesa_1920x1200p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1357,7 +1280,6 @@ static const struct reg_s tvregs_vesa_2160x1200p90hz[] = {
        {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
-       {P_ENCP_VIDEO_EN, 1},
        {P_ENCI_VIDEO_EN, 0},
        {MREG_END_MARKER, 0},
 };
@@ -1384,7 +1306,6 @@ static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1411,7 +1332,6 @@ static const struct reg_s tvregs_vesa_2560x1080p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1437,7 +1357,6 @@ static const struct reg_s tvregs_vesa_2560x1440p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 
@@ -1463,7 +1382,6 @@ static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
 
        {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0}
 };
 #endif
@@ -1490,7 +1408,7 @@ static struct vic_tvregs_set tvregsTab[] = {
        {HDMI_1920x1080i50_16x9, tvregs_1080i_50hz},
        {HDMI_1920x1080p50_16x9, tvregs_1080p_50hz},
        {HDMI_1920x1080p25_16x9, tvregs_1080p_50hz},
-       {HDMI_1920x1080p30_16x9, tvregs_1080p_30hz},
+       {HDMI_1920x1080p30_16x9, tvregs_1080p},
        {HDMI_1920x1080p24_16x9, tvregs_1080p_24hz},
        {HDMI_3840x2160p30_16x9, tvregs_4k2k_30hz},
        {HDMI_3840x2160p25_16x9, tvregs_4k2k_25hz},
@@ -1573,7 +1491,6 @@ static const struct reg_s tvregs_3dfp_1080p60[] = {
        {P_ENCP_DE_V_END_ODD, 0x0,},
 
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -1613,7 +1530,6 @@ static const struct reg_s tvregs_3dfp_1080p24[] = {
        {P_ENCP_DE_V_END_ODD, 0x0,},
 
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -1653,7 +1569,6 @@ static const struct reg_s tvregs_3dfp_1080p50[] = {
        {P_ENCP_DE_V_END_ODD, 0x0,},
 
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -1693,7 +1608,6 @@ static const struct reg_s tvregs_3dfp_720p50[] = {
        {P_ENCP_DE_V_END_ODD, 0x0,},
 
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 
@@ -1733,7 +1647,6 @@ static const struct reg_s tvregs_3dfp_720p60[] = {
        {P_ENCP_DE_V_END_ODD, 0x0,},
 
        {P_ENCI_VIDEO_EN, 0},
-       {P_ENCP_VIDEO_EN, 1},
        {MREG_END_MARKER, 0},
 };
 

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 2185452..14385cc 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -759,12 +759,9 @@ static void enc_vpu_bridge_reset(int mode)
 
        wr_clk = (hd_read_reg(P_VPU_HDMI_SETTING) & 0xf00) >> 8;
        if (mode) {
-               hd_write_reg(P_ENCP_VIDEO_EN, 0);
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2);
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4);
                mdelay(1);
-               hd_write_reg(P_ENCP_VIDEO_EN, 1);
-               mdelay(1);
                hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
                mdelay(1);
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 2, 0, 2);
@@ -1113,7 +1110,6 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
                        (0 << 12)
        );
        hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
-       hd_write_reg(P_ENCP_VIDEO_EN, 1);
 }
 
 static void hdmi_tvenc480i_set(struct hdmitx_vidpara *param)
@@ -1805,7 +1801,6 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
                        (0 << 12)
                );
                hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
-               hd_write_reg(P_ENCP_VIDEO_EN, 1); /* Enable VENC */
                break;
        case HDMI_480p60_16x9_rpt:
        case HDMI_576p50_16x9_rpt:
@@ -2283,12 +2278,12 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev)
 
        hdmitx_set_enc_hw(hdev);
 
-       hdmitx_set_hw(hdev);
-
        /* For 3D, enable phy by SystemControl at last step */
        if ((!hdev->flag_3dfp) && (!hdev->flag_3dtb) && (!hdev->flag_3dss))
                hdmitx_set_phy(hdev);
 
+       hdmitx_set_hw(hdev);
+
        return 0;
 }
 
@@ -6060,7 +6055,6 @@ static void config_hdmi20_tx(enum hdmi_vic vic,
        /* Reset pulse */
        hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f);
 
-       hd_write_reg(P_ENCP_VIDEO_EN, 0);
        hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0xdf);
        hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0);
        mdelay(10);
@@ -6078,8 +6072,7 @@ static void config_hdmi20_tx(enum hdmi_vic vic,
                hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH));
 
        hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0);
-       hd_write_reg(P_ENCP_VIDEO_EN, 0xff);
-
+       hd_write_reg(P_ENCP_VIDEO_EN, 1); /* enable it finially */
        hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 0, 3, 1);
        mdelay(1);
        hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 1, 3, 1);