;;- Machine description for GNU compiler
;;- MIL-STD-1750A version.
-;; Copyright (C) 1994, 1995 Free Software Foundation, Inc.
-;; Contributed by O.M.Kellogg, DASA (kellogg@space.otn.dasa.de).
+;; Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
+;; Contributed by O.M.Kellogg, DASA (oliver.kellogg@space.otn.dasa.de).
;; This file is part of GNU CC.
;; block move.
-; there is a problem with this insn in gcc-2.2.3
-; (clobber (match_dup 2)) does not prevent use of this operand later
-;
(define_insn "movstrqi"
- [(set (mem:BLK (match_operand:QI 0 "register_operand" "r"))
- (mem:BLK (match_operand:QI 1 "register_operand" "r")))
- (use (match_operand:QI 2 "register_operand" "r"))
- (use (match_operand:QI 3 "immediate_operand" ""))
+ [(set (match_operand:BLK 0 "mov_memory_operand" "m")
+ (match_operand:BLK 1 "mov_memory_operand" "m"))
+ (use (match_operand:QI 2 "general_operand" "r"))
+ (match_operand 3 "" "")
(clobber (match_dup 0))
(clobber (match_dup 1))
(clobber (match_dup 2))]
""
- "* return (char *)movcnt_regno_adjust(operands); ")
+ "*
+ {
+ rtx regops[3];
+ regops[0] = XEXP(operands[0],0);
+ regops[1] = XEXP(operands[1],0);
+ regops[2] = operands[2];
+ return (char *)movcnt_regno_adjust(regops);
+ } ")
;; compare instructions.
(define_insn "cmphf"
[(set (cc0)
- (compare (match_operand:HF 0 "general_operand" "r,z,r")
- (match_operand:HF 1 "general_operand" "r,Q,m")))]
+ (compare (match_operand:HF 0 "general_operand" "r,r")
+ (match_operand:HF 1 "general_operand" "r,m")))]
""
"@
fcr r%0,r%1
- fcb %Q1
fc r%0,%1 ")
(define_insn "cmptqf"
{
rtx new_operands[2];
new_operands[0] = operands[0];
- new_operands[1] = gen_rtx (REG, HImode, REGNO(operands[1]) + 1);
+ new_operands[1] = gen_rtx (REG, QImode, REGNO(operands[1]) + 1);
output_asm_insn(\"lr r%0,r%1 ;trunchiqi2\",new_operands);
return \";\";
} ")
-;; zero extension instructions
-
-(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (zero_extend:HI (match_operand:QI 1 "general_operand" "r,m,i")))]
- ""
- "*
- {
- rtx new_opnds[2];
- output_asm_insn(\"xorr r%0,r%0 ;zero_extendqihi2\",operands);
- new_opnds[0] = gen_rtx (REG, HImode, REGNO(operands[0]) + 1);
- new_opnds[1] = operands[1];
- switch (which_alternative)
- {
- case 0:
- output_asm_insn(\"lr r%0,r%1\",new_opnds);
- break;
- case 1:
- output_asm_insn(\"l r%0,%1\",new_opnds);
- break;
- case 2:
- output_asm_insn(\"lim r%0,%1\",new_opnds);
- break;
- }
- return \";\";
- } ")
+;; zero extension instructions: not defined, GCC can synthesize
;; sign extension instructions
new_opnds[1] = operands[1];
output_asm_insn(\"xorr r%0,r%0 ;extendhftqf2\",new_opnds);
if (which_alternative == 0)
- return \"dlr r%0,r%1 ; put condition codes back on track\";
+ return \"dlr r%0,r%1\";
else
- return \"dl r%0,%1 ; put condition codes back on track\";
+ return \"dl r%0,%1\";
} ")
; 1750 TQF-to-HF truncate is a no-op: just leave away the least signif. 16 bits
;; 16-bit moves
(define_insn "movqi"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,t,r,Q,m,m")
- (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,Q,m,t,r,K"))]
+ [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,r,r,m,m")
+ (match_operand:QI 1 "general_operand" "O,I,J,M,i,r,m,r,K"))]
""
"@
xorr r%0,r%0
lim r%0,%1 ; 'M' constraint
lim r%0,%1 ; 'i' constraint
lr r%0,r%1
- lb %Q1
l r%0,%1
- stb %Q0
st r%1,%0
stc %1,%0 ")
}
")
+; Move small constant to memory, HImode
+(define_insn ""
+ [(set (match_operand:HI 0 "memory_operand" "=m")
+ (match_operand:HI 1 "small_nonneg_const" "K"))]
+ ""
+ "*
+ {
+ rtx new_opnds[2];
+ new_opnds[0] = operands[0];
+ new_opnds[1] = operands[1];
+ output_asm_insn (\"stc 0,%0 ;movhi cst->mem\", new_opnds);
+ add_1_to_mem (new_opnds[0]);
+ output_asm_insn (\"stc %1,%0\", new_opnds);
+ return \";\";
+ }
+ ")
+
(define_insn "movhi"
- [(set (match_operand:HI 0 "general_operand" "=r,z,r,Q,m")
- (match_operand:HI 1 "general_operand" "r,Q,m,z,r"))]
+ [(set (match_operand:HI 0 "general_operand" "=r,r,m")
+ (match_operand:HI 1 "general_operand" "r,m,r"))]
""
"@
dlr r%0,r%1
- dlb %Q1
dl r%0,%1
- dstb %Q0
dst r%1,%0 ")
-;; Single-Float moves are *same* as HImode moves:
+;; Single-Float moves are similar to HImode moves
-;(define_insn "movhf"
-; [(set (match_operand:HF 0 "general_operand" "=r,r,r,m")
-; (match_operand:HF 1 "general_operand" "F,r,m,r"))]
-; ""
-; "@
-; %D1\;dl r%0,%F1
-; dlr r%0,r%1
-; dl r%0,%1
-; dst r%1,%0 ")
+; Move HFmode zero to memory
+(define_insn ""
+ [(set (match_operand:HF 0 "memory_operand" "=m")
+ (match_operand:HF 1 "zero_operand" "G"))]
+ ""
+ "*
+ {
+ rtx new_opnds[2];
+ new_opnds[0] = operands[0];
+ new_opnds[1] = operands[1];
+ output_asm_insn (\"stc 0,%0 ;movhf 0.0->mem\", new_opnds);
+ add_1_to_mem (new_opnds[0]);
+ output_asm_insn (\"stc 0,%0\", new_opnds);
+ return \";\";
+ }
+ ")
(define_insn "movhf"
- [(set (match_operand:HF 0 "general_operand" "=r,z,r,Q,m")
- (match_operand:HF 1 "general_operand" "r,Q,m,z,r"))]
+ [(set (match_operand:HF 0 "general_operand" "=r,r,m")
+ (match_operand:HF 1 "general_operand" "r,m,r"))]
""
"@
dlr r%0,r%1
- dlb %Q1
dl r%0,%1
- dstb %Q0
dst r%1,%0 ")
;; Longfloat moves
-;(define_insn "movtqf"
-; [(set (match_operand:TQF 0 "general_operand" "=r,r,r,m")
-; (match_operand:TQF 1 "general_operand" "F,r,m,r"))]
-; ""
-; "@
-; %E1\;efl r%0,%G1
-; eflr.m %0,%1
-; efl r%0,%1
-; efst r%1,%0 ")
+; Move TQFmode zero to memory
+(define_insn ""
+ [(set (match_operand:TQF 0 "memory_operand" "=m")
+ (match_operand:TQF 1 "zero_operand" "G"))]
+ ""
+ "*
+ {
+ rtx new_opnds[2];
+ new_opnds[0] = operands[0];
+ new_opnds[1] = operands[1];
+ output_asm_insn (\"stc 0,%0 ;movtqf 0.0->mem\", new_opnds);
+ add_1_to_mem (new_opnds[0]);
+ output_asm_insn (\"stc 0,%0\", new_opnds);
+ add_1_to_mem (new_opnds[0]);
+ output_asm_insn (\"stc 0,%0\", new_opnds);
+ return \";\";
+ }
+ ")
(define_insn "movtqf"
[(set (match_operand:TQF 0 "general_operand" "=r,r,m")
;; single integer
(define_insn "addqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,t,r,m,m")
- (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,J,i,r,Q,m,I,J")))]
+ [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,r,m,m")
+ (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "I,J,i,r,m,I,J")))]
""
"*
switch (which_alternative)
case 3:
return \"ar r%0,r%2\";
case 4:
- return \"ab %Q2\";
- case 5:
return \"a r%0,%2\";
- case 6:
+ case 5:
return \"incm %2,%0\";
- case 7:
+ case 6:
return \"decm %J2,%0\";
} ")
da r%0,%2 ")
(define_insn "addhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,z,r")
- (plus:HF (match_operand:HF 1 "register_operand" "%0,0,0")
- (match_operand:HF 2 "general_operand" "r,Q,m")))]
+ [(set (match_operand:HF 0 "register_operand" "=r,r")
+ (plus:HF (match_operand:HF 1 "register_operand" "%0,0")
+ (match_operand:HF 2 "general_operand" "r,m")))]
""
"@
far r%0,r%2
- fab %Q2
fa r%0,%2 ")
(define_insn "addtqf3"
;; single integer
(define_insn "subqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,r,t,r,m")
- (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "I,i,r,Q,m,I")))]
+ [(set (match_operand:QI 0 "general_operand" "=r,r,r,r,m")
+ (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "I,i,r,m,I")))]
""
"@
sisp r%0,%2
sim r%0,%2
sr r%0,r%2
- sbb %Q2
s r%0,%2
decm %2,%0 ")
ds r%0,%2 ")
(define_insn "subhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,z,r")
- (minus:HF (match_operand:HF 1 "register_operand" "0,0,0")
- (match_operand:HF 2 "general_operand" "r,Q,m")))]
+ [(set (match_operand:HF 0 "register_operand" "=r,r")
+ (minus:HF (match_operand:HF 1 "register_operand" "0,0")
+ (match_operand:HF 2 "general_operand" "r,m")))]
""
"@
fsr r%0,r%2
- fsb %Q2
fs r%0,%2 ")
(define_insn "subtqf3"
; 32-bit product
(define_insn "mulqihi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,t,r")
- (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+ (mult:HI (match_operand:QI 1 "register_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "M,r,m")))]
""
"@
mim r%0,%1
mr r%0,r%2
- mb %Q2
m r%0,%2 ")
(define_insn "mulhi3"
; not available on 1750: "umulhi3","umulhisi3","umulsi3" (unsigned multiply's)
(define_insn "mulhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,z,r")
- (mult:HF (match_operand:HF 1 "register_operand" "%0,0,0")
- (match_operand:HF 2 "general_operand" "r,Q,m")))]
+ [(set (match_operand:HF 0 "register_operand" "=r,r")
+ (mult:HF (match_operand:HF 1 "register_operand" "%0,0")
+ (match_operand:HF 2 "general_operand" "r,m")))]
""
"@
fmr r%0,r%2
- fmb %Q2
fm r%0,%2 ")
(define_insn "multqf3"
dd r%0,%2 ")
(define_insn "divhf3"
- [(set (match_operand:HF 0 "register_operand" "=r,z,r")
- (div:HF (match_operand:HF 1 "register_operand" "0,0,0")
- (match_operand:HF 2 "general_operand" "r,Q,m")))]
+ [(set (match_operand:HF 0 "register_operand" "=r,r")
+ (div:HF (match_operand:HF 1 "register_operand" "0,0")
+ (match_operand:HF 2 "general_operand" "r,m")))]
""
"@
fdr r%0,r%2
- fdb %Q2
fd r%0,%2 ")
(define_insn "divtqf3"
;; AND
(define_insn "andqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
- (and:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
+ [(set (match_operand:QI 0 "general_operand" "=r,r,r")
+ (and:QI (match_operand:QI 1 "general_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "M,r,m")))]
""
"@
andm r%0,%2
andr r%0,r%2
- andb %Q2
and r%0,%2 ")
; This sets incorrect condition codes. See notice_update_cc()
;; OR
(define_insn "iorqi3"
- [(set (match_operand:QI 0 "general_operand" "=r,r,t,r")
- (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
- (match_operand:QI 2 "general_operand" "M,r,Q,m")))]
+ [(set (match_operand:QI 0 "general_operand" "=r,r,r")
+ (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0")
+ (match_operand:QI 2 "general_operand" "M,r,m")))]
""
"@
orim r%0,%2
orr r%0,r%2
- orb %Q2
or r%0,%2 ")
; This sets incorrect condition codes. See notice_update_cc()
else
{
rtx new_opnds[2];
- new_opnds[0] = gen_rtx (REG, QImode, REGNO(operands[0]));
- new_opnds[1] = gen_rtx (REG, QImode, REGNO(operands[0]) + 1);
- output_asm_insn(\"lr r%0,r%1 ; ashlhi3 shiftcount > 16\",new_opnds);
+ output_asm_insn(\"dsll r%0,16 ; ashlhi3 shiftcount > 16\",operands);
+ new_opnds[0] = operands[0];
new_opnds[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL(operands[2]) - 16);
output_asm_insn(\"sll r%0,%1\",new_opnds);
return \";\";
;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
;; which isn't valid.
(define_expand "lshrqi3"
- [(set (match_operand:QI 0 "general_operand" "=r")
- (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "g")))]
""
"
;; Same applies for arithmetic shift right.
(define_expand "ashrqi3"
- [(set (match_operand:QI 0 "general_operand" "=r")
- (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "g")))]
""
"
;; HImode arithmetic shift right.
(define_expand "ashrhi3"
- [(set (match_operand:HI 0 "general_operand" "=r")
- (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "g")))]
""
"
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