In order to make sure RCS engine is idle, we need to add
DC flush + CS stall + Render target Cache flush + Depth Cache
on Gfx 12 and additional CCS cache flush on Gfx12.5.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23786>
iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+ PIPE_CONTROL_STATE_CACHE_INVALIDATE |
+ (GFX_VERx10 == 125 ?
+ PIPE_CONTROL_CCS_CACHE_FLUSH : 0));
/* If the aux-map state number increased, then we need to rewrite the
* register. Rewriting the register is used to both set the aux-map