drm/etnaviv: add workaround for GC620 on TH1520 (0x5552)

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
(cherry picked from commit 373e8161c571f1326f505b2c77c2e68342aac69d)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 36799f59ec4e287d8a529c65560173e4ba120fc5..5683cfcdb8589201d8c7f33c11b06c1457b8d76e 100644 (file)
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -523,6 +523,10 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
                control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
                gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 
+               if (etnaviv_is_model_rev(gpu, GC620, 0x5552)) {
+                       gpu_write(gpu, 0x00800, 0x10);
+               }
+
                if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) {
                        gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
                                  VIVS_MMUv2_AHB_CONTROL_RESET);
@@ -748,6 +752,12 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
                gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
        }
 
+       /* FIXME: use feature bit 5 of minor features 12, G2D_DEC400EX */
+       if (etnaviv_is_model_rev(gpu, GC620, 0x5552)) {
+               gpu_write(gpu, 0x800, 0x2010188);
+               gpu_write(gpu, 0x808, 0x3fc104);
+       }
+
        if (gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) {
                u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
                val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;