powerpc: Fix vsx_splat_v4si in 32 bit mode

Tamar's recent patch to teach CSE to perform vector extract exercises
VSX splat more frequently, which exposed a constraint error for the
vsx_splat patterns.  The pattern could be created for Power9, but
the "we constraint only provided alternatives in 64 bit mode. The
instructions are valid in 32 bit mode and SImode is allowed in VSX
registers.  This patch updates the constraints from "we" to "wa" to
allow the pattern and fix the failing testcases.

gcc/ChangeLog:

	* config/rs6000/vsx.md (vsx_splat_v4si): Change constraints to "wa".
	(vsx_splat_v4si_di): Change constraint to "wa".

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0bf04fe..a97f7f2 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4565,7 +4565,7 @@
 
 ;; V4SI splat support
 (define_insn "vsx_splat_v4si"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=we,we")
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
        (vec_duplicate:V4SI
         (match_operand:SI 1 "splat_input_operand" "r,Z")))]
   "TARGET_P9_VECTOR"
@@ -4578,7 +4578,7 @@
 ;; allows us to use direct move to get the value in a vector register
 ;; so that we can use XXSPLTW
 (define_insn "vsx_splat_v4si_di"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we")
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
        (vec_duplicate:V4SI
         (truncate:SI
          (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))]