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AVX-512. 59/n. Add vptest[n]m, ucmp, cmpeq insn patterns.
authorkyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 14 Oct 2014 08:15:32 +0000 (08:15 +0000)
committerkyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Tue, 14 Oct 2014 08:15:32 +0000 (08:15 +0000)
gcc/
* config/i386/i386.c
(ix86_expand_args_builtin): Handle CODE_FOR_avx512vl_cmpv4di3_mask,
CODE_FOR_avx512vl_cmpv8si3_mask, CODE_FOR_avx512vl_ucmpv4di3_mask,
CODE_FOR_avx512vl_ucmpv8si3_mask, CODE_FOR_avx512vl_cmpv2di3_mask,
CODE_FOR_avx512vl_cmpv4si3_mask, CODE_FOR_avx512vl_ucmpv2di3_mask,
CODE_FOR_avx512vl_ucmpv4si3_mask.
* config/i386/sse.md
(define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"): Delete.
"<avx512>_ucmp<VI12_AVX512VL:mode>3<mask_scalar_merge_name>"):New.
(define_insn
"<avx512>_ucmp<VI48_AVX512VL:mode>3<mask_scalar_merge_name>"):Ditto.
(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"): Ditto.
(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"): Ditto.
(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"): Ditto.
(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"): Ditto.
(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"): Ditto.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@216177 138bc75d-0d04-0410-961f-82ee72b054a4

gcc/ChangeLog patch | blob | history
gcc/config/i386/i386.c patch | blob | history
gcc/config/i386/sse.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 604e34c..5ee1d70 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -7,6 +7,32 @@
            Kirill Yukhin  <kirill.yukhin@intel.com>
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 
+       * config/i386/i386.c
+       (ix86_expand_args_builtin): Handle CODE_FOR_avx512vl_cmpv4di3_mask,
+       CODE_FOR_avx512vl_cmpv8si3_mask, CODE_FOR_avx512vl_ucmpv4di3_mask,
+       CODE_FOR_avx512vl_ucmpv8si3_mask, CODE_FOR_avx512vl_cmpv2di3_mask,
+       CODE_FOR_avx512vl_cmpv4si3_mask, CODE_FOR_avx512vl_ucmpv2di3_mask,
+       CODE_FOR_avx512vl_ucmpv4si3_mask.
+       * config/i386/sse.md
+       (define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"): Delete.
+       "<avx512>_ucmp<VI12_AVX512VL:mode>3<mask_scalar_merge_name>"):New.
+       (define_insn
+       "<avx512>_ucmp<VI48_AVX512VL:mode>3<mask_scalar_merge_name>"):Ditto.
+       (define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"): Ditto.
+       (define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"): Ditto.
+       (define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"): Ditto.
+       (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"): Ditto.
+       (define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"): Ditto.
+
+2014-10-14  Alexander Ivchenko  <alexander.ivchenko@intel.com>
+           Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+           Anna Tikhonova  <anna.tikhonova@intel.com>
+           Ilya Tocar  <ilya.tocar@intel.com>
+           Andrey Turetskiy  <andrey.turetskiy@intel.com>
+           Ilya Verbin  <ilya.verbin@intel.com>
+           Kirill Yukhin  <kirill.yukhin@intel.com>
+           Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
        * config/i386/sse.md
        (define_expand "vec_widen_umult_even_v8si<mask_name>"): Add masking.
        (define_insn "*vec_widen_umult_even_v8si<mask_name>"): Ditto.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1c38353..a485bb1 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -34108,6 +34108,14 @@ ix86_expand_args_builtin (const struct builtin_description *d,
              case CODE_FOR_avx512f_cmpv16si3_mask:
              case CODE_FOR_avx512f_ucmpv8di3_mask:
              case CODE_FOR_avx512f_ucmpv16si3_mask:
+             case CODE_FOR_avx512vl_cmpv4di3_mask:
+             case CODE_FOR_avx512vl_cmpv8si3_mask:
+             case CODE_FOR_avx512vl_ucmpv4di3_mask:
+             case CODE_FOR_avx512vl_ucmpv8si3_mask:
+             case CODE_FOR_avx512vl_cmpv2di3_mask:
+             case CODE_FOR_avx512vl_cmpv4si3_mask:
+             case CODE_FOR_avx512vl_ucmpv2di3_mask:
+             case CODE_FOR_avx512vl_ucmpv4si3_mask:
                error ("the last argument must be a 3-bit immediate");
                return const0_rtx;
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 70cfa6a..99fd5cf 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2522,11 +2522,25 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "avx512f_ucmp<mode>3<mask_scalar_merge_name>"
+(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI48_512 1 "register_operand" "v")
-          (match_operand:VI48_512 2 "nonimmediate_operand" "vm")
+         [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
+          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
+          (match_operand:SI 3 "const_0_to_7_operand" "n")]
+         UNSPEC_UNSIGNED_PCMP))]
+  "TARGET_AVX512BW"
+  "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
+  [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<avx512>_ucmp<mode>3<mask_scalar_merge_name>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+       (unspec:<avx512fmaskmode>
+         [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
+          (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
           (match_operand:SI 3 "const_0_to_7_operand" "n")]
          UNSPEC_UNSIGNED_PCMP))]
   "TARGET_AVX512F"
@@ -10152,20 +10166,42 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
-(define_expand "avx512f_eq<mode>3<mask_scalar_merge_name>"
+(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
+       (unspec:<avx512fmaskmode>
+         [(match_operand:VI12_AVX512VL 1 "register_operand")
+          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
+         UNSPEC_MASKED_EQ))]
+  "TARGET_AVX512BW"
+  "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
+
+(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI48_512 1 "register_operand")
-          (match_operand:VI48_512 2 "nonimmediate_operand")]
+         [(match_operand:VI48_AVX512VL 1 "register_operand")
+          (match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
          UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F"
   "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
 
-(define_insn "avx512f_eq<mode>3<mask_scalar_merge_name>_1"
+(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI48_512 1 "register_operand" "%v")
-          (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
+         [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
+          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
+         UNSPEC_MASKED_EQ))]
+  "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
+  "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+  [(set_attr "type" "ssecmp")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+       (unspec:<avx512fmaskmode>
+         [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
+          (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
          UNSPEC_MASKED_EQ))]
   "TARGET_AVX512F && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
   "vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
@@ -10248,11 +10284,11 @@
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
-(define_insn "avx512f_gt<mode>3<mask_scalar_merge_name>"
+(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-         [(match_operand:VI48_512 1 "register_operand" "v")
-          (match_operand:VI48_512 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))]
+         [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
+          (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))]
   "TARGET_AVX512F"
   "vpcmpgt<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
   [(set_attr "type" "ssecmp")
@@ -10260,6 +10296,18 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
+(define_insn "<avx512>_gt<mode>3<mask_scalar_merge_name>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+       (unspec:<avx512fmaskmode>
+         [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
+          (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] UNSPEC_MASKED_GT))]
+  "TARGET_AVX512BW"
+  "vpcmpgt<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+  [(set_attr "type" "ssecmp")
+   (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
 (define_insn "sse2_gt<mode>3"
   [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
        (gt:VI124_128
@@ -10653,22 +10701,44 @@
              ]
              (const_string "<sseinsnmode>")))])
 
-(define_insn "avx512f_testm<mode>3<mask_scalar_merge_name>"
+(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-        [(match_operand:VI48_512 1 "register_operand" "v")
-         (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
+        [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
+         (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
+        UNSPEC_TESTM))]
+  "TARGET_AVX512BW"
+  "vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode"  "<sseinsnmode>")])
+
+(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+       (unspec:<avx512fmaskmode>
+        [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
+         (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
         UNSPEC_TESTM))]
   "TARGET_AVX512F"
   "vptestm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
   [(set_attr "prefix" "evex")
    (set_attr "mode"  "<sseinsnmode>")])
 
-(define_insn "avx512f_testnm<mode>3<mask_scalar_merge_name>"
+(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
+  [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
+       (unspec:<avx512fmaskmode>
+        [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
+         (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
+        UNSPEC_TESTNM))]
+  "TARGET_AVX512BW"
+  "vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
+  [(set_attr "prefix" "evex")
+   (set_attr "mode"  "<sseinsnmode>")])
+
+(define_insn "<avx512>_testnm<mode>3<mask_scalar_merge_name>"
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
        (unspec:<avx512fmaskmode>
-        [(match_operand:VI48_512 1 "register_operand" "v")
-         (match_operand:VI48_512 2 "nonimmediate_operand" "vm")]
+        [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
+         (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
         UNSPEC_TESTNM))]
   "TARGET_AVX512F"
   "vptestnm<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}"
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