drm/i915/gen9: WA ST Unit Power Optimization Disable
authorRobert Beckett <robert.beckett@intel.com>
Tue, 8 Sep 2015 09:31:52 +0000 (10:31 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 14 Sep 2015 14:59:39 +0000 (16:59 +0200)
WaDisableSTUnitPowerOptimization:skl,bxt

Signed-off-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c

index 495ac17..dd3d235 100644 (file)
@@ -6943,6 +6943,9 @@ enum skl_disp_power_wells {
 #define HSW_ROW_CHICKEN3               0xe49c
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
+#define HALF_SLICE_CHICKEN2            0xe180
+#define   GEN8_ST_PO_DISABLE           (1<<13)
+
 #define HALF_SLICE_CHICKEN3            0xe184
 #define   HSW_SAMPLE_C_PERFORMANCE     (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
index 684e069..16a4ead 100644 (file)
@@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
                                  GEN8_SAMPLER_POWER_BYPASS_DIS);
        }
 
+       /* WaDisableSTUnitPowerOptimization:skl,bxt */
+       WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+
        return 0;
 }