DRM_ERROR("failed to create stop work.\n");
goto err_free_start;
}
-
- init_completion(&c_node->stop_complete);
}
c_node->event_work = pp_create_event_work();
mutex_init(&c_node->lock);
mutex_init(&c_node->mem_lock);
mutex_init(&c_node->event_lock);
- init_completion(&c_node->start_complete);
+ init_completion(&c_node->cmd_complete);
+ complete(&c_node->cmd_complete);
for_each_pp_ops(i)
INIT_LIST_HEAD(&c_node->mem_list[i]);
} else {
mutex_lock(&ppdrv->drv_lock);
- reinit_completion(&c_node->start_complete);
-
ret = pp_start_property(ppdrv, c_node);
if (ret) {
DRM_INFO("%s:failed to start property:id[%d]\n"
return -EINVAL;
}
- DRM_INFO("%s:prop_id[%d]ops_id[%s]buf_id[%d][%s]\n",
+ DRM_DEBUG("%s:prop_id[%d]ops_id[%s]buf_id[%d][%s]\n",
__func__, qbuf->prop_id, qbuf->ops_id ? "dst" : "src",
qbuf->buf_id, qbuf->buf_type ? "dq" : "eq");
} else {
mutex_lock(&ppdrv->drv_lock);
- reinit_completion(&c_node->start_complete);
-
ret = pp_start_property(ppdrv, c_node);
if (ret) {
DRM_INFO("%s:failed to start property:id[%d]\n"
cmd_work = c_node->stop_work;
cmd_work->ctrl = cmd_ctrl->ctrl;
pp_handle_cmd_work(dev, ppdrv, cmd_work, c_node);
-
- if (!wait_for_completion_timeout(&c_node->stop_complete,
- msecs_to_jiffies(300))) {
- DRM_ERROR("timeout stop:prop_id[%d]\n",
- c_node->property.prop_id);
- }
} else {
ret = pp_stop_property(ppdrv->drm_dev, ppdrv,
c_node);
cmd_work = c_node->stop_work;
cmd_work->ctrl = cmd_ctrl->ctrl;
pp_handle_cmd_work(dev, ppdrv, cmd_work, c_node);
-
- if (!wait_for_completion_timeout(&c_node->stop_complete,
- msecs_to_jiffies(300))) {
- DRM_ERROR("timeout stop:prop_id[%d]\n",
- c_node->property.prop_id);
- }
} else {
ret = pp_stop_property(ppdrv->drm_dev, ppdrv,
c_node);
} else {
mutex_lock(&ppdrv->drv_lock);
- reinit_completion(&c_node->start_complete);
-
ret = pp_start_property(ppdrv, c_node);
if (ret) {
DRM_INFO("%s:failed to start property:id[%d]\n"
return 0;
}
+void pp_wait_completion(struct tdm_pp_cmd_node *c_node)
+{
+ int ret;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ ret = wait_for_completion_timeout(
+ &c_node->cmd_complete, msecs_to_jiffies(120));
+ if (ret < 0)
+ DRM_ERROR("failed to wait completion:ret[%d]\n", ret);
+ else if (!ret)
+ DRM_ERROR("timeout\n");
+}
+
int pp_start_property(struct tdm_ppdrv *ppdrv,
struct tdm_pp_cmd_node *c_node)
{
goto err_unlock;
}
+ reinit_completion(&c_node->cmd_complete);
+
/* set current property in ppdrv */
ret = pp_set_property(ppdrv, property);
if (ret) {
}
}
+ pp_wait_completion(c_node);
+
return 0;
err_unlock:
DRM_DEBUG_KMS("prop_id[%d]\n", property->prop_id);
+ pp_wait_completion(c_node);
+
/* stop operations */
if (ppdrv->stop)
ppdrv->stop(ppdrv->dev, property->cmd);
case PP_CTRL_PLAY:
case PP_CTRL_RESUME:
ret = pp_start_property(ppdrv, c_node);
- if (ret) {
+ if (ret)
DRM_ERROR("failed to start property:prop_id[%d]\n",
c_node->property.prop_id);
- goto err_unlock;
- }
-
- /*
- * M2M case supports wait_completion of transfer.
- * because M2M case supports single unit operation
- * with multiple queue.
- * M2M need to wait completion of data transfer.
- */
- if (pp_is_m2m_cmd(property->cmd)) {
- if (!wait_for_completion_timeout
- (&c_node->start_complete, msecs_to_jiffies(200))) {
- DRM_ERROR("timeout event:prop_id[%d]\n",
- c_node->property.prop_id);
- goto err_unlock;
- }
- }
break;
case PP_CTRL_STOP:
case PP_CTRL_PAUSE:
ret = pp_stop_property(ppdrv->drm_dev, ppdrv,
c_node);
- if (ret) {
+ if (ret)
DRM_ERROR("failed to stop property.\n");
- goto err_unlock;
- }
-
- complete(&c_node->stop_complete);
break;
default:
DRM_ERROR("unknown control type\n");
DRM_DEBUG_KMS("ctrl[%d] done.\n", cmd_work->ctrl);
-err_unlock:
mutex_unlock(&c_node->lock);
mutex_unlock(&ppdrv->drv_lock);
}
err_completion:
if (pp_is_m2m_cmd(c_node->property.cmd))
- complete(&c_node->start_complete);
+ complete_all(&c_node->cmd_complete);
}
static int pp_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
{
u32 cfg;
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
/* s/w reset */
cfg = sc_read(SCALER_CFG);
{
u32 cfg;
- DRM_INFO("%s:enable[%d]\n", __func__, enable);
+ DRM_DEBUG("%s:enable[%d]\n", __func__, enable);
cfg = sc_read(SCALER_INT_EN);
{
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
- DRM_INFO("%s:fmt[0x%x]\n", __func__, fmt);
+ DRM_DEBUG("%s:fmt[0x%x]\n", __func__, fmt);
switch (fmt) {
case DRM_FORMAT_RGB565:
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
u32 cfg;
- DRM_INFO("%s:fmt[0x%x]\n", __func__, fmt);
+ DRM_DEBUG("%s:fmt[0x%x]\n", __func__, fmt);
cfg = sc_read(SCALER_SRC_CFG);
cfg &= ~(SCALER_CFG_TILE_EN|SCALER_CFG_FMT_MASK);
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
u32 cfg;
- DRM_INFO("%s:degree[%d]flip[0x%x]\n", __func__,
+ DRM_DEBUG("%s:degree[%d]flip[0x%x]\n", __func__,
degree, flip);
cfg = sc_read(SCALER_ROT_CFG);
img_pos.h = pos->w;
}
- DRM_INFO("%s:x[%d]y[%d]w[%d]h[%d]\n",
+ DRM_DEBUG("%s:x[%d]y[%d]w[%d]h[%d]\n",
__func__, pos->x, pos->y, pos->w, pos->h);
/* pixel offset */
SCALER_SRC_H(pos->h));
sc_write(cfg, SCALER_SRC_WH);
- DRM_INFO("%s:swap[%d]hsize[%d]vsize[%d]\n",
+ DRM_DEBUG("%s:swap[%d]hsize[%d]vsize[%d]\n",
__func__, swap, sz->hsize, sz->vsize);
/* span size */
return -EINVAL;
}
- DRM_INFO("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
+ DRM_DEBUG("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
property->prop_id, buf_id, buf_type);
/* Set current buf_id */
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
u32 cfg;
- DRM_INFO("%s:fmt[0x%x]\n", __func__, fmt);
+ DRM_DEBUG("%s:fmt[0x%x]\n", __func__, fmt);
switch (fmt) {
case DRM_FORMAT_RGB565:
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
u32 cfg;
- DRM_INFO("%s:fmt[0x%x]\n", __func__, fmt);
+ DRM_DEBUG("%s:fmt[0x%x]\n", __func__, fmt);
cfg = sc_read(SCALER_DST_CFG);
cfg &= ~(SCALER_CFG_SWAP_MASK|SCALER_CFG_FMT_MASK);
struct tdm_ppdrv *ppdrv = &ctx->ppdrv;
u32 cfg;
- DRM_INFO("%s:degree[%d]flip[0x%x]\n", __func__,
+ DRM_DEBUG("%s:degree[%d]flip[0x%x]\n", __func__,
degree, flip);
cfg = sc_read(SCALER_ROT_CFG);
u32 cfg;
bool itu_709;
- DRM_INFO("%s:sfmt[0x%x]dfmt[0x%x]range[%d]width[%d]\n", __func__,
+ DRM_DEBUG("%s:sfmt[0x%x]dfmt[0x%x]range[%d]width[%d]\n", __func__,
fmt[TDM_OPS_SRC], fmt[TDM_OPS_DST],
sc->range, width);
{
u32 cfg;
- DRM_INFO("%s:hratio[%ld]vratio[%ld]\n",
+ DRM_DEBUG("%s:hratio[%ld]vratio[%ld]\n",
__func__, sc->hratio, sc->vratio);
cfg = sc_read(SCALER_H_RATIO);
u32 phase, tab, cnt = 0;
u32 cfg, val_h, val_l;
- DRM_INFO("%s:coef[%d]\n", __func__, coef);
+ DRM_DEBUG("%s:coef[%d]\n", __func__, coef);
for (phase = 0; phase < SC_COEF_PHASE; phase++) {
for (tab = SC_COEF_H_8T; tab > 0; tab -= 2, cnt++) {
u32 phase, tab, cnt = 0;
u32 cfg, val_h, val_l;
- DRM_INFO("%s:coef[%d]\n", __func__, coef);
+ DRM_DEBUG("%s:coef[%d]\n", __func__, coef);
for (phase = 0; phase < SC_COEF_PHASE; phase++) {
for (tab = SC_COEF_V_4T; tab > 0; tab -= 2, cnt++) {
{
int hcoef, vcoef;
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
hcoef = sc_get_scale_filter(sc->hratio);
vcoef = sc_get_scale_filter(sc->vratio);
static int sc_set_scaler(struct sc_context *ctx, struct sc_scaler *sc,
struct tdm_pos *src, struct tdm_pos *dst)
{
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
if (ctx->rotation) {
sc->hratio = SC_RATIO(src->h, dst->w);
sc->vratio = SC_RATIO(src->h, dst->h);
}
- DRM_INFO("%s:hratio[%ld]vratio[%ld]\n",
+ DRM_DEBUG("%s:hratio[%ld]vratio[%ld]\n",
__func__, sc->hratio, sc->vratio);
sc_set_scaler_coef(ctx, &ctx->sc);
struct tdm_pos img_pos = *pos;
u32 cfg;
- DRM_INFO("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
+ DRM_DEBUG("%s:swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
__func__, swap, pos->x, pos->y, pos->w, pos->h);
if (swap) {
cfg = (SCALER_DST_W(pos->w) | SCALER_DST_H(pos->h));
sc_write(cfg, SCALER_DST_WH);
- DRM_INFO("%s:hsize[%d]vsize[%d]\n",
+ DRM_DEBUG("%s:hsize[%d]vsize[%d]\n",
__func__, sz->hsize, sz->vsize);
/* span size */
property = &c_node->property;
- DRM_INFO("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
+ DRM_DEBUG("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__,
property->prop_id, buf_id, buf_type);
/* Set current buf_id */
u32 cfg;
int *buf_id = ctx->cur_buf_id;
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
#ifdef DEBUG
sc_print_reg(ctx);
return IRQ_HANDLED;
}
- DRM_INFO("%s:src buf_id[%d]dst buf_id[%d]\n", __func__,
+ DRM_DEBUG("%s:src buf_id[%d]dst buf_id[%d]\n", __func__,
buf_id[TDM_OPS_SRC], buf_id[TDM_OPS_DST]);
event_work->ppdrv = ppdrv;
struct sc_scaler *sc = &ctx->sc;
int ret;
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
/* reset h/w block */
ret = sc_sw_reset(ctx);
static int sc_check_prepare(struct sc_context *ctx)
{
- DRM_INFO("%s\n", __func__);
+ DRM_DEBUG("%s\n", __func__);
return 0;
}
u32 cfg;
int ret, i;
- DRM_INFO("%s:cmd[%d]\n", __func__, cmd);
+ DRM_DEBUG("%s:cmd[%d]\n", __func__, cmd);
if (!c_node) {
DRM_ERROR("failed to get c_node.\n");
struct sc_context *ctx = get_sc_context(dev);
u32 cfg;
- DRM_INFO("%s:cmd[%d]\n", __func__, cmd);
+ DRM_DEBUG("%s:cmd[%d]\n", __func__, cmd);
switch (cmd) {
case PP_CMD_M2M: