perf jevents: Add support for HiSilicon CPA PMU aliasing
authorQi Liu <liuqi115@huawei.com>
Thu, 24 Feb 2022 11:11:29 +0000 (19:11 +0800)
committerArnaldo Carvalho de Melo <acme@redhat.com>
Fri, 25 Feb 2022 18:35:07 +0000 (15:35 -0300)
Add support for HiSilicon CPA PMU aliasing.

The kernel driver is in drivers/perf/hisilicon/hisi_uncore_cpa_pmu.c

Reviewed-by: John Garry <john.garry@huawei.com>
Signed-off-by: Qi Liu <liuqi115@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linuxarm@huawei.com
Link: https://lore.kernel.org/r/20220224111129.41416-3-liuqi115@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json [new file with mode: 0644]
tools/perf/pmu-events/jevents.c

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json
new file mode 100644 (file)
index 0000000..7bcddec
--- /dev/null
@@ -0,0 +1,81 @@
+[
+       {
+               "ConfigCode": "0x00",
+               "EventName": "cpa_cycles",
+               "BriefDescription": "count of CPA cycles",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x61",
+               "EventName": "cpa_p1_wr_dat",
+               "BriefDescription": "Number of write ops transmitted by the P1 port",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x62",
+               "EventName": "cpa_p1_rd_dat",
+               "BriefDescription": "Number of read ops transmitted by the P1 port",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x3",
+               "EventName": "cpa_p1_rd_dat_64b",
+               "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x4",
+               "EventName": "cpa_p1_rd_dat_32b",
+               "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0xE1",
+               "EventName": "cpa_p0_wr_dat",
+               "BriefDescription": "Number of write ops transmitted by the P0 port",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0xE2",
+               "EventName": "cpa_p0_rd_dat",
+               "BriefDescription": "Number of read ops transmitted by the P0 port",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x83",
+               "EventName": "cpa_p0_rd_dat_64b",
+               "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "ConfigCode": "0x84",
+               "EventName": "cpa_p0_rd_dat_32b",
+               "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles",
+               "BriefDescription": "Average bandwidth of CPA Port 1",
+               "MetricGroup": "CPA",
+               "MetricName": "cpa_p1_avg_bw",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       },
+       {
+               "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles",
+               "BriefDescription": "Average bandwidth of CPA Port 0",
+               "MetricGroup": "CPA",
+               "MetricName": "cpa_p0_avg_bw",
+               "Compat": "0x00000030",
+               "Unit": "hisi_sicl,cpa"
+       }
+]
index 1a57c3f..159d9ea 100644 (file)
@@ -277,6 +277,7 @@ static struct map {
        { "CPU-M-CF", "cpum_cf" },
        { "CPU-M-SF", "cpum_sf" },
        { "UPI LL", "uncore_upi" },
+       { "hisi_sicl,cpa", "hisi_sicl,cpa"},
        { "hisi_sccl,ddrc", "hisi_sccl,ddrc" },
        { "hisi_sccl,hha", "hisi_sccl,hha" },
        { "hisi_sccl,l3c", "hisi_sccl,l3c" },