Merge tag 'v4.4.35' into tizen

This is the 4.4.35 stable release

Change-Id: I016616a636a1c38e276e4c1c1b4728666b34a253
Signed-off-by: SeokYeon Hwang <syeon.hwang@samsung.com>

diff --cc arch/x86/mm/pat.c
index f299c1b5f6cd7d9d2a81b5b6ecdd95f65072c1d2,6ad687d104cafb360c26cb1110c8fdf45fa43680..b15a083074997707118fbe1106ce37f9b03995bb
--- 1/arch/x86/mm/pat.c
--- 2/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@@ -206,10 -212,7 +217,10 @@@ static void pat_bsp_init(u64 pat
  {
        u64 tmp_pat;
  
-       if (!cpu_has_pat) {
 +      if (__force_pat)
 +              goto force_pat;
 +
+       if (!boot_cpu_has(X86_FEATURE_PAT)) {
                pat_disable("PAT not supported by CPU.");
                return;
        }
@@@ -223,22 -223,14 +231,18 @@@
                return;
        }
  
 +force_pat:
        wrmsrl(MSR_IA32_CR_PAT, pat);
  
- done:
-       pat_init_cache_modes(pat);
+       __init_cache_modes(pat);
  }
  
  static void pat_ap_init(u64 pat)
  {
-       if (!pat_enabled())
-               return;
- 
-       if (!cpu_has_pat) {
 +      if (__force_pat)
 +              goto force_pat;
 +
+       if (!boot_cpu_has(X86_FEATURE_PAT)) {
                /*
                 * If this happens we are on a secondary CPU, but switched to
                 * PAT on the boot CPU. We have no way to undo PAT.
@@@ -284,10 -283,36 +296,42 @@@ static void init_cache_modes(void
                 */
                pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
                      PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
+       }
+ 
+       __init_cache_modes(pat);
  
-       } else if ((c->x86_vendor == X86_VENDOR_INTEL) &&
-                  (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
-                   ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
+       init_cm_done = 1;
+ }
+ 
+ /**
+  * pat_init - Initialize PAT MSR and PAT table
+  *
+  * This function initializes PAT MSR and PAT table with an OS-defined value
+  * to enable additional cache attributes, WC and WT.
+  *
+  * This function must be called on all CPUs using the specific sequence of
+  * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this
+  * procedure for PAT.
+  */
+ void pat_init(void)
+ {
+       u64 pat;
+       struct cpuinfo_x86 *c = &boot_cpu_data;
+ 
++      if (__force_pat) {
++              pr_warn("Force x86 PAT\n");
++              setup_force_cpu_cap(X86_FEATURE_PAT);
++              goto force_pat;
++      }
++
+       if (!pat_enabled()) {
+               init_cache_modes();
+               return;
+       }
+ 
+       if ((c->x86_vendor == X86_VENDOR_INTEL) &&
+           (((c->x86 == 0x6) && (c->x86_model <= 0xd)) ||
+            ((c->x86 == 0xf) && (c->x86_model <= 0x6)))) {
                /*
                 * PAT support with the lower four entries. Intel Pentium 2,
                 * 3, M, and 4 are affected by PAT errata, which makes the

diff --cc include/linux/pci_ids.h
Simple merge