amd: rename GFX110x to NAVI31-33
authorMarek Olšák <marek.olsak@amd.com>
Mon, 4 Sep 2023 17:23:53 +0000 (13:23 -0400)
committerMarge Bot <emma+marge@anholt.net>
Sat, 30 Sep 2023 23:08:47 +0000 (23:08 +0000)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25492>

14 files changed:
docs/drivers/amd/hw/pops.rst
src/amd/addrlib/src/amdgpu_asic_addr.h
src/amd/addrlib/src/core/addrlib.cpp
src/amd/addrlib/src/gfx11/gfx11addrlib.cpp
src/amd/ci/gitlab-ci.yml
src/amd/common/ac_gpu_info.c
src/amd/common/ac_surface_test_common.h
src/amd/common/amd_family.c
src/amd/common/amd_family.h
src/amd/compiler/aco_ir.cpp
src/amd/compiler/tests/helpers.cpp
src/amd/drm-shim/amdgpu_devices.c
src/amd/vulkan/radv_video.c
src/amd/vulkan/winsys/null/radv_null_winsys.c

index b50f301..5941c0f 100644 (file)
@@ -470,7 +470,7 @@ Additional configuration
 These are some largely unresearched options found in the register declarations.
 PAL doesn't use them, so it's unknown if they make any significant difference.
 No effect was found in `nvpro-samples/vk_order_independent_transparency <https://github.com/nvpro-samples/vk_order_independent_transparency>`_
-during testing on GFX9 ``CHIP_RAVEN`` and GFX11 ``CHIP_GFX1100``.
+during testing on GFX9 ``CHIP_RAVEN`` and GFX11 ``CHIP_NAVI31``.
 
 * ``DB_SHADER_CONTROL.EXEC_IF_OVERLAPPED`` on GFX9–10.3.
 * ``PA_SC_BINNER_CNTL_0.BIN_MAPPING_MODE = BIN_MAP_MODE_POPS`` on GFX10+.
index c4b028c..be3aa8a 100644 (file)
@@ -27,7 +27,7 @@
 #define FAMILY_RV      0x8E //# 142 / Raven
 #define FAMILY_NV      0x8F //# 143 / Navi: 10
 #define FAMILY_VGH     0x90 //# 144 / Van Gogh
-#define FAMILY_GFX1100 0x91
+#define FAMILY_NV3     0x91 //# 145 / Navi: 3x
 #define FAMILY_GFX1103 0x94
 #define FAMILY_RMB     0x92 //# 146 / Rembrandt
 #define FAMILY_RPL     0x95 //# 149 / Raphael
@@ -45,7 +45,7 @@
 #define FAMILY_IS_AI(f)      FAMILY_IS(f, AI)
 #define FAMILY_IS_RV(f)      FAMILY_IS(f, RV)
 #define FAMILY_IS_NV(f)      FAMILY_IS(f, NV)
-#define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
+#define FAMILY_IS_NV3(f)     FAMILY_IS(f, NV3)
 #define FAMILY_IS_RMB(f)     FAMILY_IS(f, RMB)
 
 #define AMDGPU_UNKNOWN          0xFF
 
 #define AMDGPU_VANGOGH_RANGE    0x01, 0xFF //# 1 <= x < max
 
-#define AMDGPU_GFX1100_RANGE    0x01, 0x10 //# 01 <= x < 16
-#define AMDGPU_GFX1101_RANGE    0x20, 0xFF //# 32 <= x < 255
-#define AMDGPU_GFX1102_RANGE    0x10, 0x20 //# 16 <= x < 32
-
+#define AMDGPU_NAVI31_RANGE     0x01, 0x10 //# 01 <= x < 16
+#define AMDGPU_NAVI32_RANGE     0x20, 0xFF //# 32 <= x < 255
+#define AMDGPU_NAVI33_RANGE     0x10, 0x20 //# 16 <= x < 32
 #define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128
 #define AMDGPU_GFX1103_R2_RANGE 0x80, 0xFF //# 128 <= x < max
 
 
 #define ASICREV_IS_VANGOGH(r)          ASICREV_IS(r, VANGOGH)
 
-#define ASICREV_IS_GFX1100(r)          ASICREV_IS(r, GFX1100)
-#define ASICREV_IS_GFX1101(r)          ASICREV_IS(r, GFX1101)
-#define ASICREV_IS_GFX1102(r)          ASICREV_IS(r, GFX1102)
+#define ASICREV_IS_NAVI31_P(r)         ASICREV_IS(r, NAVI31)
+#define ASICREV_IS_NAVI32_P(r)         ASICREV_IS(r, NAVI32)
+#define ASICREV_IS_NAVI33_P(r)         ASICREV_IS(r, NAVI33)
 #define ASICREV_IS_GFX1103_R1(r)       ASICREV_IS(r, GFX1103_R1)
 #define ASICREV_IS_GFX1103_R2(r)       ASICREV_IS(r, GFX1103_R2)
 
index 3cf52f4..f0a99b2 100644 (file)
@@ -215,7 +215,7 @@ ADDR_E_RETURNCODE Lib::Create(
                     case FAMILY_MDN:
                         pLib = Gfx10HwlInit(&client);
                         break;
-                    case FAMILY_GFX1100:
+                    case FAMILY_NV3:
                     case FAMILY_GFX1103:
                         pLib = Gfx11HwlInit(&client);
                         break;
index 441d28c..a343e56 100644 (file)
@@ -728,14 +728,14 @@ ChipFamily Gfx11Lib::HwlConvertChipFamily(
 
     switch (chipFamily)
     {
-        case FAMILY_GFX1100:
-            if (ASICREV_IS_GFX1100(chipRevision))
+        case FAMILY_NV3:
+            if (ASICREV_IS_NAVI31_P(chipRevision))
             {
             }
-            if (ASICREV_IS_GFX1101(chipRevision))
+            if (ASICREV_IS_NAVI32_P(chipRevision))
             {
             }
-            if (ASICREV_IS_GFX1102(chipRevision))
+            if (ASICREV_IS_NAVI33_P(chipRevision))
             {
             }
             break;
index 2fe4bc6..8e16f26 100644 (file)
@@ -275,7 +275,7 @@ radv-fossils:
     - AMDGPU_GPU_ID="NAVI21"
       ./install/fossilize-runner.sh
     # RDNA3 (GFX11)
-    - AMDGPU_GPU_ID="GFX1100"
+    - AMDGPU_GPU_ID="NAVI31"
       ./install/fossilize-runner.sh
 
 ############### vkd3d-proton
index f75e0c2..4706edf 100644 (file)
@@ -836,10 +836,10 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
       case FAMILY_MDN:
          identify_chip2(MENDOCINO, RAPHAEL_MENDOCINO);
          break;
-      case FAMILY_GFX1100:
-         identify_chip(GFX1100);
-         identify_chip(GFX1101);
-         identify_chip(GFX1102);
+      case FAMILY_NV3:
+         identify_chip(NAVI31);
+         identify_chip(NAVI32);
+         identify_chip(NAVI33);
          break;
       case FAMILY_GFX1103:
          identify_chip(GFX1103_R1);
@@ -1767,7 +1767,7 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
    fprintf(f, "Multimedia info:\n");
    fprintf(f, "    vce_encode = %u\n", info->ip[AMD_IP_VCE].num_queues);
 
-   if (info->family >= CHIP_GFX1100 || info->family == CHIP_GFX940)
+   if (info->family >= CHIP_NAVI31 || info->family == CHIP_GFX940)
       fprintf(f, "    vcn_unified = %u\n", info->ip[AMD_IP_VCN_UNIFIED].num_queues);
    else {
       fprintf(f, "    vcn_decode = %u\n", info->ip[AMD_IP_VCN_DEC].num_queues);
index de2b4d6..0eae5c3 100644 (file)
@@ -121,9 +121,9 @@ static void init_gfx103(struct radeon_info *info)
 
 static void init_gfx11(struct radeon_info *info)
 {
-   info->family = CHIP_GFX1100;
+   info->family = CHIP_NAVI31;
    info->gfx_level = GFX11;
-   info->family_id = FAMILY_GFX1100;
+   info->family_id = FAMILY_NV3;
    info->chip_external_rev = 0x01;
    info->use_display_dcc_unaligned = false;
    info->use_display_dcc_with_retile_blit = true;
index 9ec41f8..39dda07 100644 (file)
@@ -85,12 +85,12 @@ const char *ac_get_family_name(enum radeon_family family)
       return "REMBRANDT";
    case CHIP_RAPHAEL_MENDOCINO:
       return "RAPHAEL_MENDOCINO";
-   case CHIP_GFX1100:
-      return "GFX1100";
-   case CHIP_GFX1101:
-      return "GFX1101";
-   case CHIP_GFX1102:
-      return "GFX1102";
+   case CHIP_NAVI31:
+      return "NAVI31";
+   case CHIP_NAVI32:
+      return "NAVI32";
+   case CHIP_NAVI33:
+      return "NAVI33";
    case CHIP_GFX1103_R1:
       return "GFX1103_R1";
    case CHIP_GFX1103_R2:
@@ -102,7 +102,7 @@ const char *ac_get_family_name(enum radeon_family family)
 
 enum amd_gfx_level ac_get_gfx_level(enum radeon_family family)
 {
-   if (family >= CHIP_GFX1100)
+   if (family >= CHIP_NAVI31)
       return GFX11;
    if (family >= CHIP_NAVI21)
       return GFX10_3;
@@ -120,8 +120,8 @@ enum amd_gfx_level ac_get_gfx_level(enum radeon_family family)
 
 unsigned ac_get_family_id(enum radeon_family family)
 {
-   if (family >= CHIP_GFX1100)
-      return FAMILY_GFX1100;
+   if (family >= CHIP_NAVI31)
+      return FAMILY_NV3;
    if (family >= CHIP_NAVI21)
       return FAMILY_NV;
    if (family >= CHIP_NAVI10)
@@ -210,11 +210,11 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
       return "gfx1035";
    case CHIP_RAPHAEL_MENDOCINO:
       return "gfx1036";
-   case CHIP_GFX1100:
+   case CHIP_NAVI31:
       return "gfx1100";
-   case CHIP_GFX1101:
+   case CHIP_NAVI32:
       return "gfx1101";
-   case CHIP_GFX1102:
+   case CHIP_NAVI33:
       return "gfx1102";
    case CHIP_GFX1103_R1:
    case CHIP_GFX1103_R2:
index aaca71a..3b7a3d7 100644 (file)
@@ -113,9 +113,10 @@ enum radeon_family
    CHIP_NAVI24,         /* Radeon 6400, 6500 (formerly "Beige Goby") */
    CHIP_REMBRANDT,      /* Ryzen 6000 (formerly "Yellow Carp") */
    CHIP_RAPHAEL_MENDOCINO, /* Ryzen 7000(X), Ryzen 7045, Ryzen 7020 */
-   CHIP_GFX1100,
-   CHIP_GFX1101,
-   CHIP_GFX1102,
+   /* GFX11 (RDNA 3) */
+   CHIP_NAVI31,         /* Radeon 7900 */
+   CHIP_NAVI32,         /* Radeon 7800, 7700 */
+   CHIP_NAVI33,         /* Radeon 7600, 7700S (mobile) */
    CHIP_GFX1103_R1,
    CHIP_GFX1103_R2,
    CHIP_LAST,
index 9982248..df49876 100644 (file)
@@ -89,7 +89,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
       case GFX9: program->family = CHIP_VEGA10; break;
       case GFX10: program->family = CHIP_NAVI10; break;
       case GFX10_3: program->family = CHIP_NAVI21; break;
-      case GFX11: program->family = CHIP_GFX1100; break;
+      case GFX11: program->family = CHIP_NAVI31; break;
       default: program->family = CHIP_UNKNOWN; break;
       }
    } else {
@@ -119,7 +119,7 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
       program->dev.sgpr_limit =
          108; /* includes VCC, which can be treated as s[106-107] on GFX10+ */
 
-      if (family == CHIP_GFX1100 || family == CHIP_GFX1101) {
+      if (family == CHIP_NAVI31 || family == CHIP_NAVI32) {
          program->dev.physical_vgprs = program->wave_size == 32 ? 1536 : 768;
          program->dev.vgpr_alloc_granule = program->wave_size == 32 ? 24 : 12;
       } else {
index 407b1d7..239f4e0 100644 (file)
@@ -498,7 +498,7 @@ get_vk_device(enum amd_gfx_level gfx_level)
    case GFX9: family = CHIP_VEGA10; break;
    case GFX10: family = CHIP_NAVI10; break;
    case GFX10_3: family = CHIP_NAVI21; break;
-   case GFX11: family = CHIP_GFX1100; break;
+   case GFX11: family = CHIP_NAVI31; break;
    default: family = CHIP_UNKNOWN; break;
    }
    return get_vk_device(family);
index 3c8328a..7dd1968 100644 (file)
@@ -1319,8 +1319,8 @@ const struct amdgpu_device amdgpu_devices[] = {
       },
    },
    {
-      .name = "gfx1100",
-      .radeon_family = CHIP_GFX1100,
+      .name = "navi31",
+      .radeon_family = CHIP_NAVI31,
       .hw_ip_gfx = {
          .hw_ip_version_major = 11,
          .hw_ip_version_minor = 0,
index 55cd414..846b9c2 100644 (file)
@@ -125,7 +125,7 @@ si_vid_alloc_stream_handle(struct radv_physical_device *pdevice)
 void
 radv_init_physical_device_decoder(struct radv_physical_device *pdevice)
 {
-   if (pdevice->rad_info.family >= CHIP_GFX1100 || pdevice->rad_info.family == CHIP_GFX940)
+   if (pdevice->rad_info.family >= CHIP_NAVI31 || pdevice->rad_info.family == CHIP_GFX940)
       pdevice->vid_decode_ip = AMD_IP_VCN_UNIFIED;
    else if (radv_has_uvd(pdevice))
       pdevice->vid_decode_ip = AMD_IP_UVD;
@@ -181,9 +181,9 @@ radv_init_physical_device_decoder(struct radv_physical_device *pdevice)
    case CHIP_GFX940:
       pdevice->vid_addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX9;
       break;
-   case CHIP_GFX1100:
-   case CHIP_GFX1101:
-   case CHIP_GFX1102:
+   case CHIP_NAVI31:
+   case CHIP_NAVI32:
+   case CHIP_NAVI33:
    case CHIP_GFX1103_R1:
    case CHIP_GFX1103_R2:
       pdevice->vid_addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
index a9cf5ab..3ef2bc7 100644 (file)
@@ -69,7 +69,7 @@ static const struct {
    [CHIP_VANGOGH] = {0x163F, 8, false},
    [CHIP_NAVI22] = {0x73C0, 8, true},
    [CHIP_NAVI23] = {0x73E0, 8, true},
-   [CHIP_GFX1100] = {0x744C, 24, true},
+   [CHIP_NAVI31] = {0x744C, 24, true},
    /* clang-format on */
 };
 
@@ -88,7 +88,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
          info->family = i;
          info->name = ac_get_family_name(i);
 
-         if (info->family >= CHIP_GFX1100)
+         if (info->family >= CHIP_NAVI31)
             info->gfx_level = GFX11;
          else if (i >= CHIP_NAVI21)
             info->gfx_level = GFX10_3;
@@ -132,7 +132,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
    info->has_3d_cube_border_color_mipmap = true;
    info->has_image_opcodes = true;
 
-   if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101)
+   if (info->family == CHIP_NAVI31 || info->family == CHIP_NAVI32)
       info->num_physical_wave64_vgprs_per_simd = 768;
    else if (info->gfx_level >= GFX10)
       info->num_physical_wave64_vgprs_per_simd = 512;