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perf/x86/intel: Add Elkhart Lake support
author
Kan Liang
<kan.liang@linux.intel.com>
Tue, 28 Jan 2020 18:31:17 +0000
(10:31 -0800)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Thu, 5 Mar 2020 15:43:37 +0000
(16:43 +0100)
[ Upstream commit
eda23b387f6c4bb2971ac7e874a09913f533b22c
]
Elkhart Lake also uses Tremont CPU. From the perspective of Intel PMU,
there is nothing changed compared with Jacobsville.
Share the perf code with Jacobsville.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link:
https://lkml.kernel.org/r/1580236279-35492-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/x86/events/intel/core.c
patch
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diff --git
a/arch/x86/events/intel/core.c
b/arch/x86/events/intel/core.c
index
fcef678
..
c531e3f
100644
(file)
--- a/
arch/x86/events/intel/core.c
+++ b/
arch/x86/events/intel/core.c
@@
-4746,6
+4746,7
@@
__init int intel_pmu_init(void)
break;
case INTEL_FAM6_ATOM_TREMONT_D:
+ case INTEL_FAM6_ATOM_TREMONT:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));