drm/msm/dsi: split clk rate setting and enable

Decouple enable and rate setting.  Prep work to handle bootloader
enabled display.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index eff1a4c..4de771d 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -178,6 +178,8 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
 int msm_dsi_host_init(struct msm_dsi *msm_dsi);
 int msm_dsi_runtime_suspend(struct device *dev);
 int msm_dsi_runtime_resume(struct device *dev);
+int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host);
+int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host);
 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host);
 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host);
 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host);

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 86ad3fd..38d514f 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -168,6 +168,7 @@ static const struct msm_dsi_config sdm845_dsi_cfg = {
 };
 
 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
+       .link_clk_set_rate = dsi_link_clk_set_rate_v2,
        .link_clk_enable = dsi_link_clk_enable_v2,
        .link_clk_disable = dsi_link_clk_disable_v2,
        .clk_init_ver = dsi_clk_init_v2,
@@ -179,6 +180,7 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
 };
 
 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
+       .link_clk_set_rate = dsi_link_clk_set_rate_6g,
        .link_clk_enable = dsi_link_clk_enable_6g,
        .link_clk_disable = dsi_link_clk_disable_6g,
        .clk_init_ver = NULL,
@@ -190,6 +192,7 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
 };
 
 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
+       .link_clk_set_rate = dsi_link_clk_set_rate_6g,
        .link_clk_enable = dsi_link_clk_enable_6g,
        .link_clk_disable = dsi_link_clk_disable_6g,
        .clk_init_ver = dsi_clk_init_6g_v2,

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index 50a37ce..32a9d12 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -35,6 +35,7 @@ struct msm_dsi_config {
 };
 
 struct msm_dsi_host_cfg_ops {
+       int (*link_clk_set_rate)(struct msm_dsi_host *msm_host);
        int (*link_clk_enable)(struct msm_dsi_host *msm_host);
        void (*link_clk_disable)(struct msm_dsi_host *msm_host);
        int (*clk_init_ver)(struct msm_dsi_host *msm_host);

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 458cec8..33c8d6d 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -505,7 +505,7 @@ int msm_dsi_runtime_resume(struct device *dev)
        return dsi_bus_clk_enable(msm_host);
 }
 
-int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
+int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
 {
        int ret;
 
@@ -515,13 +515,13 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
        ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
        ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
        if (msm_host->byte_intf_clk) {
@@ -530,10 +530,18 @@ int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
                if (ret) {
                        pr_err("%s: Failed to set rate byte intf clk, %d\n",
                               __func__, ret);
-                       goto error;
+                       return ret;
                }
        }
 
+       return 0;
+}
+
+
+int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
+{
+       int ret;
+
        ret = clk_prepare_enable(msm_host->esc_clk);
        if (ret) {
                pr_err("%s: Failed to enable dsi esc clk\n", __func__);
@@ -573,7 +581,7 @@ error:
        return ret;
 }
 
-int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
+int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
 {
        int ret;
 
@@ -584,27 +592,34 @@ int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
        ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
        ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
        ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
        ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
        if (ret) {
                pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
-               goto error;
+               return ret;
        }
 
+       return 0;
+}
+
+int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
+{
+       int ret;
+
        ret = clk_prepare_enable(msm_host->byte_clk);
        if (ret) {
                pr_err("%s: Failed to enable dsi byte clk\n", __func__);
@@ -1996,6 +2011,7 @@ int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
         * mdp clock need to be enabled to receive dsi interrupt
         */
        pm_runtime_get_sync(&msm_host->pdev->dev);
+       cfg_hnd->ops->link_clk_set_rate(msm_host);
        cfg_hnd->ops->link_clk_enable(msm_host);
 
        /* TODO: vote for bus bandwidth */
@@ -2344,7 +2360,9 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
        }
 
        pm_runtime_get_sync(&msm_host->pdev->dev);
-       ret = cfg_hnd->ops->link_clk_enable(msm_host);
+       ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
+       if (!ret)
+               ret = cfg_hnd->ops->link_clk_enable(msm_host);
        if (ret) {
                pr_err("%s: failed to enable link clocks. ret=%d\n",
                       __func__, ret);