arm64: dts: imx8: conn: Fix reg order for USB3 controller

Cadence USB3 bindings specify a specific reg order. Adjust DT entries
to match the bindings.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index e62a43591361b360a64f11998bda741708bbc1f0..fc1a5d34382b7e5324517f7d65c00eb19259d75c 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -157,12 +157,10 @@ conn_subsys: bus@5b000000 {
 
                usbotg3_cdns3: usb@5b120000 {
                        compatible = "cdns,usb3";
-                       reg = <0x5b130000 0x10000>,     /* memory area for HOST registers */
-                             <0x5b140000 0x10000>,   /* memory area for DEVICE registers */
-                             <0x5b120000 0x10000>;   /* memory area for OTG/DRD registers */
-                       reg-names = "xhci", "dev", "otg";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
+                       reg = <0x5b120000 0x10000>,   /* memory area for OTG/DRD registers */
+                             <0x5b130000 0x10000>,   /* memory area for HOST registers */
+                             <0x5b140000 0x10000>;   /* memory area for DEVICE registers */
+                       reg-names = "otg", "xhci", "dev";
                        interrupt-parent = <&gic>;
                        interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,