unsigned getNumSuccessors() const { return getNumIndirectDests() + 1; }
- BlockAddress *getBlockAddressForIndirectDest(unsigned DestNo) const;
-
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Instruction *I) {
return (I->getOpcode() == Instruction::CallBr);
MachineBasicBlock *Target = FuncInfo.MBBMap[Dest];
Target->setIsInlineAsmBrIndirectTarget();
Target->setMachineBlockAddressTaken();
+ Target->setLabelMustBeEmitted();
// Don't add duplicate machine successors.
if (Dests.insert(Dest).second)
addSuccessorWithProb(CallBrMBB, Target, BranchProbability::getZero());
OpInfo.CallOperandVal = Call.getArgOperand(ArgNo);
break;
case InlineAsm::isLabel:
- OpInfo.CallOperandVal =
- cast<CallBrInst>(&Call)->getBlockAddressForIndirectDest(LabelNo);
- OpInfo.ConstraintVT =
- getAsmOperandValueType(DL, OpInfo.CallOperandVal->getType())
- .getSimpleVT();
+ OpInfo.CallOperandVal = cast<CallBrInst>(&Call)->getIndirectDest(LabelNo);
++LabelNo;
continue;
case InlineAsm::isClobber:
setName(NameStr);
}
-BlockAddress *
-CallBrInst::getBlockAddressForIndirectDest(unsigned DestNo) const {
- return BlockAddress::get(const_cast<Function *>(getFunction()),
- getIndirectDest(DestNo));
-}
-
CallBrInst::CallBrInst(const CallBrInst &CBI)
: CallBase(CBI.Attrs, CBI.FTy, CBI.getType(), Instruction::CallBr,
OperandTraits<CallBase>::op_end(this) - CBI.getNumOperands(),
// In any sort of PIC mode addresses need to be computed at runtime by
// adding in a register or some sort of table lookup. These can't
- // be used as immediates. BlockAddresses are fine though.
+ // be used as immediates. BlockAddresses and BasicBlocks are fine though.
if ((Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC()) &&
- !isa<BlockAddressSDNode>(Op))
+ !(isa<BlockAddressSDNode>(Op) || isa<BasicBlockSDNode>(Op)))
return;
// If we are in non-pic codegen mode, we allow the address of a global (with
define i32 @test1() {
; CHECK-LABEL: test1:
; CHECK: .word b
-; CHECK-NEXT: .word .Ltmp0
+; CHECK-NEXT: .word .LBB0_2
; CHECK: // %bb.1:
-; CHECK: .Ltmp0:
-; CHECK: .LBB0_2: // %indirect
+; CHECK: .LBB0_2: // Block address taken
entry:
callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "!i"()
to label %cleanup [label %indirect]
if.then:
; CHECK: .word b
-; CHECK-NEXT: .word .Ltmp2
-; CHECK: .Ltmp2:
-; CHECK-NEXT: .LBB1_3: // %if.end6
+; CHECK-NEXT: .word .LBB1_3
+; CHECK: .LBB1_3: // Block address taken
callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "!i"()
to label %if.then4 [label %if.end6]
br i1 %phitmp, label %if.end10, label %if.then9
if.then9:
-; CHECK: .Ltmp4:
-; CHECK-NEXT: .LBB1_5: // %l_yes
+; CHECK: .LBB1_5: // Block address taken
callbr void asm sideeffect "", "!i"()
to label %if.end10 [label %l_yes]
; PPC64LE-NEXT: ld r0, 16(r1)
; PPC64LE-NEXT: mtlr r0
; PPC64LE-NEXT: blr
-; PPC64LE-NEXT: .Ltmp0: # Block address taken
-; PPC64LE-NEXT: .LBB3_2: # %return_early
+; PPC64LE-NEXT: .LBB3_2: # Block address taken
+; PPC64LE-NEXT: # %return_early
+; PPC64LE-NEXT: # Label of block must be emitted
; PPC64LE-NEXT: li r3, 0
; PPC64LE-NEXT: b .LBB3_1
;
; PPC64BE-NEXT: ld r0, 16(r1)
; PPC64BE-NEXT: mtlr r0
; PPC64BE-NEXT: blr
-; PPC64BE-NEXT: .Ltmp0: # Block address taken
-; PPC64BE-NEXT: .LBB3_2: # %return_early
+; PPC64BE-NEXT: .LBB3_2: # Block address taken
+; PPC64BE-NEXT: # %return_early
+; PPC64BE-NEXT: # Label of block must be emitted
; PPC64BE-NEXT: li r3, 0
; PPC64BE-NEXT: b .LBB3_1
entry:
; PPC64LE-NEXT: # %bb.1: # %return
; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
-; PPC64LE-NEXT: .Ltmp1: # Block address taken
-; PPC64LE-NEXT: .LBB4_2: # %return_early
+; PPC64LE-NEXT: .LBB4_2: # Block address taken
+; PPC64LE-NEXT: # %return_early
+; PPC64LE-NEXT: # Label of block must be emitted
; PPC64LE-NEXT: li r3, 0
; PPC64LE-NEXT: extsw r3, r3
; PPC64LE-NEXT: blr
; PPC64BE-NEXT: # %bb.1: # %return
; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
-; PPC64BE-NEXT: .Ltmp1: # Block address taken
-; PPC64BE-NEXT: .LBB4_2: # %return_early
+; PPC64BE-NEXT: .LBB4_2: # Block address taken
+; PPC64BE-NEXT: # %return_early
+; PPC64BE-NEXT: # Label of block must be emitted
; PPC64BE-NEXT: li r3, 0
; PPC64BE-NEXT: extsw r3, r3
; PPC64BE-NEXT: blr
; output from SelectionDAG.
; CHECK: t0: ch = EntryToken
-; CHECK-NEXT: t16: i64 = BlockAddress<@test, %fail> 0
; CHECK-NEXT: t4: i32,ch = CopyFromReg t0, Register:i32 %3
; CHECK-NEXT: t10: i32 = add t4, Constant:i32<1>
; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10
; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
; CHECK-NEXT: t8: i32 = add t2, Constant:i32<4>
; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
-; CHECK-NEXT: t30: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2359305>, Register:i32 %5, TargetConstant:i64<13>, TargetBlockAddress:i64<@test, %fail> 0, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1
+; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2359305>, Register:i32 %5, TargetConstant:i64<13>, BasicBlock:ch<fail 0x{{[0-9a-f]+}}>, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1
define i32 @test(i32 %a, i32 %b, i32 %c) {
entry:
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.4: # %bb17
; CHECK-NEXT: callq widget@PLT
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_5: # %bb18
+; CHECK-NEXT: .LBB0_5: # Block address taken
+; CHECK-NEXT: # %bb18
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movw $0, 14(%rbx)
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: jmp .LBB0_9
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: # %bb.7: # %if.then20.critedge
+; CHECK-NEXT: .LBB0_7: # Block address taken
+; CHECK-NEXT: # %if.then20.critedge
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl j(%rip), %edi
; CHECK-NEXT: movslq %eax, %rcx
; CHECK-NEXT: movl $1, %esi
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: jmp .Ltmp0
+; CHECK-NEXT: jmp .LBB0_1
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: # %bb.1: # %fail
+; CHECK-NEXT: .LBB0_1: # Block address taken
+; CHECK-NEXT: # %fail
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl
entry:
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: jmp .Ltmp1
-; CHECK-NEXT: jmp .Ltmp1
+; CHECK-NEXT: jmp .LBB1_2
+; CHECK-NEXT: jmp .LBB1_2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %normal
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp1: # Block address taken
-; CHECK-NEXT: .LBB1_2: # %fail
+; CHECK-NEXT: .LBB1_2: # Block address taken
+; CHECK-NEXT: # %fail
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl
entry:
; CHECK-NEXT: andl $511, %eax # imm = 0x1FF
; CHECK-NEXT: leaq (%rdx,%rax,8), %rax
; CHECK-NEXT: #APP
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: jmp .Ltmp1
; CHECK-NEXT: .Ltmp2:
-; CHECK-NEXT: jmp .Ltmp3
-; CHECK-NEXT: .Ltmp4:
-; CHECK-NEXT: .zero (-(((.Ltmp5-.Ltmp6)-(.Ltmp4-.Ltmp2))>0))*((.Ltmp5-.Ltmp6)-(.Ltmp4-.Ltmp2)),144
-; CHECK-NEXT: .Ltmp7:
+; CHECK-NEXT: .zero (-(((.Ltmp3-.Ltmp4)-(.Ltmp2-.Ltmp0))>0))*((.Ltmp3-.Ltmp4)-(.Ltmp2-.Ltmp0)),144
+; CHECK-NEXT: .Ltmp5:
entry:
%0 = tail call i64 asm sideeffect "mov %cr3,$0\0A\09", "=r,=*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i64) nonnull @__force_order)
%and.i = and i64 %0, 9223372036854771712
define i32 @test1(i32 %x) {
; CHECK-LABEL: test1:
; CHECK: .quad .Ltmp0
-; CHECK-NEXT: .quad .Ltmp1
-; CHECK: .Ltmp1:
-; CHECK-NEXT: # %bb.1: # %bar
+; CHECK-NEXT: .quad .LBB0_1
+; CHECK: .LBB0_1: # Block address taken
+; CHECK-NEXT: # %bar
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: callq foo
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: # %bb.2: # %baz
; Check the second INLINEASM_BR target block is preceded by the block with the
; second INLINEASM_BR.
-; CHECK: bb.2 (%ir-block.7, machine-block-address-taken, ir-block-address-taken %ir-block.7, inlineasm-br-indirect-target):
+; CHECK: bb.2 (%ir-block.7, machine-block-address-taken, inlineasm-br-indirect-target):
; CHECK-NEXT: predecessors: %bb.1
; Check the first INLINEASM_BR target block is predecessed by the block with
; the first INLINEASM_BR.
-; CHECK: bb.4 (%ir-block.11, machine-block-address-taken, ir-block-address-taken %ir-block.11, inlineasm-br-indirect-target):
+; CHECK: bb.4 (%ir-block.11, machine-block-address-taken, inlineasm-br-indirect-target):
; CHECK-NEXT: predecessors: %bb.0
@.str = private unnamed_addr constant [26 x i8] c"inline asm#1 returned %d\0A\00", align 1
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: jmp .Ltmp0
+; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %normal
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_2: # %abnormal
+; CHECK-NEXT: .LBB0_2: # Block address taken
+; CHECK-NEXT: # %abnormal
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl
entry:
; CHECK-NEXT: #APP
; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: testl %edi, %esi
-; CHECK-NEXT: jne .Ltmp1
+; CHECK-NEXT: jne .LBB1_4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: jmp .LBB1_3
; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: #APP
; CHECK-NEXT: testl %esi, %edi
; CHECK-NEXT: testl %esi, %edi
-; CHECK-NEXT: jne .Ltmp2
+; CHECK-NEXT: jne .LBB1_5
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: .Ltmp2: # Block address taken
-; CHECK-NEXT: .LBB1_5: # %return
+; CHECK-NEXT: .LBB1_5: # Block address taken
+; CHECK-NEXT: # %return
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp1: # Block address taken
-; CHECK-NEXT: .LBB1_4: # %label_true
+; CHECK-NEXT: .LBB1_4: # Block address taken
+; CHECK-NEXT: # %label_true
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movl $-2, %eax
; CHECK-NEXT: jmp .LBB1_5
; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp3: # Block address taken
-; CHECK-NEXT: .LBB2_6: # %indirect
+; CHECK-NEXT: .LBB2_6: # Block address taken
+; CHECK-NEXT: # %indirect
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: jmp .LBB2_5
; CHECK-NEXT: #APP
; CHECK-NEXT: testl %ecx, %ecx
; CHECK-NEXT: testl %edx, %ecx
-; CHECK-NEXT: jne .Ltmp4
+; CHECK-NEXT: jne .LBB3_3
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %asm.fallthrough
; CHECK-NEXT: #APP
; CHECK-NEXT: testl %ecx, %edx
; CHECK-NEXT: testl %ecx, %edx
-; CHECK-NEXT: jne .Ltmp5
+; CHECK-NEXT: jne .LBB3_4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.2: # %asm.fallthrough2
; CHECK-NEXT: addl %edx, %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp4: # Block address taken
-; CHECK-NEXT: .LBB3_3: # %label_true
+; CHECK-NEXT: .LBB3_3: # Block address taken
+; CHECK-NEXT: # %label_true
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $-2, %eax
-; CHECK-NEXT: .Ltmp5: # Block address taken
-; CHECK-NEXT: .LBB3_4: # %return
+; CHECK-NEXT: .LBB3_4: # Block address taken
+; CHECK-NEXT: # %return
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: retl
entry:
%0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "=r,=r,r,!i,!i,~{dirflag},~{fpsr},~{flags}"(i32 %out1)
; CHECK: # %bb.0:
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .Ltmp6: # Block address taken
-; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: .LBB4_1: # Block address taken
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: retl
%1 = call i32 @llvm.read_register.i32(metadata !3)
%2 = callbr i32 asm "", "={esp},!i,{esp},~{dirflag},~{fpsr},~{flags}"(i32 %1)
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movq %rsi, %r14
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_1: # %loop
+; CHECK-NEXT: .LBB0_1: # Block address taken
+; CHECK-NEXT: # %loop
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movq (%r14), %rbx
; CHECK-NEXT: callq foo@PLT
; CHECK-NEXT: movq %rbx, %rdi
; CHECK: # %bb.0:
; CHECK-NEXT: leaq 8(%rdi), %rax
; CHECK-NEXT: #APP
-; CHECK-NEXT: # 8(%rdi) .Ltmp0
+; CHECK-NEXT: # 8(%rdi) .LBB0_1
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: retq
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: .LBB0_1: # Block address taken
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movq $0, -8(%rax)
; CHECK-NEXT: retq
%2 = getelementptr inbounds %struct1, %struct1* %0, i64 0, i32 1
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: jmp .Ltmp0
+; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %normal
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_2: # %fail
+; CHECK-NEXT: .LBB0_2: # Block address taken
+; CHECK-NEXT: # %fail
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl
entry:
; CHECK-NEXT: #APP
; CHECK-EMPTY:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: jmp .Ltmp1
+; CHECK-NEXT: jmp .LBB1_2
; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %normal
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
-; CHECK-NEXT: .Ltmp1: # Block address taken
-; CHECK-NEXT: .LBB1_2: # %fail
+; CHECK-NEXT: .LBB1_2: # Block address taken
+; CHECK-NEXT: # %fail
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retl
entry:
define i32 @test3(i32 %a) {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: .Ltmp2: # Block address taken
-; CHECK-NEXT: .LBB3_1: # %label01
+; CHECK-NEXT: .LBB3_1: # Block address taken
+; CHECK-NEXT: # %label01
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB3_2 Depth 2
; CHECK-NEXT: # Child Loop BB3_3 Depth 3
; CHECK-NEXT: # Child Loop BB3_4 Depth 4
-; CHECK-NEXT: .Ltmp3: # Block address taken
-; CHECK-NEXT: .LBB3_2: # %label02
+; CHECK-NEXT: # Label of block must be emitted
+; CHECK-NEXT: .LBB3_2: # Block address taken
+; CHECK-NEXT: # %label02
; CHECK-NEXT: # Parent Loop BB3_1 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB3_3 Depth 3
; CHECK-NEXT: # Child Loop BB3_4 Depth 4
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: addl $4, {{[0-9]+}}(%esp)
-; CHECK-NEXT: .Ltmp4: # Block address taken
-; CHECK-NEXT: .LBB3_3: # %label03
+; CHECK-NEXT: .LBB3_3: # Block address taken
+; CHECK-NEXT: # %label03
; CHECK-NEXT: # Parent Loop BB3_1 Depth=1
; CHECK-NEXT: # Parent Loop BB3_2 Depth=2
; CHECK-NEXT: # => This Loop Header: Depth=3
; CHECK-NEXT: # Child Loop BB3_4 Depth 4
-; CHECK-NEXT: .Ltmp5: # Block address taken
-; CHECK-NEXT: .LBB3_4: # %label04
+; CHECK-NEXT: # Label of block must be emitted
+; CHECK-NEXT: .LBB3_4: # Block address taken
+; CHECK-NEXT: # %label04
; CHECK-NEXT: # Parent Loop BB3_1 Depth=1
; CHECK-NEXT: # Parent Loop BB3_2 Depth=2
; CHECK-NEXT: # Parent Loop BB3_3 Depth=3
; CHECK-NEXT: # => This Inner Loop Header: Depth=4
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: #APP
-; CHECK-NEXT: jmp .Ltmp2
-; CHECK-NEXT: jmp .Ltmp3
-; CHECK-NEXT: jmp .Ltmp4
+; CHECK-NEXT: jmp .LBB3_1
+; CHECK-NEXT: jmp .LBB3_2
+; CHECK-NEXT: jmp .LBB3_3
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.5: # %normal0
; CHECK-NEXT: # in Loop: Header=BB3_4 Depth=4
; CHECK-NEXT: #APP
-; CHECK-NEXT: jmp .Ltmp2
-; CHECK-NEXT: jmp .Ltmp3
-; CHECK-NEXT: jmp .Ltmp4
-; CHECK-NEXT: jmp .Ltmp5
+; CHECK-NEXT: jmp .LBB3_1
+; CHECK-NEXT: jmp .LBB3_2
+; CHECK-NEXT: jmp .LBB3_3
+; CHECK-NEXT: jmp .LBB3_4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.6: # %normal1
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
-; CHECK-NEXT: ja .Ltmp6
+; CHECK-NEXT: ja .LBB4_3
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.1: # %asm.fallthrough
; CHECK-NEXT: #APP
-; CHECK-NEXT: ja .Ltmp6
+; CHECK-NEXT: ja .LBB4_3
; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: .Ltmp6: # Block address taken
-; CHECK-NEXT: .LBB4_3: # %quux
+; CHECK-NEXT: .LBB4_3: # Block address taken
+; CHECK-NEXT: # %quux
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: retl
entry:
callbr void asm sideeffect "ja $0", "!i,~{dirflag},~{fpsr},~{flags}"()
; CHECK-LABEL: x:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## InlineAsm Start
-; CHECK-NEXT: ## Ltmp0
+; CHECK-NEXT: ## LBB1_1
; CHECK-EMPTY:
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: ## %bb.2: ## %return
; CHECK-NEXT: retl
; CHECK-NEXT: Ltmp0: ## Block address taken
; CHECK-NEXT: LBB1_1: ## %overflow
+; CHECK-NEXT: ## Label of block must be emitted
; CHECK-NEXT: retl
callbr void asm "# ${0:l}\0A", "!i"()
to label %return [label %overflow]
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: callq fn
; CHECK-NEXT: #APP
-; CHECK-NEXT: # jump to .Ltmp0
+; CHECK-NEXT: # jump to .LBB0_4
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: movl $4, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
-; CHECK-NEXT: .Ltmp0: # Block address taken
-; CHECK-NEXT: .LBB0_4: # %two
+; CHECK-NEXT: .LBB0_4: # Block address taken
+; CHECK-NEXT: # %two
+; CHECK-NEXT: # Label of block must be emitted
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: successors: %bb.5(0x80000000), %bb.4(0x00000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.2, [[MOV64rm]], %bb.1
- ; CHECK-NEXT: INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, blockaddress(@test1, %ir-block.bb17.i.i.i), 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
+ ; CHECK-NEXT: INLINEASM_BR &"#$0 $1 $2", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42, 13 /* imm */, 0, 13 /* imm */, %bb.4, 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
; CHECK-NEXT: JMP_1 %bb.5
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.4.bb17.i.i.i (machine-block-address-taken, ir-block-address-taken %ir-block.bb17.i.i.i, inlineasm-br-indirect-target):
+ ; CHECK-NEXT: bb.4.bb17.i.i.i (machine-block-address-taken, inlineasm-br-indirect-target):
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: {{ $}}