np->desc_ver = DESC_VER_3;
np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
if (dma_64bit) {
- if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
+ if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
dev_printk(KERN_INFO, &pci_dev->dev,
"64-bit DMA failed, using 32-bit addressing\n");
else
dev->features |= NETIF_F_HIGHDMA;
- if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
+ if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
dev_printk(KERN_INFO, &pci_dev->dev,
"64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
}
adapter->pci_using_dac = 0;
- mask = DMA_32BIT_MASK;
+ mask = DMA_BIT_MASK(32);
/*
* Consistent DMA mask is set to 32 bit because it cannot be set to
* 35 bits. For P3 also leave it at 32 bits for now. Only the rings
* come off this pool.
*/
- cmask = DMA_32BIT_MASK;
+ cmask = DMA_BIT_MASK(32);
#ifndef CONFIG_IA64
if (revision_id >= NX_P3_B0)
- mask = DMA_39BIT_MASK;
+ mask = DMA_BIT_MASK(39);
else if (revision_id == NX_P2_C1)
- mask = DMA_35BIT_MASK;
+ mask = DMA_BIT_MASK(35);
#endif
if (pci_set_dma_mask(pdev, mask) == 0 &&
pci_set_consistent_dma_mask(pdev, cmask) == 0) {
if (sizeof(dma_addr_t) > 4) {
const u64 required_mask = dma_get_required_mask(dev);
- if (required_mask > DMA_39BIT_MASK &&
+ if (required_mask > DMA_BIT_MASK(39) &&
dma_set_mask(dev, DMA_BIT_MASK(64)) == 0)
ahd->flags |= AHD_64BIT_ADDRESSING;
else if (required_mask > DMA_32BIT_MASK &&
- dma_set_mask(dev, DMA_39BIT_MASK) == 0)
+ dma_set_mask(dev, DMA_BIT_MASK(39)) == 0)
ahd->flags |= AHD_39BIT_ADDRESSING;
else
dma_set_mask(dev, DMA_32BIT_MASK);