drm/msm/dsi: Add PHY configuration for SC7280

The SC7280 SoC uses the 7nm (V4.1) DSI PHY driver with
different enable|disable regulator loads.

Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1624365748-24224-3-git-send-email-rajeevny@codeaurora.org
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index dc7f3e4..e9c6af7 100644 (file)
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -116,9 +116,9 @@ config DRM_MSM_DSI_10NM_PHY
          Choose this option if DSI PHY on SDM845 is used on the platform.
 
 config DRM_MSM_DSI_7NM_PHY
-       bool "Enable DSI 7nm PHY driver in MSM DRM (used by SM8150/SM8250)"
+       bool "Enable DSI 7nm PHY driver in MSM DRM"
        depends on DRM_MSM_DSI
        default y
        help
-         Choose this option if DSI PHY on SM8150/SM8250 is used on the
-         platform.
+         Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on
+         the platform.

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 265530d..cf5c8d0 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -639,6 +639,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
          .data = &dsi_phy_7nm_cfgs },
        { .compatible = "qcom,dsi-phy-7nm-8150",
          .data = &dsi_phy_7nm_8150_cfgs },
+       { .compatible = "qcom,sc7280-dsi-phy-7nm",
+         .data = &dsi_phy_7nm_7280_cfgs },
 #endif
        {}
 };

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index 675f0b4..4beed07 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -51,6 +51,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
 extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
 
 struct msm_dsi_dphy_timing {
        u32 clk_zero;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index bc31039..ae7aab7 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1063,3 +1063,29 @@ const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs = {
        .io_start = { 0xae94400, 0xae96400 },
        .num_dsi_phy = 2,
 };
+
+const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs = {
+       .has_phy_lane = true,
+       .reg_cfg = {
+               .num = 1,
+               .regs = {
+                       {"vdds", 37550, 0},
+               },
+       },
+       .ops = {
+               .enable = dsi_7nm_phy_enable,
+               .disable = dsi_7nm_phy_disable,
+               .pll_init = dsi_pll_7nm_init,
+               .save_pll_state = dsi_7nm_pll_save_state,
+               .restore_pll_state = dsi_7nm_pll_restore_state,
+       },
+       .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+       .max_pll_rate = 5000000000ULL,
+#else
+       .max_pll_rate = ULONG_MAX,
+#endif
+       .io_start = { 0xae94400 },
+       .num_dsi_phy = 1,
+       .quirks = DSI_PHY_7NM_QUIRK_V4_1,
+};