[Hexagon] Remove trailing spaces, NFC

llvm-svn: 318875

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index c262bd6..c9d1822 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1151,7 +1151,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
       EVT RegVT = VA.getLocVT();
       if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
           RegVT == MVT::i32 || RegVT == MVT::f32) {
-        unsigned VReg = 
+        unsigned VReg =
           RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);

diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
index 51ef37f..afd63c6 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -63,7 +63,7 @@ let Namespace = "Hexagon" in {
 
   // Rc - control registers
   class Rc<bits<5> num, string n,
-           list<string> alt = [], list<Register> alias = []> : 
+           list<string> alt = [], list<Register> alias = []> :
         HexagonReg<num, n, alt, alias> {
     let Num = num;
   }
@@ -285,7 +285,7 @@ def HvxQR : RegisterClass<"Hexagon", [VecI1], 512, (add Q0, Q1, Q2, Q3)> {
 }
 
 let Size = 32 in
-def PredRegs : RegisterClass<"Hexagon", 
+def PredRegs : RegisterClass<"Hexagon",
   [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
 
 let Size = 32 in

diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
index d540c09..26f4ac0 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
+++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
@@ -15,5 +15,5 @@ entry:
   ret void
 }
 
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
 attributes #1 = { nounwind readnone }

diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
index ee56e90..7984fee 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
+++ b/llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
@@ -342,7 +342,7 @@ declare float @llvm.hexagon.F2.sfimm.n(i32)
 define float @F2_sfimm_n() {
   %z = call float @llvm.hexagon.F2.sfimm.n(i32 0)
   ret float %z
-} 
+}
 ; CHECK: = sfmake(#0):neg
 
 declare double @llvm.hexagon.F2.dfimm.p(i32)

diff --git a/llvm/test/CodeGen/Hexagon/mulh.ll b/llvm/test/CodeGen/Hexagon/mulh.ll
index 0442e28..013c691 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/mulh.ll
+++ b/llvm/test/CodeGen/Hexagon/mulh.ll
@@ -3,7 +3,7 @@
 target triple = "hexagon"
 
 ; CHECK-LABEL: danny:
-; CHECK: r{{[0-9]+}} = mpy(r0,r1)  
+; CHECK: r{{[0-9]+}} = mpy(r0,r1)
 define i32 @danny(i32 %a0, i32 %a1) {
 b2:
   %v3 = sext i32 %a0 to i64

diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll b/llvm/test/CodeGen/Hexagon/newvaluejump2.ll
index fbc3f29..99c9d1a 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/newvaluejump2.ll
+++ b/llvm/test/CodeGen/Hexagon/newvaluejump2.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
 ; RUN:    | FileCheck %s
-; Check that we generate new value jump, both registers, with one 
+; Check that we generate new value jump, both registers, with one
 ; of the registers as new.
 
 @Reg = common global i32 0, align 4

diff --git a/llvm/test/CodeGen/Hexagon/rdf-copy.ll b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
index ce47cf6..0a6a43a 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/rdf-copy.ll
+++ b/llvm/test/CodeGen/Hexagon/rdf-copy.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
-; 
+;
 ; Check that
 ;     {
 ;         r1 = r0

diff --git a/llvm/test/CodeGen/Hexagon/split-const32-const64.ll b/llvm/test/CodeGen/Hexagon/split-const32-const64.ll
index 9574146..30bc5ed 100644 (file)
--- a/llvm/test/CodeGen/Hexagon/split-const32-const64.ll
+++ b/llvm/test/CodeGen/Hexagon/split-const32-const64.ll
@@ -9,7 +9,7 @@
 @lb = external global i64
 
 ; CHECK-LABEL: test1:
-; CHECK-NOT: CONST32 
+; CHECK-NOT: CONST32
 define void @test1() nounwind {
 entry:
   br label %block

diff --git a/llvm/test/MC/Disassembler/Hexagon/st.txt b/llvm/test/MC/Disassembler/Hexagon/st.txt
index 0f936c2..6f8edbf 100644 (file)
--- a/llvm/test/MC/Disassembler/Hexagon/st.txt
+++ b/llvm/test/MC/Disassembler/Hexagon/st.txt
@@ -243,7 +243,7 @@
 0x03 0x40 0x45 0x85 0xab 0xf5 0x51 0xab
 # CHECK: p3 = r5
 # CHECK-NEXT: if (p3.new) memh(r17++#10) = r21
-0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab 
+0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21
 0x2b 0xf5 0x71 0xab
@@ -326,7 +326,7 @@
 # CHECK-NEXT: if (!p3.new) memw(r17+#84) = #31
 0xab 0xdf 0x91 0x40
 # CHECK: if (p3) memw(r17+#84) = r31
-0xab 0xdf 0x91 0x44 
+0xab 0xdf 0x91 0x44
 # CHECK: if (!p3) memw(r17+#84) = r31
 0x03 0x40 0x45 0x85 0xab 0xdf 0x91 0x42
 # CHECK: p3 = r5

diff --git a/llvm/test/MC/Hexagon/instructions/j.s b/llvm/test/MC/Hexagon/instructions/j.s
index 0a9003b..4a5a8c8 100644 (file)
--- a/llvm/test/MC/Hexagon/instructions/j.s
+++ b/llvm/test/MC/Hexagon/instructions/j.s
@@ -201,6 +201,6 @@ if (r17<=#0) jump:t 0
 
 # Transfer and jump
 # CHECK: 00 d5 09 16
-{ r17 = #21 ; jump 0} 
+{ r17 = #21 ; jump 0 }
 # CHECK: 00 c9 0d 17
 { r17 = r21 ; jump 0 }

diff --git a/llvm/test/MC/Hexagon/instructions/st.s b/llvm/test/MC/Hexagon/instructions/st.s
index 6ea6e9f..3c849a1 100644 (file)
--- a/llvm/test/MC/Hexagon/instructions/st.s
+++ b/llvm/test/MC/Hexagon/instructions/st.s
@@ -287,7 +287,7 @@ if (!p3) memh(r17++#10) = r21
 { p3 = r5
   if (p3.new) memh(r17++#10) = r21 }
 # CHECK: 03 40 45 85
-# CHECK-NEXT: af f5 51 ab 
+# CHECK-NEXT: af f5 51 ab
 { p3 = r5
   if (!p3.new) memh(r17++#10) = r21 }
 # CHECK: 2b f5 71 ab
@@ -390,7 +390,7 @@ if (!p3) memw(r17+#84)=#31
   if (!p3.new) memw(r17+#84)=#31 }
 # CHECK: ab df 91 40
 if (p3) memw(r17+#84) = r31
-# CHECK: ab df 91 44 
+# CHECK: ab df 91 44
 if (!p3) memw(r17+#84) = r31
 # CHECK: 03 40 45 85
 # CHECK-NEXT: ab df 91 42

diff --git a/llvm/test/MC/Hexagon/test.s b/llvm/test/MC/Hexagon/test.s
index 35a395a..62296f6 100644 (file)
--- a/llvm/test/MC/Hexagon/test.s
+++ b/llvm/test/MC/Hexagon/test.s
@@ -1,4 +1,4 @@
 #RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s
 
 { vmem (r0 + #0) = v0
-  r0 = memw(r0) } 
+  r0 = memw(r0) }

diff --git a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
index a81737a..a568bba 100644 (file)
--- a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
+++ b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
@@ -3,7 +3,7 @@
 ; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
 
 
-; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5] 
+; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
 ; DISABLE-NOT: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
 ; DISABLE : = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]