default x2apic cluster mode on platforms
supporting x2apic.
- x86_mrst_timer= [X86-32,APBT]
- Choose timer option for x86 Moorestown MID platform.
+ x86_intel_mid_timer= [X86-32,APBT]
+ Choose timer option for x86 Intel MID platform.
Two valid options are apbt timer only and lapic timer
plus one apbt timer for broadcast timer.
- x86_mrst_timer=apbt_only | lapic_and_apbt
+ x86_intel_mid_timer=apbt_only | lapic_and_apbt
xd= [HW,XT] Original XT pre-IDE (RLL encoded) disks.
xd_geo= See header of drivers/block/xd.c.
X86_SUBARCH_PC = 0,
X86_SUBARCH_LGUEST,
X86_SUBARCH_XEN,
- X86_SUBARCH_MRST,
+ X86_SUBARCH_INTEL_MID,
X86_SUBARCH_CE4100,
X86_NR_SUBARCHS,
};
#include <linux/sfi.h>
#include <linux/pci.h>
-extern int pci_mrst_init(void);
+extern int intel_mid_pci_init(void);
extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
extern int sfi_mrtc_num;
extern struct sfi_rtc_table_entry sfi_mrtc_array[];
* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
* identified via MSRs.
*/
-enum mrst_cpu_type {
- MRST_CPU_CHIP_LINCROFT = 1,
- MRST_CPU_CHIP_PENWELL,
- MRST_CPU_CHIP_CLOVERVIEW,
+enum intel_mid_cpu_type {
+ INTEL_MID_CPU_CHIP_LINCROFT = 1,
+ INTEL_MID_CPU_CHIP_PENWELL,
+ INTEL_MID_CPU_CHIP_CLOVERVIEW,
};
-extern enum mrst_cpu_type __mrst_cpu_chip;
+extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
#ifdef CONFIG_X86_INTEL_MID
-static inline enum mrst_cpu_type mrst_identify_cpu(void)
+static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
{
- return __mrst_cpu_chip;
+ return __intel_mid_cpu_chip;
}
#else /* !CONFIG_X86_INTEL_MID */
-#define mrst_identify_cpu() (0)
+#define intel_mid_identify_cpu() (0)
#endif /* !CONFIG_X86_INTEL_MID */
-enum mrst_timer_options {
- MRST_TIMER_DEFAULT,
- MRST_TIMER_APBT_ONLY,
- MRST_TIMER_LAPIC_APBT,
+enum intel_mid_timer_options {
+ INTEL_MID_TIMER_DEFAULT,
+ INTEL_MID_TIMER_APBT_ONLY,
+ INTEL_MID_TIMER_LAPIC_APBT,
};
enum {
};
extern int mrst_platform_id(void);
-extern enum mrst_timer_options mrst_timer_options;
+extern enum intel_mid_timer_options intel_mid_timer_options;
enum {
MFLD_BOARD_UNKNOWN = 0,
#define MRST_VRTC_MAP_SZ (1024)
/*#define MRST_VRTC_PGOFFSET (0xc00) */
-extern void mrst_rtc_init(void);
+extern void intel_mid_rtc_init(void);
extern int mrst_pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
extern void setup_default_timer_irq(void);
#ifdef CONFIG_X86_INTEL_MID
-extern void x86_mrst_early_setup(void);
+extern void x86_intel_mid_early_setup(void);
#else
-static inline void x86_mrst_early_setup(void) { }
+static inline void x86_intel_mid_early_setup(void) { }
#endif
#ifdef CONFIG_X86_INTEL_CE
adev->num = smp_processor_id();
memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
- if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
+ if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
global_clock_event = &adev->evt;
printk(KERN_DEBUG "%s clockevent registered as global\n",
static __init int apbt_late_init(void)
{
- if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
+ if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
!apb_timer_block_enabled)
return 0;
/* This notifier should be called after workqueue is ready */
}
#ifdef CONFIG_SMP
/* kernel cmdline disable apb timer, so we will use lapic timers */
- if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
+ if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
printk(KERN_INFO "apbt: disabled per cpu timer\n");
return;
}
/* Call the subarch specific early setup function */
switch (boot_params.hdr.hardware_subarch) {
- case X86_SUBARCH_MRST:
- x86_mrst_early_setup();
+ case X86_SUBARCH_INTEL_MID:
+ x86_intel_mid_early_setup();
break;
case X86_SUBARCH_CE4100:
x86_ce4100_early_setup();
return 0;
/* Intel MID platforms don't have ioport rtc */
- if (mrst_identify_cpu())
+ if (intel_mid_identify_cpu())
return -ENODEV;
platform_device_register(&rtc_device);
where, size, value);
}
-static int mrst_pci_irq_enable(struct pci_dev *dev)
+static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
u8 pin;
struct io_apic_irq_attr irq_attr;
return 0;
}
-struct pci_ops pci_mrst_ops = {
+struct pci_ops intel_mid_pci_ops = {
.read = pci_read,
.write = pci_write,
};
/**
- * pci_mrst_init - installs pci_mrst_ops
+ * intel_mid_pci_init - installs intel_mid_pci_ops
*
* Moorestown has an interesting PCI implementation (see above).
* Called when the early platform detection installs it.
*/
-int __init pci_mrst_init(void)
+int __init intel_mid_pci_init(void)
{
printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
pci_mmcfg_late_init();
- pcibios_enable_irq = mrst_pci_irq_enable;
- pci_root_ops = pci_mrst_ops;
+ pcibios_enable_irq = intel_mid_pci_irq_enable;
+ pci_root_ops = intel_mid_pci_ops;
/* Continue with standard init */
return 1;
}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
-static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
+static void __devinit intel_mid_power_off_unused_dev(struct pci_dev *dev)
{
pci_set_power_state(dev, PCI_D3cold);
}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812, mrst_power_off_unused_dev);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801,
+ intel_mid_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809,
+ intel_mid_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C,
+ intel_mid_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0812,
+ intel_mid_power_off_unused_dev);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815,
+ intel_mid_power_off_unused_dev);
/*
* The Firmware should program the Langwell keypad registers to indicate
* in d0i0 during IFWI update. Reboot is needed to work pmu
* driver properly again. After calling this function and IFWI
* update, system is always rebooted as IFWI update function,
- * intel_scu_ipc_medfw_upgrade() is called from mrst_emergency_reboot().
+ * intel_scu_ipc_medfw_upgrade() is called from intel_mid_emergency_reboot().
*/
int pmu_set_devices_in_d0i0(void)
{
*/
writel(pm_ssc->pmu2_states[0], &mid_pmu_cxt->pmu_reg->pm_ssc[0]);
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
writel(pm_ssc->pmu2_states[1],
&mid_pmu_cxt->pmu_reg->pm_ssc[1]);
writel(pm_ssc->pmu2_states[2],
if ((base_class == PCI_BASE_CLASS_DISPLAY) && !sub_class)
index = 1;
- else if ((__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) &&
+ else if ((__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) &&
(base_class == PCI_BASE_CLASS_MULTIMEDIA) &&
(sub_class == ISP_SUB_CLASS))
index = MFLD_ISP_POS;
set_mid_pci_cap(index, PM_SUPPORT);
} else if ((base_class == PCI_BASE_CLASS_MULTIMEDIA) &&
(sub_class == ISP_SUB_CLASS)) {
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
set_mid_pci_log_id(index, (u32)index);
set_mid_pci_cap(index, PM_SUPPORT);
} else if (ss && cap) {
{
pm_ssc->pmu2_states[0] = readl(&mid_pmu_cxt->pmu_reg->pm_sss[0]);
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
pm_ssc->pmu2_states[1] =
readl(&mid_pmu_cxt->pmu_reg->pm_sss[1]);
pm_ssc->pmu2_states[2] =
goto out_err1;
}
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
mid_pmu_cxt->pmu1_max_devs = PMU1_MAX_PENWELL_DEVS;
mid_pmu_cxt->pmu2_max_devs = PMU2_MAX_PENWELL_DEVS;
mid_pmu_cxt->ss_per_reg = 16;
mid_pmu_cxt->pmu_reg = pmu;
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
/* Map the memory of offload_reg */
mid_pmu_cxt->base_addr.offload_reg =
ioremap_nocache(0xffd01ffc, 4);
free_irq(dev->irq, &pmu_sc_irq);
/* Freeing up memory allocated for PMU1 & PMU2 */
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
iounmap(mid_pmu_cxt->base_addr.offload_reg);
mid_pmu_cxt->base_addr.offload_reg = NULL;
}
spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
freq = 100000000 / (spi0_cdiv + 1);
- if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL)
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL)
mrst_spi_paddr = MRST_REGBASE_SPI1;
- else if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+ else if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW)
mrst_spi_paddr = CLV_REGBASE_SPI1;
pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
#include <linux/i2c/tc35876x.h>
/*
* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
- * cmdline option x86_mrst_timer can be used to override the configuration
+ * cmdline option x86_intel_mid_timer can be used to override the configuration
* to prefer one or the other.
* at runtime, there are basically three timer configurations:
* 1. per cpu apbt clock only
* lapic (always-on,ARAT) ------ 150
*/
-__cpuinitdata enum mrst_timer_options mrst_timer_options;
+__cpuinitdata enum intel_mid_timer_options intel_mid_timer_options;
static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
-enum mrst_cpu_type __mrst_cpu_chip;
-EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
+enum intel_mid_cpu_type __intel_mid_cpu_chip;
+EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
int sfi_mtimer_num;
return true;
}
-static void mrst_power_off(void)
+void intel_mid_power_off(void)
{
- if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_LINCROFT)
intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 1);
else {
#ifdef CONFIG_INTEL_MID_OSIP
}
-static void mrst_emergency_reboot(void)
+static void intel_mid_reboot(void)
{
if (intel_scu_ipc_medfw_upgrade()) {
pr_debug("intel_scu_ipc: IFWI upgrade failed...\n");
BUG();
}
- if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT)
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_LINCROFT)
intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0);
else
intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);
return 0;
}
-static unsigned long __init mrst_calibrate_tsc(void)
+static unsigned long __init intel_mid_calibrate_tsc(void)
{
unsigned long flags, fast_calibrate;
- if ((__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) ||
- (__mrst_cpu_chip == MRST_CPU_CHIP_CLOVERVIEW)) {
+ if ((__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) ||
+ (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_CLOVERVIEW)) {
u32 lo, hi, ratio, fsb;
rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
return 0;
}
-static void __init mrst_time_init(void)
+static void __init intel_mid_time_init(void)
{
sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
- switch (mrst_timer_options) {
- case MRST_TIMER_APBT_ONLY:
+ switch (intel_mid_timer_options) {
+ case INTEL_MID_TIMER_APBT_ONLY:
break;
- case MRST_TIMER_LAPIC_APBT:
+ case INTEL_MID_TIMER_LAPIC_APBT:
x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
break;
apbt_time_init();
}
-static void __cpuinit mrst_arch_setup(void)
+static void __cpuinit intel_mid_arch_setup(void)
{
if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
- __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
+ __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL;
else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
- __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+ __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_LINCROFT;
else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x35)
- __mrst_cpu_chip = MRST_CPU_CHIP_CLOVERVIEW;
+ __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW;
else {
pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
boot_cpu_data.x86, boot_cpu_data.x86_model);
- __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
+ __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_LINCROFT;
}
}
/* MID systems don't have i8042 controller */
-static int mrst_i8042_detect(void)
+int intel_mid_i8042_detect(void)
{
return 0;
}
* Moorestown specific x86_init function overrides and early setup
* calls.
*/
-void __init x86_mrst_early_setup(void)
+void __init x86_intel_mid_early_setup(void)
{
x86_init.resources.probe_roms = x86_init_noop;
x86_init.resources.reserve_resources = x86_init_noop;
- x86_init.timers.timer_init = mrst_time_init;
+ x86_init.timers.timer_init = intel_mid_time_init;
x86_init.timers.setup_percpu_clockev = x86_init_noop;
x86_init.irqs.pre_vector_init = x86_init_noop;
- x86_init.oem.arch_setup = mrst_arch_setup;
+ x86_init.oem.arch_setup = intel_mid_arch_setup;
x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
- x86_platform.calibrate_tsc = mrst_calibrate_tsc;
- x86_platform.i8042_detect = mrst_i8042_detect;
- x86_init.timers.wallclock_init = mrst_rtc_init;
- x86_init.pci.init = pci_mrst_init;
+ x86_platform.calibrate_tsc = intel_mid_calibrate_tsc;
+ x86_platform.i8042_detect = intel_mid_i8042_detect;
+ x86_init.timers.wallclock_init = intel_mid_rtc_init;
+ x86_init.pci.init = intel_mid_pci_init;
x86_init.pci.fixup_irqs = x86_init_noop;
legacy_pic = &null_legacy_pic;
/* Moorestown specific power_off/restart method */
- pm_power_off = mrst_power_off;
+ pm_power_off = intel_mid_power_off;
if (mfld_shutdown) {
saved_shutdown = machine_ops.shutdown;
machine_ops.shutdown = mfld_shutdown;
}
- machine_ops.emergency_restart = mrst_emergency_reboot;
+ machine_ops.emergency_restart = intel_mid_reboot;
/* Avoid searching for BIOS MP tables */
x86_init.mpparse.find_smp_config = x86_init_noop;
* if user does not want to use per CPU apb timer, just give it a lower rating
* than local apic timer and skip the late per cpu timer init.
*/
-static inline int __init setup_x86_mrst_timer(char *arg)
+static inline int __init setup_x86_intel_mid_timer(char *arg)
{
if (!arg)
return -EINVAL;
if (strcmp("apbt_only", arg) == 0)
- mrst_timer_options = MRST_TIMER_APBT_ONLY;
+ intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY;
else if (strcmp("lapic_and_apbt", arg) == 0)
- mrst_timer_options = MRST_TIMER_LAPIC_APBT;
+ intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT;
else {
- pr_warning("X86 MRST timer option %s not recognised"
- " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
+ pr_warning("X86 INTEL_MID timer option %s not recognised"
+ " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n",
arg);
return -EINVAL;
}
return 0;
}
-__setup("x86_mrst_timer=", setup_x86_mrst_timer);
+__setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer);
/*
* Parsing GPIO table first, since the DEVS table will need this table
static inline bool mrst_has_msic(void)
{
- return mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL ||
- mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW;
+ return ((intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL) ||
+ (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW));
}
static int msic_scu_status_change(struct notifier_block *nb,
static const struct intel_v4l2_subdev_id *get_v4l2_ids(int *n_subdev)
{
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW) {
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW) {
if (n_subdev)
*n_subdev = ARRAY_SIZE(v4l2_ids_clv);
return v4l2_ids_clv;
for (i = 0; i < num; i++, pentry++) {
int irq = pentry->irq;
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW &&
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW &&
(strcmp(pentry->name, "dis71430m") == 0 ||
strcmp(pentry->name, "ov2720") == 0)) {
/* Skip legacy camera entries which do not exist on this
};
#endif
-static int __init mrst_platform_init(void)
+static int __init intel_mid_platform_init(void)
{
#ifdef CONFIG_SWITCH_MID
int err;
sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW) {
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW) {
/* Add ov8830 driver for detection
* -- FIXME: remove as soon as ov8830 is defined in SFI table */
sfi_handle_i2c_dev(OV8830_BUS, &ov8830_info);
return 0;
}
-arch_initcall(mrst_platform_init);
+arch_initcall(intel_mid_platform_init);
/*
* we will search these buttons in SFI GPIO table (by name)
{
struct cloverview_usb_otg_pdata *pdata;
- if (__mrst_cpu_chip != MRST_CPU_CHIP_CLOVERVIEW)
+ if (__intel_mid_cpu_chip != INTEL_MID_CPU_CHIP_CLOVERVIEW)
return NULL;
pdata = (struct cloverview_usb_otg_pdata *)
return 0;
}
-void __init mrst_rtc_init(void)
+void __init intel_mid_rtc_init(void)
{
unsigned long vrtc_paddr;
};
/* Register the RTC device if appropriate */
-static int __init mrst_device_create(void)
+static int __init intel_mid_device_create(void)
{
- /* No Moorestown, no device */
- if (!mrst_identify_cpu())
+ /* No valid CPU, no device */
+ if (!intel_mid_identify_cpu())
return -ENODEV;
/* No timer, no device */
if (!sfi_mrtc_num)
return platform_device_register(&vrtc_device);
}
-module_init(mrst_device_create);
+module_init(intel_mid_device_create);
{
struct gpadc_info *mgi = data;
- if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW)
mgi->irq_status = ADC1INT_RND;
else
mgi->irq_status = readl(mgi->intr) >> 8 & 0xff;
return -ENODEV;
}
- if (platform == MRST_CPU_CHIP_LINCROFT) {
+ if (platform == INTEL_MID_CPU_CHIP_LINCROFT) {
bytes = 0;
d = 0;
for (i = 0; i < count; i++) {
if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
/* Workaround: values are read as 0 without memcpy_fromio */
memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
- if (platform == MRST_CPU_CHIP_LINCROFT) {
+ if (platform == INTEL_MID_CPU_CHIP_LINCROFT) {
for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
data[nc] = ipc_data_readb(offset);
} else {
int ret;
struct fw_ud param;
- if (platform != MRST_CPU_CHIP_PENWELL)
+ if (platform != INTEL_MID_CPU_CHIP_PENWELL)
return -EINVAL;
ret = copy_from_user(¶m, arg, sizeof(struct fw_ud));
u32 cmdid;
u32 data_off;
- if (platform != MRST_CPU_CHIP_PENWELL)
+ if (platform != INTEL_MID_CPU_CHIP_PENWELL)
return -EINVAL;
if (offset + len > IPC_MIP_MAX_ADDR)
u8 *buf = NULL;
int offset_align, len_align = 0;
- if (platform != MRST_CPU_CHIP_PENWELL)
+ if (platform != INTEL_MID_CPU_CHIP_PENWELL)
return -EINVAL;
if (offset + len > IPC_MIP_MAX_ADDR)
return -EINVAL;
ipc_wbuf[0] = clk;
ipc_wbuf[1] = 0;
if (khz) {
- base_freq = mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW ?
- 38400 : 19200;
+ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_CLOVERVIEW)
+ base_freq = 38400;
+ else
+ base_freq = 19200;
div = base_freq / khz - 1;
if (div >= 3 || (div + 1) * khz != base_freq)
return -EINVAL; /* Allow only exact frequencies */
static int __init intel_scu_ipc_init(void)
{
- platform = mrst_identify_cpu();
+ platform = intel_mid_identify_cpu();
if (platform == 0)
return -ENODEV;
if (cmd != INTEL_SCU_IPC_FW_REVISION_GET && !capable(CAP_SYS_RAWIO))
return -EPERM;
- platform = mrst_identify_cpu();
+ platform = intel_mid_identify_cpu();
switch (cmd) {
case INTEL_SCU_IPC_FW_UPDATE:
{
- if (platform == MRST_CPU_CHIP_LINCROFT) {
+ if (platform == INTEL_MID_CPU_CHIP_LINCROFT) {
u8 *fwbuf = kmalloc(MAX_FW_SIZE, GFP_KERNEL);
if (fwbuf == NULL)
return -ENOMEM;
}
case INTEL_SCU_IPC_MEDFIELD_FW_UPDATE:
{
- if (platform == MRST_CPU_CHIP_PENWELL) {
+ if (platform == INTEL_MID_CPU_CHIP_PENWELL) {
ret = intel_scu_ipc_medfw_prepare(argp);
if (ret < 0) {
char *p;
unsigned long vrtc_date, oshob_date;
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
if (rtc_intr & RTC_AF) {
p = (char *) &vrtc_date;
*(p+1) = vrtc_cmos_read(RTC_DAY_OF_MONTH);
vrtc_cmos_write(min, RTC_MINUTES_ALARM);
vrtc_cmos_write(sec, RTC_SECONDS_ALARM);
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
/* Support for date-field in Alarm using OSHOB
* Since, vRTC doesn't have Alarm-registers for date-fields,
* write date-fields into OSHOB for SCU to sync to MSIC-RTC */
* in Standby. In penwell vRTC is kept on even during standby.
* hence this ipc message need not be sent
*/
- if (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_LINCROFT) {
ret = intel_scu_ipc_simple_command(IPCMSG_VRTC,
IPC_CMD_VRTC_SETALARM);
if (ret)
/* make RTC device wake capable from sleep */
device_init_wakeup(dev, true);
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
retval = intel_scu_ipc_command(IPCMSG_GET_HOBBASE, 0,
NULL, 0, &oshob_base, 1);
if (retval < 0) {
if (is_valid_irq(mrst->irq))
free_irq(mrst->irq, mrst->rtc);
- if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
+ if (__intel_mid_cpu_chip == INTEL_MID_CPU_CHIP_PENWELL) {
if (oshob_addr != NULL)
iounmap(oshob_addr);
}
/* This ifdef can go once the cpu ident stuff is cleaned up in arch */
#if defined(CONFIG_X86_INTEL_MID)
- if (mrst_identify_cpu())
+ if (intel_mid_identify_cpu())
i2c_adap = i2c_get_adapter(2);
else /* Oaktrail uses I2C 1 */
#endif
projects / kernel / kernel-mfld-blackbay.git / commitdiff