gsc1 = &gsc_1;
gsc2 = &gsc_2;
gsc3 = &gsc_3;
+ mshc0 = &dwmmc_0;
+ mshc1 = &dwmmc_1;
+ mshc2 = &dwmmc_2;
+ mshc3 = &dwmmc_3;
+ i2c0 = &i2c_0;
+ i2c1 = &i2c_1;
+ i2c2 = &i2c_2;
+ i2c3 = &i2c_3;
+ i2c4 = &i2c_4;
+ i2c5 = &i2c_5;
+ i2c6 = &i2c_6;
+ i2c7 = &i2c_7;
+ i2c8 = &i2c_8;
};
gic:interrupt-controller@10481000 {
interrupts = <0 42 0>;
};
+ codec@11000000 {
+ compatible = "samsung,mfc-v6";
+ reg = <0x11000000 0x10000>;
+ interrupts = <0 96 0>;
+ };
+
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
};
+ tmu@10060000 {
+ compatible = "samsung,exynos5250-tmu";
+ reg = <0x10060000 0x100>;
+ interrupts = <0 65 0>;
+ };
+
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 54 0>;
};
- i2c@12C60000 {
+ sata@122F0000 {
+ compatible = "samsung,exynos5-sata-ahci";
+ reg = <0x122F0000 0x1ff>;
+ interrupts = <0 115 0>;
+ };
+
+ sata-phy@12170000 {
+ compatible = "samsung,exynos5-sata-phy";
+ reg = <0x12170000 0x1ff>;
+ };
+
+ i2c_0: i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
#size-cells = <0>;
};
- i2c@12C70000 {
+ i2c_1: i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
#size-cells = <0>;
};
- i2c@12C80000 {
+ i2c_2: i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
#size-cells = <0>;
};
- i2c@12C90000 {
+ i2c_3: i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
#size-cells = <0>;
};
- i2c@12CA0000 {
+ i2c_4: i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
#size-cells = <0>;
};
- i2c@12CB0000 {
+ i2c_5: i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
#size-cells = <0>;
};
- i2c@12CC0000 {
+ i2c_6: i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
#size-cells = <0>;
};
- i2c@12CD0000 {
+ i2c_7: i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
#size-cells = <0>;
};
- i2c@12CE0000 {
+ i2c_8: i2c@12CE0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
interrupts = <0 64 0>;
#size-cells = <0>;
};
+ i2c@121D0000 {
+ compatible = "samsung,exynos5-sata-phy-i2c";
+ reg = <0x121D0000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
spi_0: spi@12d20000 {
compatible = "samsung,exynos4210-spi";
reg = <0x12d20000 0x100>;
#size-cells = <0>;
};
- dwmmc0@12200000 {
+ dwmmc_0: dwmmc0@12200000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
#size-cells = <0>;
};
- dwmmc1@12210000 {
+ dwmmc_1: dwmmc1@12210000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
#size-cells = <0>;
};
- dwmmc2@12220000 {
+ dwmmc_2: dwmmc2@12220000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
#size-cells = <0>;
};
- dwmmc3@12230000 {
+ dwmmc_3: dwmmc3@12230000 {
compatible = "samsung,exynos5250-dw-mshc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
SAVE_ITEM(EXYNOS5_VPLL_CON0),
SAVE_ITEM(EXYNOS5_VPLL_CON1),
SAVE_ITEM(EXYNOS5_VPLL_CON2),
+ SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+ SAVE_ITEM(EXYNOS5_PWR_CTRL2),
};
#endif
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
-struct clksrc_clk exynos5_clk_mout_mpll = {
+static struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
/* Core list of CMU_TOP side */
-struct clk *exynos5_clkset_aclk_top_list[] = {
+static struct clk *exynos5_clkset_aclk_top_list[] = {
[0] = &exynos5_clk_mout_mpll_user.clk,
[1] = &exynos5_clk_mout_bpll_user.clk,
};
-struct clksrc_sources exynos5_clkset_aclk = {
+static struct clksrc_sources exynos5_clkset_aclk = {
.sources = exynos5_clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
};
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
};
-struct clk *exynos5_clkset_aclk_333_166_list[] = {
+static struct clk *exynos5_clkset_aclk_333_166_list[] = {
[0] = &exynos5_clk_mout_cpll.clk,
[1] = &exynos5_clk_mout_mpll_user.clk,
};
-struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
.sources = exynos5_clkset_aclk_333_166_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
};
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 24),
}, {
+ .name = "tmu_apbif",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
.name = "rtc",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "sata",
- .devname = "ahci",
+ .devname = "exynos5-sata",
+ .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
- .name = "sata_phy",
+ .name = "sata-phy",
+ .devname = "exynos5-sata-phy",
+ .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 24),
}, {
- .name = "sata_phy_i2c",
+ .name = "i2c",
+ .devname = "exynos5-sata-phy-i2c",
+ .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "mfc",
- .devname = "s5p-mfc",
+ .devname = "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 5),
}, {
+ .name = "dp",
+ .devname = "exynos-dp",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
.name = "jpeg",
.enable = exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 2),
.ctrlbit = (1 << 0),
};
-struct clk *exynos5_clkset_group_list[] = {
+static struct clk *exynos5_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = NULL,
[2] = &exynos5_clk_sclk_hdmi24m,
[9] = &exynos5_clk_mout_cpll.clk,
};
-struct clksrc_sources exynos5_clkset_group = {
+static struct clksrc_sources exynos5_clkset_group = {
.sources = exynos5_clkset_group_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
-struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.clk = {
.name = "sclk_fimd",
.devname = "exynos5-fb.1",
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
}, {
.clk = {
+ .name = "sclk_sata",
+ .devname = "exynos5-sata",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
.name = "sclk_gscl_wrap",
.devname = "s5p-mipi-csis.0",
.enable = exynos5_clksrc_mask_gscl_ctrl,
#define exynos5_clock_resume NULL
#endif
-struct syscore_ops exynos5_clock_syscore_ops = {
+static struct syscore_ops exynos5_clock_syscore_ops = {
.suspend = exynos5_clock_suspend,
.resume = exynos5_clock_resume,
};
#include <asm/suspend.h>
#include <asm/unified.h>
#include <asm/cpuidle.h>
+ #include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pmu.h>
cpu_suspend(0, idle_finisher);
#ifdef CONFIG_SMP
- scu_enable(S5P_VA_SCU);
+ if (!soc_is_exynos5250())
+ scu_enable(S5P_VA_SCU);
#endif
cpu_pm_exit();
return exynos4_enter_core0_aftr(dev, drv, new_index);
}
+ static void __init exynos5_core_down_clk(void)
+ {
+ unsigned int tmp;
+
+ /*
+ * Enable arm clock down (in idle) and set arm divider
+ * ratios in WFI/WFE state.
+ */
+ tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
+ PWR_CTRL1_CORE1_DOWN_RATIO | \
+ PWR_CTRL1_DIV2_DOWN_EN | \
+ PWR_CTRL1_DIV1_DOWN_EN | \
+ PWR_CTRL1_USE_CORE1_WFE | \
+ PWR_CTRL1_USE_CORE0_WFE | \
+ PWR_CTRL1_USE_CORE1_WFI | \
+ PWR_CTRL1_USE_CORE0_WFI;
+ __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+
+ /*
+ * Enable arm clock up (on exiting idle). Set arm divider
+ * ratios when not in idle along with the standby duration
+ * ratios.
+ */
+ tmp = PWR_CTRL2_DIV2_UP_EN | \
+ PWR_CTRL2_DIV1_UP_EN | \
+ PWR_CTRL2_DUR_STANDBY2_VAL | \
+ PWR_CTRL2_DUR_STANDBY1_VAL | \
+ PWR_CTRL2_CORE2_UP_RATIO | \
+ PWR_CTRL2_CORE1_UP_RATIO;
+ __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+ }
+
static int __init exynos4_init_cpuidle(void)
{
int i, max_cpuidle_state, cpu_id;
struct cpuidle_device *device;
struct cpuidle_driver *drv = &exynos4_idle_driver;
+ if (soc_is_exynos5250())
+ exynos5_core_down_clk();
+
/* Setup cpuidle driver */
drv->state_count = (sizeof(exynos4_cpuidle_set) /
sizeof(struct cpuidle_state));
#include <mach/map.h>
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
+ #define S5P_SYSREG(x) (S3C_VA_SYS + (x))
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
#define S5P_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
+#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
/* For EXYNOS5 */
-#define EXYNOS5_USB_CFG S5P_PMUREG(0x0230)
+ #define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234)
+
#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408)
#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C)
*/
#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
#include <linux/serial_core.h>
- #include <linux/of_fdt.h>
+#include <linux/memblock.h>
+ #include <linux/io.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/map.h>
+ #include <mach/regs-pmu.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
+#include <plat/mfc.h>
#include "common.h"
"s3c2440-i2c.1", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
"s3c2440-i2c.2", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
+ "s3c2440-i2c.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
+ "s3c2440-i2c.4", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
+ "s3c2440-i2c.5", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
+ "s3c2440-i2c.6", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
+ "s3c2440-i2c.7", NULL),
OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
"s3c2440-hdmiphy-i2c", NULL),
OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
"exynos4210-spi.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
"exynos4210-spi.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
+ "exynos5-sata", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
+ "exynos5-sata-phy", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
+ "exynos5-sata-phy-i2c", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
"exynos5-hdmi", NULL),
OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
"exynos5-mixer", NULL),
+ OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
+ "exynos-tmu", NULL),
{},
};
-static void __init exynos5250_dt_map_io(void)
+static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
+ "exynos4210-uart.0", NULL),
+ {},
+};
+
+static void __init exynos5_dt_map_io(void)
{
+ unsigned long root = of_get_flat_dt_root();
+
exynos_init_io(NULL, 0);
- s3c24xx_init_clocks(24000000);
+
+ if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
+ s3c24xx_init_clocks(24000000);
}
-static void __init exynos5250_dt_machine_init(void)
+static void __init exynos5_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- exynos5250_auxdata_lookup, NULL);
+ struct device_node *i2c_np;
+ const char *i2c_compat = "samsung,s3c2440-i2c";
+ unsigned int tmp;
+
+ /*
+ * Exynos5's legacy i2c controller and new high speed i2c
+ * controller have muxed interrupt sources. By default the
+ * interrupts for 4-channel HS-I2C controller are enabled.
+ * If node for first four channels of legacy i2c controller
+ * are available then re-configure the interrupts via the
+ * system register.
+ */
+ for_each_compatible_node(i2c_np, NULL, i2c_compat) {
+ if (of_device_is_available(i2c_np)) {
+ if (of_alias_get_id(i2c_np, "i2c") < 4) {
+ tmp = readl(EXYNOS5_SYS_I2C_CFG);
+ writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
+ EXYNOS5_SYS_I2C_CFG);
+ }
+ }
+ }
+
+ if (of_machine_is_compatible("samsung,exynos5250"))
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5250_auxdata_lookup, NULL);
+ else if (of_machine_is_compatible("samsung,exynos5440"))
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5440_auxdata_lookup, NULL);
}
-static char const *exynos5250_dt_compat[] __initdata = {
+static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5440",
NULL
};
+static void __init exynos5_reserve(void)
+{
+ struct s5p_mfc_dt_meminfo mfc_mem;
+
+ /* Reserve memory for MFC only if it's available */
+ mfc_mem.compatible = "samsung,mfc-v6";
+ if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
+ s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
+ mfc_mem.lsize);
+}
+
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.init_irq = exynos5_init_irq,
.smp = smp_ops(exynos_smp_ops),
- .map_io = exynos5250_dt_map_io,
+ .map_io = exynos5_dt_map_io,
.handle_irq = gic_handle_irq,
- .init_machine = exynos5250_dt_machine_init,
+ .init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
.timer = &exynos4_timer,
- .dt_compat = exynos5250_dt_compat,
+ .dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
+ .reserve = exynos5_reserve,
MACHINE_END
SAVE_ITEM(EXYNOS4_VPLL_CON1),
};
+ static struct sleep_save exynos5_sys_save[] = {
+ SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
+ };
+
static struct sleep_save exynos_core_save[] = {
/* SROM side */
SAVE_ITEM(S5P_SROM_BW),
outer_flush_all();
#endif
+ if (soc_is_exynos5250())
+ flush_cache_all();
+
/* issue the standby signal into the pm unit. */
cpu_do_idle();
s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
} else {
+ s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+ if (soc_is_exynos5250())
+ s3c_pm_do_restore(exynos5_sys_save,
+ ARRAY_SIZE(exynos5_sys_save));
+
s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (!soc_is_exynos5250()) {
}
early_wakeup:
+
+ /* Clear SLEEP mode set in INFORM1 */
+ __raw_writel(0x0, S5P_INFORM1);
+
return;
}
projects / profile / ivi / kernel-x86-ivi.git / commitdiff