PD#165090: emmc highspeed, sd highspeed.
Change-Id: Ia3899a29a97e354ec75943e21f7b1e4077f3376e
Signed-off-by: Nan Li <nan.li@amlogic.com>
/dts-v1/;
+#include "partition_mbox_normal.dtsi"
#include "mesong12b.dtsi"
/ {
0xffff 0x0>; /* ending flag */
};
+ bt-dev{
+ compatible = "amlogic, bt-dev";
+ dev_name = "bt-dev";
+ status = "okay";
+ gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+ gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
+ };
+
+ wifi{
+ compatible = "amlogic, aml_wifi";
+ dev_name = "aml_wifi";
+ status = "okay";
+ interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>;
+ irq_trigger_type = "GPIO_IRQ_LOW";
+ power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>;
+ dhd_static_buf; //if use bcm wifi, config dhd_static_buf
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_e_pins>;
+ pwm_config = <&wifi_pwm_conf>;
+ };
+
+ wifi_pwm_conf:wifi_pwm_conf{
+ pwm_channel1_conf {
+ pwms = <&pwm_ef MESON_PWM_0 30040 0>;
+ duty-cycle = <15020>;
+ times = <10>;
+ };
+ pwm_channel2_conf {
+ pwms = <&pwm_ef MESON_PWM_2 30030 0>;
+ duty-cycle = <15015>;
+ times = <12>;
+ };
+ };
+
codec_mm {
compatible = "amlogic, codec, mm";
memory-region = <&codec_mm_cma &codec_mm_reserved>;
*/
tv_bit_mode = <1>;
};
+
+&sd_emmc_c {
+ status = "okay";
+ emmc {
+ caps = "MMC_CAP_8_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED",
+ "MMC_CAP_NONREMOVABLE",
+ /* "MMC_CAP_1_8V_DDR", */
+ "MMC_CAP_HW_RESET",
+ "MMC_CAP_ERASE",
+ "MMC_CAP_CMD23";
+ /* caps2 = "MMC_CAP2_HS200";*/
+ /* "MMC_CAP2_HS400";*/
+ f_min = <400000>;
+ f_max = <200000000>;
+ };
+};
+
&sd_emmc_b {
- status = "disabled";
+ status = "okay";
sd {
caps = "MMC_CAP_4_BIT_DATA",
"MMC_CAP_MMC_HIGHSPEED",
+ "MMC_CAP_SD_HIGHSPEED";
+ f_min = <400000>;
+ f_max = <50000000>;
+ };
+};
+
+&sd_emmc_a {
+ status = "okay";
+ sdio {
+ caps = "MMC_CAP_4_BIT_DATA",
+ "MMC_CAP_MMC_HIGHSPEED",
"MMC_CAP_SD_HIGHSPEED",
"MMC_CAP_NONREMOVABLE",
"MMC_CAP_UHS_SDR12",
"MMC_CAP_UHS_SDR25",
"MMC_CAP_UHS_SDR50",
+ "MMC_CAP_UHS_SDR104",
"MMC_PM_KEEP_POWER",
- "MMC_CAP_NONREMOVABLE"; /**ptm debug */
+ "MMC_CAP_SDIO_IRQ";
f_min = <400000>;
f_max = <200000000>;
};
sd_emmc_c: emmc@ffe07000 {
status = "disabled";
- compatible = "amlogic, meson-mmc-g12a";
+ compatible = "amlogic, meson-mmc-g12b";
reg = <0x0 0xffe07000 0x0 0x800>;
interrupts = <0 191 1>;
pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins";
sd_emmc_b:sd@ffe05000 {
status = "disabled";
- compatible = "amlogic, meson-mmc-g12a";
+ compatible = "amlogic, meson-mmc-g12b";
reg = <0x0 0xffe05000 0x0 0x800>;
interrupts = <0 190 1>;
pinname = "sd";
ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
max_req_size = <0x20000>; /**128KB*/
- gpio_dat3 = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>;
+ gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>;
jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>;
gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
card_type = <5>;
sd_emmc_a:sdio@ffe03000 {
status = "disabled";
- compatible = "amlogic, meson-mmc-g12a";
+ compatible = "amlogic, meson-mmc-g12b";
reg = <0x0 0xffe03000 0x0 0x800>;
interrupts = <0 189 4>;
sdio {
pinname = "sdio";
ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */
- /* max_req_size = <0x20000>; */ /**128KB*/
- max_req_size = <0x400>;
+ max_req_size = <0x20000>; /**128KB*/
card_type = <3>;
/* 3:sdio device(ie:sdio-wifi),
* 4:SD combo (IO+mem) card
*/
- dmode = "pio";
};
};
function = "emmc";
input-enable;
bias-pull-up;
+ drive-strength = <3>;
};
};
function = "emmc";
input-enable;
bias-pull-up;
+ drive-strength = <3>;
};
};
function = "emmc";
input-enable;
bias-pull-down;
+ drive-strength = <3>;
};
};
- sd_clk_cmd_pins:sd_clk_cmd_pins {
- mux {
- groups = "sdcard_cmd_c",
- "sdcard_clk_c";
- function = "sdcard";
- input-enable;
- bias-pull-up;
- };
- };
/* sdemmc portB */
sd_clk_cmd_pins:sd_clk_cmd_pins {
mux {
function = "sdcard";
input-enable;
bias-pull-up;
+ drive-strength = <3>;
};
};
function = "sdcard";
input-enable;
bias-pull-up;
+ drive-strength = <3>;
};
};
sd_1bit_pins:sd_1bit_pins {
function = "sdcard";
input-enable;
bias-pull-up;
+ drive-strength = <3>;
};
};
ao_to_sd_uart_pins:ao_to_sd_uart_pins {
mux {
- groups = "uart_tx_ao_a_c4",
- "uart_rx_ao_a_c5";
+ groups = "uart_ao_tx_a_c3",
+ "uart_ao_rx_a_c2";
function = "uart_ao_a_ee";
bias-pull-up;
input-enable;
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <2 1>;
+ drive-strength = <3>;
};
};
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <1 1 1 1 2 1>;
+ drive-strength = <3>;
};
};
all_nand_pins: all_nand_pins {
};
&pinctrl_aobus {
+ sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins {
+ mux {
+ groups = "GPIOAO_0",
+ "GPIOAO_1";
+ function = "gpio_aobus";
+ };
+ };
+
+ sd_to_ao_uart_pins:sd_to_ao_uart_pins {
+ mux {
+ groups = "uart_ao_tx_a",
+ "uart_ao_rx_a";
+ function = "uart_ao_a";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
remote_pins:remote_pin {
mux {
groups = "remote_input_ao";
.sdmmc.sdr104.core_phase = 2,
};
+static struct meson_mmc_data mmc_data_g12b = {
+ .chip_type = MMC_CHIP_G12B,
+ .port_a_base = 0xffe03000,
+ .port_b_base = 0xffe05000,
+ .port_c_base = 0xffe07000,
+ .pinmux_base = 0xff634400,
+ .clksrc_base = 0xff63c000,
+ .ds_pin_poll = 0x3a,
+ .ds_pin_poll_en = 0x48,
+ .ds_pin_poll_bit = 13,
+ .sdmmc.init.core_phase = 3,
+ .sdmmc.init.tx_phase = 0,
+ .sdmmc.init.rx_phase = 0,
+ .sdmmc.hs.core_phase = 2,
+ .sdmmc.ddr.core_phase = 2,
+ .sdmmc.hs2.core_phase = 3,
+ .sdmmc.hs4.tx_delay = 0,
+ .sdmmc.sd_hs.core_phase = 2,
+ .sdmmc.sdr104.core_phase = 2,
+};
+
static const struct of_device_id meson_mmc_of_match[] = {
{
.compatible = "amlogic, meson-mmc-gxbb",
.compatible = "amlogic, meson-mmc-g12a",
.data = &mmc_data_g12a,
},
+ {
+ .compatible = "amlogic, meson-mmc-g12b",
+ .data = &mmc_data_g12b,
+ },
+
{}
};
MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
if (aml_card_type_sdio(pdata)) {
if ((host->data->chip_type == MMC_CHIP_GXLX)
- || (host->data->chip_type == MMC_CHIP_G12A))
+ || (host->data->chip_type == MMC_CHIP_G12A)
+ || (host->data->chip_type == MMC_CHIP_G12B))
err = _aml_sd_emmc_execute_tuning(mmc, opcode,
&tuning_data, adj_win_start);
else {
#define MODULE_NAME "amlsd"
/* #define CARD_DETECT_IRQ 1 */
#define AML_MMC_TDMA 1
-#define SD_EMMC_DEBUG_BOARD 1
+//#define SD_EMMC_DEBUG_BOARD 1
#if 0
#define A0_GP_CFG0 (0xc8100240)
MMC_CHIP_GXLX = 0x26,
MMC_CHIP_TXHD = 0x27,
MMC_CHIP_G12A = 0x28,
+ MMC_CHIP_G12B = 0x29,
};
struct mmc_phase {