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[RISCV] fix dead code
author
Wu Xinlong
<821408745@qq.com>
Thu, 27 Jan 2022 07:48:25 +0000
(15:48 +0800)
committer
Wu Xinlong
<821408745@qq.com>
Thu, 27 Jan 2022 08:00:01 +0000
(16:00 +0800)
fix dead code mentioned on https://reviews.llvm.org/D98136
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D118323
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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diff --git
a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index
72d91b1
..
01c6bd9
100644
(file)
--- a/
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@
-191,8
+191,8
@@
enum OperandType : unsigned {
OPERAND_SIMM12,
OPERAND_UIMM20,
OPERAND_UIMMLOG2XLEN,
- OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
OPERAND_RVKRNUM,
+ OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.