ARM: meson: enable L2 cache
authorBeniamino Galvani <b.galvani@gmail.com>
Tue, 18 Nov 2014 14:25:41 +0000 (15:25 +0100)
committerCarlo Caione <carlo@caione.org>
Tue, 18 Nov 2014 15:35:01 +0000 (16:35 +0100)
This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
arch/arm/mach-meson/Kconfig
arch/arm/mach-meson/meson.c

index b289e8e..18301dc 100644 (file)
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
        bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
        select GENERIC_IRQ_CHIP
        select ARM_GIC
+       select CACHE_L2X0
 
 if ARCH_MESON
 
index 8f42d8f..5d6affe 100644 (file)
@@ -24,4 +24,6 @@ static const char * const meson_common_board_compat[] = {
 
 DT_MACHINE_START(MESON, "Amlogic Meson platform")
        .dt_compat      = meson_common_board_compat,
+       .l2c_aux_val    = 0,
+       .l2c_aux_mask   = ~0,
 MACHINE_END