return true;
}
-/// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default:
- break;
- case AArch64::ADDSWrx:
- case AArch64::ADDSXrx:
- case AArch64::ADDSXrx64:
- case AArch64::ADDWrx:
- case AArch64::ADDXrx:
- case AArch64::ADDXrx64:
- case AArch64::SUBSWrx:
- case AArch64::SUBSXrx:
- case AArch64::SUBSXrx64:
- case AArch64::SUBWrx:
- case AArch64::SUBXrx:
- case AArch64::SUBXrx64:
- if (MI.getOperand(3).isImm()) {
- unsigned val = MI.getOperand(3).getImm();
- return (val != 0);
- }
- break;
- }
-
- return false;
-}
-
// Return true if this instruction simply sets its single destination register
// to zero. This is equivalent to a register rename of the zero-register.
bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
// Generic predicates.
+// Identify arithmetic instructions with extend.
+def IsArithExtPred : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64,
+ SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>;
+
// Identify arithmetic instructions with shift.
def IsArithShiftPred : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs,
SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>;
// Target predicates.
-// Identify arithmetic and logic instructions with a shifted register.
-def RegShiftedFn : TIIPredicate<"hasShiftedReg",
- MCOpcodeSwitchStatement<
- [MCOpcodeSwitchCase<
- !listconcat(IsArithShiftPred.ValidOpcodes,
- IsLogicShiftPred.ValidOpcodes),
+// Identify arithmetic instructions with an extended register.
+def RegExtendedFn : TIIPredicate<"hasExtendedReg",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ IsArithExtPred.ValidOpcodes,
MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
- MCReturnStatement<FalsePred>>>;
-def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
+ MCReturnStatement<FalsePred>>>;
+def RegExtendedPred : MCSchedPredicate<RegExtendedFn>;
+
+// Identify arithmetic and logic instructions with a shifted register.
+def RegShiftedFn : TIIPredicate<"hasShiftedReg",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ !listconcat(IsArithShiftPred.ValidOpcodes,
+ IsLogicShiftPred.ValidOpcodes),
+ MCReturnStatement<CheckNot<CheckZeroOperand<3>>>>],
+ MCReturnStatement<FalsePred>>>;
+def RegShiftedPred : MCSchedPredicate<RegShiftedFn>;
// Identify a load or store using the register offset addressing mode
// with an extended or scaled register.
-def ScaledIdxFn : TIIPredicate<"isScaledAddr",
- MCOpcodeSwitchStatement<
- [MCOpcodeSwitchCase<
- !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
- IsStoreRegOffsetPred.ValidOpcodes),
- MCReturnStatement<
- CheckAny<[CheckNot<CheckMemExtLSL>,
- CheckMemScaled]>>>],
- MCReturnStatement<FalsePred>>>;
-def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;
+def ScaledIdxFn : TIIPredicate<"isScaledAddr",
+ MCOpcodeSwitchStatement<
+ [MCOpcodeSwitchCase<
+ !listconcat(IsLoadRegOffsetPred.ValidOpcodes,
+ IsStoreRegOffsetPred.ValidOpcodes),
+ MCReturnStatement<
+ CheckAny<[CheckNot<CheckMemExtLSL>,
+ CheckMemScaled]>>>],
+ MCReturnStatement<FalsePred>>>;
+def ScaledIdxPred : MCSchedPredicate<ScaledIdxFn>;