clk: g12a: add bt656 clock [1/1]

PD#SWPL-3359

Problem:
the bt656 clocks were missing

Solution:
1.add bt656 clocks
2.fix several errors for media clocks

Verify:
test passed on u200

Change-Id: Iff69e790c78335930d6b2ea54f7544aca464e1fb
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a.h b/drivers/amlogic/clk/g12a/g12a.h
index e14fc18..db28001 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.h
+++ b/drivers/amlogic/clk/g12a/g12a.h
@@ -117,7 +117,7 @@
 #define HHI_SYS1_PLL_CNTL5        0x394 /* 0xe5 offset in data sheet */
 #define HHI_SYS1_PLL_CNTL6        0x398 /* 0xe6 offset in data sheet */
 /*****************/
-
+#define HHI_BT656_CLK_CNTL             0x3d4 /* 0xf5 offset in data sheet */
 #define HHI_SPICC_CLK_CNTL      0x3dc /* 0xf7 offset in data sheet */
 /* AO registers*/
 #define AO_RTI_PWR_CNTL_REG0 0x10 /* 0x4 offset in data sheet */

diff --git a/drivers/amlogic/clk/g12a/g12a_clk_media.c b/drivers/amlogic/clk/g12a/g12a_clk_media.c
index a4371eb..c737706 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a_clk_media.c
+++ b/drivers/amlogic/clk/g12a/g12a_clk_media.c
@@ -734,13 +734,13 @@ static struct clk_mux vapb_mux = {
 };
 
 static struct clk_hw *vapb_clk_hws[] = {
-       [CLKID_VPU_P0_MUX - CLKID_VPU_P0_MUX]   = &vapb_p0_mux.hw,
-       [CLKID_VPU_P0_DIV - CLKID_VPU_P0_MUX]   = &vapb_p0_div.hw,
-       [CLKID_VPU_P0_GATE - CLKID_VPU_P0_MUX]  = &vapb_p0_gate.hw,
-       [CLKID_VPU_P1_MUX - CLKID_VPU_P0_MUX]   = &vapb_p1_mux.hw,
-       [CLKID_VPU_P1_DIV - CLKID_VPU_P0_MUX]   = &vapb_p1_div.hw,
-       [CLKID_VPU_P1_GATE - CLKID_VPU_P0_MUX]  = &vapb_p1_gate.hw,
-       [CLKID_VPU_MUX - CLKID_VPU_P0_MUX]      = &vapb_mux.hw,
+       [CLKID_VAPB_P0_MUX - CLKID_VAPB_P0_MUX]   = &vapb_p0_mux.hw,
+       [CLKID_VAPB_P0_DIV - CLKID_VAPB_P0_MUX]   = &vapb_p0_div.hw,
+       [CLKID_VAPB_P0_GATE - CLKID_VAPB_P0_MUX]  = &vapb_p0_gate.hw,
+       [CLKID_VAPB_P1_MUX - CLKID_VAPB_P0_MUX]   = &vapb_p1_mux.hw,
+       [CLKID_VAPB_P1_DIV - CLKID_VAPB_P0_MUX]   = &vapb_p1_div.hw,
+       [CLKID_VAPB_P1_GATE - CLKID_VAPB_P0_MUX]  = &vapb_p1_gate.hw,
+       [CLKID_VAPB_MUX - CLKID_VAPB_P0_MUX]      = &vapb_mux.hw,
 };
 
 static struct clk_gate ge2d_gate = {
@@ -768,7 +768,7 @@ static struct clk_mux vpu_clkb_tmp_mux = {
                .name = "vpu_clkb_tmp_mux",
                .ops = &clk_mux_ops,
                .parent_names = vpu_clkb_tmp_parent_names,
-               .num_parents = 8,
+               .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_names),
                .flags = CLK_GET_RATE_NOCACHE,
        },
 };
@@ -822,7 +822,7 @@ static struct clk_gate vpu_clkb_gate = {
        .bit_idx = 8,
        .lock = &clk_lock,
        .hw.init = &(struct clk_init_data) {
-               .name = "vpu_clkb_tmp_gate",
+               .name = "vpu_clkb_gate",
                .ops = &clk_gate_ops,
                .parent_names = (const char *[]){ "vpu_clkb_div" },
                .num_parents = 1,
@@ -943,6 +943,56 @@ static struct clk_hw *vpu_clkc_hws[] = {
        [CLKID_VPU_CLKC_MUX - CLKID_VPU_CLKC_P0_MUX]      = &vpu_clkc_mux.hw,
 };
 
+/* cts_bt656 */
+static const char * const bt656_parent_names[] = { "fclk_div2",
+"fclk_div3", "fclk_div5", "fclk_div7" };
+
+static struct clk_mux bt656_mux = {
+       .reg = (void *)HHI_BT656_CLK_CNTL,
+       .mask = 0x3,
+       .shift = 9,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "bt656_mux",
+               .ops = &clk_mux_ops,
+               .parent_names = bt656_parent_names,
+               .num_parents = ARRAY_SIZE(bt656_parent_names),
+               .flags = CLK_GET_RATE_NOCACHE,
+       },
+};
+
+static struct clk_divider bt656_div = {
+       .reg = (void *)HHI_BT656_CLK_CNTL,
+       .shift = 0,
+       .width = 7,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "bt656_div",
+               .ops = &clk_divider_ops,
+               .parent_names = (const char *[]){ "bt656_mux" },
+               .num_parents = 1,
+               .flags = CLK_GET_RATE_NOCACHE,
+       },
+};
+
+static struct clk_gate bt656_gate = {
+       .reg = (void *)HHI_BT656_CLK_CNTL,
+       .bit_idx = 7,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data) {
+               .name = "bt656_gate",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "bt656_div" },
+               .num_parents = 1,
+               .flags = CLK_GET_RATE_NOCACHE,
+       },
+};
+
+static struct clk_hw *bt656_clk_hws[] = {
+       [0] = &bt656_mux.hw,
+       [1] = &bt656_div.hw,
+       [2] = &bt656_gate.hw,
+};
 
 void meson_g12a_media_init(void)
 {
@@ -1024,6 +1074,22 @@ void meson_g12a_media_init(void)
        vpu_clkc_p1_gate.reg = clk_base + (unsigned long)(vpu_clkc_p1_gate.reg);
        vpu_clkc_mux.reg = clk_base + (unsigned long)(vpu_clkc_mux.reg);
 
+       /* bt656 clk */
+       bt656_mux.reg = clk_base + (unsigned long)(bt656_mux.reg);
+       bt656_div.reg = clk_base + (unsigned long)(bt656_div.reg);
+       bt656_gate.reg = clk_base + (unsigned long)(bt656_gate.reg);
+
+       clks[CLKID_BT656_COMP] = clk_register_composite(NULL,
+               "bt656_composite",
+               bt656_parent_names, ARRAY_SIZE(bt656_parent_names),
+               bt656_clk_hws[0], &clk_mux_ops,
+               bt656_clk_hws[1], &clk_divider_ops,
+               bt656_clk_hws[2], &clk_gate_ops, 0);
+       if (IS_ERR(clks[CLKID_BT656_COMP]))
+               panic("%s: %d clk_register_composite bt656_composite error\n",
+                       __func__, __LINE__);
+
+
        clks[CLKID_DSI_MEAS_COMP] = clk_register_composite(NULL,
                "dsi_meas_composite",
                g12a_meas_parent_names, 8,

diff --git a/include/dt-bindings/clock/amlogic,g12a-clkc.h b/include/dt-bindings/clock/amlogic,g12a-clkc.h
index 8812a2d..5c1f324 100644 (file)
--- a/include/dt-bindings/clock/amlogic,g12a-clkc.h
+++ b/include/dt-bindings/clock/amlogic,g12a-clkc.h
@@ -249,8 +249,12 @@
 #define CLKID_VPU_CLKC_P1_GATE   (CLKID_MEDIA_BASE + 67)
 #define CLKID_VPU_CLKC_P1_COMP   (CLKID_MEDIA_BASE + 68)
 #define CLKID_VPU_CLKC_MUX       (CLKID_MEDIA_BASE + 69)
+#define CLKID_BT656_MUX                (CLKID_MEDIA_BASE + 70)
+#define CLKID_BT656_DIV                (CLKID_MEDIA_BASE + 71)
+#define CLKID_BT656_GATE       (CLKID_MEDIA_BASE + 72)
+#define CLKID_BT656_COMP       (CLKID_MEDIA_BASE + 73)
 
-#define CLKID_MISC_BASE         (CLKID_MEDIA_BASE + 70)
+#define CLKID_MISC_BASE          (CLKID_MEDIA_BASE + 74)
 #define CLKID_SPICC0_MUX         (CLKID_MISC_BASE + 0)
 #define CLKID_SPICC0_DIV         (CLKID_MISC_BASE + 1)
 #define CLKID_SPICC0_GATE        (CLKID_MISC_BASE + 2)
@@ -259,7 +263,7 @@
 #define CLKID_SPICC1_DIV         (CLKID_MISC_BASE + 5)
 #define CLKID_SPICC1_GATE        (CLKID_MISC_BASE + 6)
 #define CLKID_SPICC1_COMP        (CLKID_MISC_BASE + 7)
-#define CLKID_TS_COMP           (CLKID_MISC_BASE + 8)
+#define CLKID_TS_COMP            (CLKID_MISC_BASE + 8)
 
 /*gpio 12M/24M */
 #define CLKID_24M               (CLKID_MISC_BASE + 9)