irqchip/versatile-fpga: Apply clear-mask earlier

Clear its own IRQs before the parent IRQ get enabled, so that the
remaining IRQs do not accidentally interrupt the parent IRQ controller.

This patch also fixes a reboot bug on OX820 SoC, where the remaining
rps-timer IRQ raises a GIC interrupt that is left pending. After that,
the rps-timer IRQ is cleared during driver initialization, and there's
no IRQ left in rps-irq when local_irq_enable() is called, which evokes
an error message "unexpected IRQ trap".

Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT")
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200321133842.2408823-1-mans0n@gorani.run

diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 70e2cff..f138673 100644 (file)
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node,
        if (of_property_read_u32(node, "valid-mask", &valid_mask))
                valid_mask = 0;
 
+       writel(clear_mask, base + IRQ_ENABLE_CLEAR);
+       writel(clear_mask, base + FIQ_ENABLE_CLEAR);
+
        /* Some chips are cascaded from a parent IRQ */
        parent_irq = irq_of_parse_and_map(node, 0);
        if (!parent_irq) {
@@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node,
 
        fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
 
-       writel(clear_mask, base + IRQ_ENABLE_CLEAR);
-       writel(clear_mask, base + FIQ_ENABLE_CLEAR);
-
        /*
         * On Versatile AB/PB, some secondary interrupts have a direct
         * pass-thru to the primary controller for IRQs 20 and 22-31 which need