drm/vc4: hdmi: Switch to blank pixels when disabled

In order to avoid pixels getting stuck in an unflushable FIFO, we need when
we disable the HDMI controller to switch away from getting our pixels from
the pixelvalve and instead use blank pixels, and switch back to the
pixelvalve when we enable the HDMI controller.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fde3efb1ad79f4476a73d310cbba3ec07dc6dabe.1599120059.git-series.maxime@cerno.tech
[hoegeun.kwon: Needed to troubleshoot page flip timed out issue.]
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Change-Id: I497f96e6d9b535d9d173d486fe1829c30093d88f

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1084623..4c10427 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -392,6 +392,12 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 
        HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
+
+       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
+                  VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
+
+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 }
 
 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
@@ -735,6 +741,9 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
                   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
                   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 
+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
+
        if (vc4_encoder->hdmi_monitor) {
                HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
                           HDMI_READ(HDMI_SCHEDULER_CONTROL) |

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 4d01757..c14ee20 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -732,6 +732,9 @@
 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET    BIT(29)
 # define VC4_HD_VID_CTL_VSYNC_LOW              BIT(28)
 # define VC4_HD_VID_CTL_HSYNC_LOW              BIT(27)
+# define VC4_HD_VID_CTL_CLRSYNC                        BIT(24)
+# define VC4_HD_VID_CTL_CLRRGB                 BIT(23)
+# define VC4_HD_VID_CTL_BLANKPIX               BIT(18)
 
 # define VC4_HD_CSC_CTL_ORDER_MASK             VC4_MASK(7, 5)
 # define VC4_HD_CSC_CTL_ORDER_SHIFT            5