+2013-05-29 Sandeep Kumar Singh <Sandeep.Singh2@kpitcummins.com>
+
+ * rx/rx.h (TARGET_CPU_CPP_BUILTINS): Add macros for RX100, RX200,
+ and RX600.
+ * rx/rx.opt: Add macro for rx100 with string rx100 and value
+ RX100.
+ * rx/rx-opts.h (rx_cpu_types): Add new cpu type rx100.
+ * rx/t-rx: Add rx100 under multi library matches option for nofpu
+ option.
+
2013-05-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/57441
{
RX600,
RX610,
- RX200
+ RX200,
+ RX100
};
#endif
loading an immediate into a register. */
extension = ".W";
break;
+ case DFmode:
+ case DImode:
case SFmode:
case SImode:
extension = ".L";
}
if (MEM_P (src) && rx_pid_data_operand (XEXP (src, 0)) == PID_UNENCODED)
- src_template = "(%A1-__pid_base)[%P1]";
+ {
+ gcc_assert (GET_MODE (src) != DImode);
+ gcc_assert (GET_MODE (src) != DFmode);
+
+ src_template = "(%A1 - __pid_base)[%P1]";
+ }
else if (MEM_P (src) && rx_small_data_operand (XEXP (src, 0)))
- src_template = "%%gp(%A1)[%G1]";
+ {
+ gcc_assert (GET_MODE (src) != DImode);
+ gcc_assert (GET_MODE (src) != DFmode);
+
+ src_template = "%%gp(%A1)[%G1]";
+ }
else
src_template = "%1";
if (MEM_P (dest) && rx_small_data_operand (XEXP (dest, 0)))
- dst_template = "%%gp(%A0)[%G0]";
+ {
+ gcc_assert (GET_MODE (dest) != DImode);
+ gcc_assert (GET_MODE (dest) != DFmode);
+
+ dst_template = "%%gp(%A0)[%G0]";
+ }
else
dst_template = "%0";
- sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
- extension, src_template, dst_template);
+ if (GET_MODE (dest) == DImode || GET_MODE (dest) == DFmode)
+ {
+ gcc_assert (! is_movu);
+
+ if (REG_P (src) && REG_P (dest) && (REGNO (dest) == REGNO (src) + 1))
+ sprintf (out_template, "mov.L\t%H1, %H0 | mov.L\t%1, %0");
+ else
+ sprintf (out_template, "mov.L\t%1, %0 | mov.L\t%H1, %H0");
+ }
+ else
+ sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
+ extension, src_template, dst_template);
return out_template;
}
\f
|| lookup_attribute ("gnu_inline", DECL_ATTRIBUTES (callee)) != NULL_TREE;
}
+static bool
+rx_enable_lra (void)
+{
+ return TARGET_ENABLE_LRA || 1;
+}
+
\f
#undef TARGET_NARROW_VOLATILE_BITFIELD
#define TARGET_NARROW_VOLATILE_BITFIELD rx_narrow_volatile_bitfield
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN rx_warn_func_return
+#undef TARGET_LRA_P
+#define TARGET_LRA_P rx_enable_lra
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rx.h"
builtin_define ("__RX610__"); \
builtin_assert ("machine=RX610"); \
} \
- else \
- builtin_assert ("machine=RX600"); \
- \
+ else if (rx_cpu_type == RX100) \
+ { \
+ builtin_define ("__RX100__"); \
+ builtin_assert ("machine=RX100"); \
+ } \
+ else if (rx_cpu_type == RX200) \
+ { \
+ builtin_define ("__RX200__"); \
+ builtin_assert ("machine=RX200"); \
+ } \
+ else if (rx_cpu_type == RX600) \
+ { \
+ builtin_define ("__RX600__"); \
+ builtin_assert ("machine=RX600"); \
+ } \
+ \
if (TARGET_BIG_ENDIAN_DATA) \
builtin_define ("__RX_BIG_ENDIAN__"); \
else \
#undef CC1_SPEC
#define CC1_SPEC "\
%{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \
+ %{mcpu=rx100:%{fpu:%erx100 cpu does not have FPU hardware}} \
%{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}"
#undef STARTFILE_SPEC
;; then all operations on doubles have to be handled by
;; library functions.
(define_mode_iterator register_modes
- [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")])
+ [(SF "") (SI "") (HI "") (QI "")])
(define_constants
[
""
""
)
+
+(define_insn "movdi"
+ [(set:DI (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (match_operand:DI 1 "general_operand" "rmi"))]
+ "TARGET_ENABLE_LRA || 1"
+ { return rx_gen_move_template (operands, false); }
+ [(set_attr "length" "16")
+ (set_attr "timings" "22")]
+)
+
+(define_insn "movdf"
+ [(set:DF (match_operand:DF 0 "nonimmediate_operand" "=rm")
+ (match_operand:DF 1 "general_operand" "rmi"))]
+ "TARGET_ENABLE_LRA || 1"
+ { return rx_gen_move_template (operands, false); }
+ [(set_attr "length" "16")
+ (set_attr "timings" "22")]
+)
EnumValue
Enum(rx_cpu_types) String(rx600) Value(RX600)
+EnumValue
+Enum(rx_cpu_types) String(rx100) Value(RX100)
+
;---------------------------------------------------
mbig-endian-data
mrx-abi
Target RejectNegative Report InverseMask(GCC_ABI)
Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default.
+
+mlra
+Target Report Mask(ENABLE_LRA)
+Enable the use of the LRA register allocator.
# MULTILIB_OPTIONS += mgcc-abi
# MULTILIB_DIRNAMES += gcc-abi
-MULTILIB_MATCHES = nofpu=mnofpu nofpu=mcpu?rx200
+MULTILIB_MATCHES = nofpu=mnofpu nofpu=mcpu?rx200 nofpu=mcpu?rx100
MULTILIB_EXCEPTIONS =
MULTILIB_EXTRA_OPTS =