the baremetal builds are currently broken because the shift ends up in the wrong
representation if the mode is SImode and the shift amount if 31. To fix this
create the rtx constant with an explicit mode so the backend passes know which
representation it needs to take.
gcc/ChangeLog:
* config/aarch64/aarch64.md (tbranch_<code><mode>3): Use gen_int_mode.
{
rtx bitvalue = gen_reg_rtx (<ZEROM>mode);
rtx reg = gen_lowpart (<ZEROM>mode, operands[0]);
- rtx val = GEN_INT (1UL << UINTVAL (operands[1]));
+ rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), <MODE>mode);
emit_insn (gen_and<zerom>3 (bitvalue, reg, val));
operands[1] = const0_rtx;
operands[0] = aarch64_gen_compare_reg (<CODE>, bitvalue,