/// supplied allocator.
///
/// This function can be overridden in a derive class.
- template<typename Ty>
- static Ty *create(BumpPtrAllocator &Allocator, MachineFunction &MF) {
- return new (Allocator.Allocate<Ty>()) Ty(MF);
+ template <typename FuncInfoTy, typename SubtargetTy = TargetSubtargetInfo>
+ static FuncInfoTy *create(BumpPtrAllocator &Allocator, const Function &F,
+ const SubtargetTy *STI) {
+ return new (Allocator.Allocate<FuncInfoTy>()) FuncInfoTy(F, STI);
}
template <typename Ty>
///
template<typename Ty>
Ty *getInfo() {
- if (!MFInfo)
- MFInfo = Ty::template create<Ty>(Allocator, *this);
return static_cast<Ty*>(MFInfo);
}
template<typename Ty>
const Ty *getInfo() const {
- return const_cast<MachineFunction*>(this)->getInfo<Ty>();
+ return static_cast<const Ty *>(MFInfo);
}
template <typename Ty> Ty *cloneInfo(const Ty &Old) {
return static_cast<Ty *>(MFInfo);
}
+ /// Initialize the target specific MachineFunctionInfo
+ void initTargetMachineFunctionInfo(const TargetSubtargetInfo &STI);
+
MachineFunctionInfo *cloneInfoFrom(
const MachineFunction &OrigMF,
const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) {
#include "llvm/ADT/Triple.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/PassManager.h"
+#include "llvm/Support/Allocator.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/PGOOptions.h"
}
using legacy::PassManagerBase;
+struct MachineFunctionInfo;
namespace yaml {
struct MachineFunctionInfo;
}
return nullptr;
}
+ /// Create the target's instance of MachineFunctionInfo
+ virtual MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return nullptr;
+ }
+
/// Allocate and return a default initialized instance of the YAML
/// representation for the MachineFunctionInfo.
virtual yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const {
RegInfo = nullptr;
MFInfo = nullptr;
+
// We can realign the stack if the target supports it and the user hasn't
// explicitly asked us not to.
bool CanRealignSP = STI->getFrameLowering()->isStackRealignable() &&
PSVManager = std::make_unique<PseudoSourceValueManager>(getTarget());
}
+void MachineFunction::initTargetMachineFunctionInfo(
+ const TargetSubtargetInfo &STI) {
+ assert(!MFInfo && "MachineFunctionInfo already set");
+ MFInfo = Target.createMachineFunctionInfo(Allocator, F, &STI);
+}
+
MachineFunction::~MachineFunction() {
clear();
}
// No pre-existing machine function, create a new one.
const TargetSubtargetInfo &STI = *TM.getSubtargetImpl(F);
MF = new MachineFunction(F, TM, STI, NextFnNum++, *this);
+ MF->initTargetMachineFunctionInfo(STI);
// Update the set entry.
I.first->second.reset(MF);
} else {
LLVM_DEBUG(dbgs() << "Resetting: " << MF.getName() << '\n');
++NumFunctionsReset;
MF.reset();
+ MF.initTargetMachineFunctionInfo(MF.getSubtarget());
+
if (EmitFallbackDiag) {
const Function &F = MF.getFunction();
DiagnosticInfoISelFallback DiagFallback(F);
return Key.equals_insensitive("b_key");
}
-AArch64FunctionInfo::AArch64FunctionInfo(MachineFunction &MF) {
- const Function &F = MF.getFunction();
- const AArch64Subtarget &STI = MF.getSubtarget<AArch64Subtarget>();
-
+AArch64FunctionInfo::AArch64FunctionInfo(const Function &F,
+ const AArch64Subtarget *STI) {
// If we already know that the function doesn't have a redzone, set
// HasRedZone here.
if (F.hasFnAttribute(Attribute::NoRedZone))
HasRedZone = false;
std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F);
- SignWithBKey = ShouldSignWithBKey(F, STI);
+ SignWithBKey = ShouldSignWithBKey(F, *STI);
// TODO: skip functions that have no instrumented allocas for optimization
IsMTETagged = F.hasFnAttribute(Attribute::SanitizeMemTag);
struct AArch64FunctionInfo;
} // end namespace yaml
+class AArch64Subtarget;
class MachineInstr;
/// AArch64FunctionInfo - This class is derived from MachineFunctionInfo and
mutable std::optional<bool> NeedsAsyncDwarfUnwindInfo;
public:
- explicit AArch64FunctionInfo(MachineFunction &MF);
+ AArch64FunctionInfo(const Function &F, const AArch64Subtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
addPass(createUnpackMachineBundles(nullptr));
}
+MachineFunctionInfo *AArch64TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return AArch64FunctionInfo::create<AArch64FunctionInfo>(
+ Allocator, F, static_cast<const AArch64Subtarget *>(STI));
+}
+
yaml::MachineFunctionInfo *
AArch64TargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::AArch64FunctionInfo();
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction &MF) const override;
using namespace llvm;
-AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF)
- : IsEntryFunction(AMDGPU::isEntryFunctionCC(
- MF.getFunction().getCallingConv())),
+AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F,
+ const AMDGPUSubtarget &ST)
+ : IsEntryFunction(AMDGPU::isEntryFunctionCC(F.getCallingConv())),
IsModuleEntryFunction(
- AMDGPU::isModuleEntryFunctionCC(MF.getFunction().getCallingConv())),
- NoSignedZerosFPMath(MF.getTarget().Options.NoSignedZerosFPMath) {
- const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(MF);
+ AMDGPU::isModuleEntryFunctionCC(F.getCallingConv())),
+ NoSignedZerosFPMath(false) {
// FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset,
// except reserved size is not correctly aligned.
- const Function &F = MF.getFunction();
Attribute MemBoundAttr = F.getFnAttribute("amdgpu-memory-bound");
MemoryBound = MemBoundAttr.getValueAsBool();
CallingConv::ID CC = F.getCallingConv();
if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL)
ExplicitKernArgSize = ST.getExplicitKernArgSize(F, MaxKernArgAlign);
+
+ // FIXME: Shouldn't be target specific
+ Attribute NSZAttr = F.getFnAttribute("no-signed-zeros-fp-math");
+ NoSignedZerosFPMath =
+ NSZAttr.isStringAttribute() && NSZAttr.getValueAsString() == "true";
}
unsigned AMDGPUMachineFunction::allocateLDSGlobal(const DataLayout &DL,
namespace llvm {
+class AMDGPUSubtarget;
+class GCNSubtarget;
+
class AMDGPUMachineFunction : public MachineFunctionInfo {
/// A map to keep track of local memory objects and their offsets within the
/// local memory space.
bool WaveLimiter = false;
public:
- AMDGPUMachineFunction(const MachineFunction &MF);
+ AMDGPUMachineFunction(const Function &F, const AMDGPUSubtarget &ST);
uint64_t getExplicitKernArgSize() const {
return ExplicitKernArgSize;
#include "GCNSchedStrategy.h"
#include "GCNVOPDUtils.h"
#include "R600.h"
+#include "R600MachineFunctionInfo.h"
#include "R600TargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "SIMachineScheduler.h"
return DAG;
}
+MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return R600MachineFunctionInfo::create<R600MachineFunctionInfo>(
+ Allocator, F, static_cast<const R600Subtarget *>(STI));
+}
+
//===----------------------------------------------------------------------===//
// GCN Pass Setup
//===----------------------------------------------------------------------===//
return new GCNPassConfig(*this, PM);
}
+MachineFunctionInfo *GCNTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SIMachineFunctionInfo::create<SIMachineFunctionInfo>(
+ Allocator, F, static_cast<const GCNSubtarget *>(STI));
+}
+
yaml::MachineFunctionInfo *GCNTargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::SIMachineFunctionInfo();
}
GCNTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
return new yaml::SIMachineFunctionInfo(
- *MFI, *MF.getSubtarget().getRegisterInfo(), MF);
+ *MFI, *MF.getSubtarget<GCNSubtarget>().getRegisterInfo(), MF);
}
bool GCNTargetMachine::parseMachineFunctionInfo(
return true;
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
convertFuncInfoToYAML(const MachineFunction &MF) const override;
//===----------------------------------------------------------------------===//
#include "R600MachineFunctionInfo.h"
+#include "R600Subtarget.h"
using namespace llvm;
-R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF)
- : AMDGPUMachineFunction(MF) { }
+R600MachineFunctionInfo::R600MachineFunctionInfo(const Function &F,
+ const R600Subtarget *STI)
+ : AMDGPUMachineFunction(F, *STI) {}
namespace llvm {
+class R600Subtarget;
+
class R600MachineFunctionInfo final : public AMDGPUMachineFunction {
public:
- R600MachineFunctionInfo(const MachineFunction &MF);
+ R600MachineFunctionInfo(const Function &F, const R600Subtarget *STI);
unsigned CFStackSize;
};
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool isMachineVerifierClean() const override { return false; }
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm
using namespace llvm;
-SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
- : AMDGPUMachineFunction(MF),
- Mode(MF.getFunction()),
- GWSResourcePSV(static_cast<const AMDGPUTargetMachine &>(MF.getTarget())),
+const GCNTargetMachine &getTM(const GCNSubtarget *STI) {
+ const SITargetLowering *TLI = STI->getTargetLowering();
+ return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
+}
+
+SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
+ const GCNSubtarget *STI)
+ : AMDGPUMachineFunction(F, *STI),
+ Mode(F),
+ GWSResourcePSV(getTM(STI)),
PrivateSegmentBuffer(false),
DispatchPtr(false),
QueuePtr(false),
ImplicitArgPtr(false),
GITPtrHigh(0xffffffff),
HighBitsOf32BitAddress(0) {
- const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
- const Function &F = MF.getFunction();
+ const GCNSubtarget &ST = *static_cast<const GCNSubtarget *>(STI);
FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
WavesPerEU = ST.getWavesPerEU(F);
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const;
public:
- SIMachineFunctionInfo(const MachineFunction &MF);
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI) = default;
+ SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
unsigned ReturnStackOffset;
public:
- ARCFunctionInfo()
- : ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
- ReturnStackOffset(-1U), MaxCallStackReq(0) {}
-
- explicit ARCFunctionInfo(MachineFunction &MF)
+ explicit ARCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: ReturnStackOffsetSet(false), VarArgsFrameIndex(0),
ReturnStackOffset(-1U), MaxCallStackReq(0) {}
~ARCFunctionInfo() {}
addPass(createARCOptAddrMode());
}
+MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return ARCFunctionInfo::create<ARCFunctionInfo>(Allocator, F, STI);
+}
+
// Force static initialization.
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
void ARMFunctionInfo::anchor() {}
-static bool GetBranchTargetEnforcement(MachineFunction &MF) {
- const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
- if (!Subtarget.isMClass() || !Subtarget.hasV7Ops())
+static bool GetBranchTargetEnforcement(const Function &F,
+ const ARMSubtarget *Subtarget) {
+ if (!Subtarget->isMClass() || !Subtarget->hasV7Ops())
return false;
- const Function &F = MF.getFunction();
if (!F.hasFnAttribute("branch-target-enforcement")) {
if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
F.getParent()->getModuleFlag("branch-target-enforcement")))
return {true, false};
}
-ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
- : isThumb(MF.getSubtarget<ARMSubtarget>().isThumb()),
- hasThumb2(MF.getSubtarget<ARMSubtarget>().hasThumb2()),
- IsCmseNSEntry(MF.getFunction().hasFnAttribute("cmse_nonsecure_entry")),
- IsCmseNSCall(MF.getFunction().hasFnAttribute("cmse_nonsecure_call")),
- BranchTargetEnforcement(GetBranchTargetEnforcement(MF)) {
-
- const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
- if (Subtarget.isMClass() && Subtarget.hasV7Ops())
- std::tie(SignReturnAddress, SignReturnAddressAll) =
- GetSignReturnAddress(MF.getFunction());
+ARMFunctionInfo::ARMFunctionInfo(const Function &F,
+ const ARMSubtarget *Subtarget)
+ : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()),
+ IsCmseNSEntry(F.hasFnAttribute("cmse_nonsecure_entry")),
+ IsCmseNSCall(F.hasFnAttribute("cmse_nonsecure_call")),
+ BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) {
+ if (Subtarget->isMClass() && Subtarget->hasV7Ops())
+ std::tie(SignReturnAddress, SignReturnAddressAll) = GetSignReturnAddress(F);
}
MachineFunctionInfo *
namespace llvm {
+class ARMSubtarget;
+
/// ARMFunctionInfo - This class is derived from MachineFunctionInfo and
/// contains private ARM-specific information for each MachineFunction.
class ARMFunctionInfo : public MachineFunctionInfo {
public:
ARMFunctionInfo() = default;
- explicit ARMFunctionInfo(MachineFunction &MF);
+ explicit ARMFunctionInfo(const Function &F, const ARMSubtarget *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "ARMTargetMachine.h"
#include "ARM.h"
+#include "ARMMachineFunctionInfo.h"
#include "ARMMacroFusion.h"
#include "ARMSubtarget.h"
#include "ARMTargetObjectFile.h"
ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
+MachineFunctionInfo *ARMBaseTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return ARMFunctionInfo::create<ARMFunctionInfo>(
+ Allocator, F, static_cast<const ARMSubtarget *>(STI));
+}
+
const ARMSubtarget *
ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
Attribute CPUAttr = F.getFnAttribute("target-cpu");
bool targetSchedulesPostRAScheduling() const override { return true; };
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
/// Returns true if a cast between SrcAS and DestAS is a noop.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// Addrspacecasts are always noops.
int VarArgsFrameIndex;
public:
- AVRMachineFunctionInfo()
- : HasSpills(false), HasAllocas(false), HasStackArgs(false),
- IsInterruptHandler(false), IsSignalHandler(false),
- CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {}
-
- explicit AVRMachineFunctionInfo(MachineFunction &MF)
+ AVRMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: HasSpills(false), HasAllocas(false), HasStackArgs(false),
CalleeSavedFrameSize(0), VarArgsFrameIndex(0) {
- unsigned CallConv = MF.getFunction().getCallingConv();
+ CallingConv::ID CallConv = F.getCallingConv();
- this->IsInterruptHandler = CallConv == CallingConv::AVR_INTR ||
- MF.getFunction().hasFnAttribute("interrupt");
- this->IsSignalHandler = CallConv == CallingConv::AVR_SIGNAL ||
- MF.getFunction().hasFnAttribute("signal");
+ this->IsInterruptHandler =
+ CallConv == CallingConv::AVR_INTR || F.hasFnAttribute("interrupt");
+ this->IsSignalHandler =
+ CallConv == CallingConv::AVR_SIGNAL || F.hasFnAttribute("signal");
}
MachineFunctionInfo *
#include "llvm/MC/TargetRegistry.h"
#include "AVR.h"
+#include "AVRMachineFunctionInfo.h"
#include "AVRTargetObjectFile.h"
#include "MCTargetDesc/AVRMCTargetDesc.h"
#include "TargetInfo/AVRTargetInfo.h"
return &SubTarget;
}
+MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return AVRMachineFunctionInfo::create<AVRMachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
//===----------------------------------------------------------------------===//
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
private:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
AVRSubtarget SubTarget;
unsigned PICLabelUId = 0;
public:
- CSKYMachineFunctionInfo(MachineFunction &) {}
+ CSKYMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
public:
HexagonMachineFunctionInfo() = default;
- HexagonMachineFunctionInfo(MachineFunction &MF) {}
+ HexagonMachineFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
+
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
#include "Hexagon.h"
#include "HexagonISelLowering.h"
#include "HexagonLoopIdiomRecognition.h"
+#include "HexagonMachineFunctionInfo.h"
#include "HexagonMachineScheduler.h"
#include "HexagonTargetObjectFile.h"
#include "HexagonTargetTransformInfo.h"
return TargetTransformInfo(HexagonTTIImpl(this, F));
}
+MachineFunctionInfo *HexagonTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
+ Allocator, F, STI);
+}
+
HexagonTargetMachine::~HexagonTargetMachine() = default;
namespace {
HexagonTargetObjectFile *getObjFileLowering() const override {
return static_cast<HexagonTargetObjectFile*>(TLOF.get());
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm
int VarArgsFrameIndex;
public:
- explicit LanaiMachineFunctionInfo(MachineFunction &MF)
+ LanaiMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: VarArgsFrameIndex(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "LanaiTargetMachine.h"
#include "Lanai.h"
+#include "LanaiMachineFunctionInfo.h"
#include "LanaiTargetObjectFile.h"
#include "LanaiTargetTransformInfo.h"
#include "TargetInfo/LanaiTargetInfo.h"
return TargetTransformInfo(LanaiTTIImpl(this, F));
}
+MachineFunctionInfo *LanaiTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return LanaiMachineFunctionInfo::create<LanaiMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
namespace {
// Lanai Code Generator Pass Configuration Options.
class LanaiPassConfig : public TargetPassConfig {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isMachineVerifierClean() const override {
return false;
}
int BranchRelaxationSpillFrameIndex = -1;
public:
- LoongArchMachineFunctionInfo(const MachineFunction &MF) {}
+ LoongArchMachineFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
public:
MSP430MachineFunctionInfo() = default;
- explicit MSP430MachineFunctionInfo(MachineFunction &MF)
- : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
+ MSP430MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "MSP430TargetMachine.h"
#include "MSP430.h"
+#include "MSP430MachineFunctionInfo.h"
#include "TargetInfo/MSP430TargetInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
return new MSP430PassConfig(*this, PM);
}
+MachineFunctionInfo *MSP430TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return MSP430MachineFunctionInfo::create<MSP430MachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
bool MSP430PassConfig::addInstSelector() {
// Install an instruction selector.
addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
}; // MSP430TargetMachine.
} // end namespace llvm
/// Mips target-specific information for each MachineFunction.
class MipsFunctionInfo : public MachineFunctionInfo {
public:
- MipsFunctionInfo(MachineFunction &MF) {}
+ MipsFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "Mips.h"
#include "Mips16ISelDAGToDAG.h"
+#include "MipsMachineFunction.h"
#include "MipsSEISelDAGToDAG.h"
#include "MipsSubtarget.h"
#include "MipsTargetObjectFile.h"
return TargetTransformInfo(MipsTTIImpl(this, F));
}
+MachineFunctionInfo *MipsTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return MipsFunctionInfo::create<MipsFunctionInfo>(Allocator, F, STI);
+}
+
// Implemented by targets that want to run passes immediately before
// machine code is emitted.
void MipsPassConfig::addPreEmitPass() {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
/// Returns true if a cast between SrcAS and DestAS is a noop.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// Mips doesn't have any special address spaces so we just reserve
SmallVector<std::string, 8> ImageHandleList;
public:
- NVPTXMachineFunctionInfo(MachineFunction &MF) {}
+ NVPTXMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "NVPTXAllocaHoisting.h"
#include "NVPTXAtomicLower.h"
#include "NVPTXLowerAggrCopies.h"
+#include "NVPTXMachineFunctionInfo.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXTargetTransformInfo.h"
#include "TargetInfo/NVPTXTargetInfo.h"
return new NVPTXPassConfig(*this, PM);
}
+MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
PB.registerPipelineParsingCallback(
[](StringRef PassName, FunctionPassManager &PM,
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
void registerPassBuilderCallbacks(PassBuilder &PB) override;
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
cl::init(false), cl::Hidden);
void PPCFunctionInfo::anchor() {}
-PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF)
+PPCFunctionInfo::PPCFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI)
: DisableNonVolatileCR(PPCDisableNonVolatileCR) {}
MachineFunctionInfo *
std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
public:
- explicit PPCFunctionInfo(const MachineFunction &MF);
+ explicit PPCFunctionInfo(const Function &F, const TargetSubtargetInfo *STI);
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "PPCTargetMachine.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "PPC.h"
+#include "PPCMachineFunctionInfo.h"
#include "PPCMachineScheduler.h"
#include "PPCMacroFusion.h"
#include "PPCSubtarget.h"
return Endianness == Endian::LITTLE;
}
+MachineFunctionInfo *PPCTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return PPCFunctionInfo::create<PPCFunctionInfo>(Allocator, F, STI);
+}
+
static MachineSchedRegistry
PPCPreRASchedRegistry("ppc-prera",
"Run PowerPC PreRA specific scheduler",
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isELFv2ABI() const { return TargetABI == PPC_ABI_ELFv2; }
bool isPPC64() const {
const Triple &TT = getTargetTriple();
SmallVector<Register, 8> SExt32Registers;
public:
- RISCVMachineFunctionInfo(const MachineFunction &MF) {}
+ RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
return I.get();
}
+MachineFunctionInfo *RISCVTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
TargetTransformInfo
RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(RISCVTTIImpl(this, F));
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override;
SparcMachineFunctionInfo()
: GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
IsLeafProc(false) {}
- explicit SparcMachineFunctionInfo(MachineFunction &MF)
- : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
- IsLeafProc(false) {}
+ SparcMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0),
+ IsLeafProc(false) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "SparcTargetMachine.h"
#include "LeonPasses.h"
#include "Sparc.h"
+#include "SparcMachineFunctionInfo.h"
#include "SparcTargetObjectFile.h"
#include "TargetInfo/SparcTargetInfo.h"
#include "llvm/CodeGen/Passes.h"
return I.get();
}
+MachineFunctionInfo *SparcTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SparcMachineFunctionInfo::create<SparcMachineFunctionInfo>(Allocator,
+ F, STI);
+}
+
namespace {
/// Sparc Code Generator Pass Configuration Options.
class SparcPassConfig : public TargetPassConfig {
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
/// Sparc 32-bit target machine
unsigned NumLocalDynamics;
public:
- explicit SystemZMachineFunctionInfo(MachineFunction &MF)
- : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
- RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
+ SystemZMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
+ : VarArgsFirstGPR(0), VarArgsFirstFPR(0), VarArgsFrameIndex(0),
+ RegSaveFrameIndex(0), FramePointerSaveIndex(0), NumLocalDynamics(0) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "SystemZTargetMachine.h"
#include "MCTargetDesc/SystemZMCTargetDesc.h"
#include "SystemZ.h"
+#include "SystemZMachineFunctionInfo.h"
#include "SystemZMachineScheduler.h"
#include "SystemZTargetTransformInfo.h"
#include "TargetInfo/SystemZTargetInfo.h"
SystemZTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(SystemZTTIImpl(this, F));
}
+
+MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>(
+ Allocator, F, STI);
+}
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool targetSchedulesPostRAScheduling() const override { return true; };
};
public:
VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
- explicit VEMachineFunctionInfo(MachineFunction &MF)
+ VEMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI)
: VarArgsFrameOffset(0), IsLeafProc(false) {}
MachineFunctionInfo *
#include "VETargetMachine.h"
#include "TargetInfo/VETargetInfo.h"
#include "VE.h"
+#include "VEMachineFunctionInfo.h"
#include "VETargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
return TargetTransformInfo(VETTIImpl(this, F));
}
+MachineFunctionInfo *VETargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return VEMachineFunctionInfo::create<VEMachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
namespace {
/// VE Code Generator Pass Configuration Options.
class VEPassConfig : public TargetPassConfig {
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isMachineVerifierClean() const override { return false; }
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool CFGStackified = false;
public:
- explicit WebAssemblyFunctionInfo(MachineFunction &) {}
+ explicit WebAssemblyFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
~WebAssemblyFunctionInfo() override;
MachineFunctionInfo *
};
} // end anonymous namespace
+MachineFunctionInfo *WebAssemblyTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return WebAssemblyFunctionInfo::create<WebAssemblyFunctionInfo>(Allocator, F,
+ STI);
+}
+
TargetTransformInfo
WebAssemblyTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(WebAssemblyTTIImpl(this, F));
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
bool usesPhysRegsForValues() const override { return false; }
public:
X86MachineFunctionInfo() = default;
+ X86MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
- explicit X86MachineFunctionInfo(MachineFunction &MF) {}
- explicit X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
+ X86MachineFunctionInfo(const X86MachineFunctionInfo &) = default;
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "X86.h"
#include "X86CallLowering.h"
#include "X86LegalizerInfo.h"
+#include "X86MachineFunctionInfo.h"
#include "X86MacroFusion.h"
#include "X86Subtarget.h"
#include "X86TargetObjectFile.h"
return new X86PassConfig(*this, PM);
}
+MachineFunctionInfo *X86TargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
+ STI);
+}
+
void X86PassConfig::addIRPasses() {
addPass(createAtomicExpandPass());
return TLOF.get();
}
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
+
bool isJIT() const { return IsJIT; }
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
public:
XCoreFunctionInfo() = default;
- explicit XCoreFunctionInfo(MachineFunction &MF) {}
+ explicit XCoreFunctionInfo(const Function &F,
+ const TargetSubtargetInfo *STI) {}
MachineFunctionInfo *
clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
#include "MCTargetDesc/XCoreMCTargetDesc.h"
#include "TargetInfo/XCoreTargetInfo.h"
#include "XCore.h"
+#include "XCoreMachineFunctionInfo.h"
#include "XCoreTargetObjectFile.h"
#include "XCoreTargetTransformInfo.h"
#include "llvm/ADT/STLExtras.h"
XCoreTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(XCoreTTIImpl(this, F));
}
+
+MachineFunctionInfo *XCoreTargetMachine::createMachineFunctionInfo(
+ BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const {
+ return XCoreFunctionInfo::create<XCoreFunctionInfo>(Allocator, F, STI);
+}
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+ MachineFunctionInfo *
+ createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+ const TargetSubtargetInfo *STI) const override;
};
} // end namespace llvm