return ret;
}
+static inline uint64_t
+intel_read_gpu_timestamp(int fd)
+{
+ struct drm_i915_reg_read reg_read = {};
+ const uint64_t render_ring_timestamp = 0x2358;
+ reg_read.offset = render_ring_timestamp | I915_REG_READ_8B_WA;
+
+ if (intel_ioctl(fd, DRM_IOCTL_I915_REG_READ, ®_read) < 0)
+ return 0;
+
+ return reg_read.val;
+}
+
/**
* A wrapper around DRM_IOCTL_I915_QUERY
*
#include <i915_drm.h>
+#include "common/intel_gem.h"
#include "dev/intel_device_info.h"
#include "perf/intel_perf.h"
#include "perf/intel_perf_query.h"
return (2.f * perf->devinfo.timestamp_frequency) / 1000000000ull;
}
-uint64_t read_gpu_timestamp(int drm_fd)
-{
- drm_i915_reg_read reg_read = {};
- const uint64_t render_ring_timestamp = 0x2358;
- reg_read.offset = render_ring_timestamp | I915_REG_READ_8B_WA;
-
- if (perf_ioctl(drm_fd, DRM_IOCTL_I915_REG_READ, ®_read) < 0) {
- PPS_LOG_ERROR("Unable to read GPU clock");
- return 0;
- }
-
- return reg_read.val;
-
-}
-
IntelDriver::IntelDriver()
{
/* Note: clock_id's below 128 are reserved.. for custom clock sources,
* again.
*/
if (gpu_timestamp_udw == 0 || (gpu_timestamp_udw + gpu_timestamp_ldw) < last_gpu_timestamp)
- gpu_timestamp_udw = read_gpu_timestamp(drm_device.fd) & 0xffffffff00000000;
+ gpu_timestamp_udw = intel_read_gpu_timestamp(drm_device.fd) & 0xffffffff00000000;
uint64_t gpu_timestamp = gpu_timestamp_udw + gpu_timestamp_ldw;
uint64_t IntelDriver::gpu_timestamp() const
{
return intel_device_info_timebase_scale(&perf->devinfo,
- read_gpu_timestamp(drm_device.fd));
+ intel_read_gpu_timestamp(drm_device.fd));
}
} // namespace pps
namespace pps
{
-int perf_ioctl(int fd, unsigned long request, void *arg)
-{
- int ret;
-
- do {
- ret = ioctl(fd, request, arg);
- } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
-
- return ret;
-}
-
IntelPerf::IntelPerf(const int drm_fd)
: drm_fd {drm_fd}
, ralloc_ctx {ralloc_context(nullptr)}